JP2780674B2 - Nonvolatile semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device, and more particularly to a flash nonvolatile semiconductor memory device in which a plurality of electrically erasable and writable data memory cell transistors are arranged.

[0002]

2. Description of the Related Art A memory cell is formed of a field effect transistor such as a field effect transistor having a floating gate, which can electrically set a threshold voltage and can erase and write data (hereinafter referred to as a memory cell transistor). ), A plurality of these memory cell transistors,
In a nonvolatile semiconductor memory device arranged in the column direction,
Data can be collectively erased electrically, and is attracting attention as a flash memory.

In such a flash type nonvolatile semiconductor memory device, data erasing is generally performed by applying a high voltage to a source by setting a control gate of all memory cell transistors to a ground potential and a drain to a floating state, and applying a high voltage to the source. The threshold voltage is lowered by extracting electrons from the floating gate by the tunnel effect due to the electric field between the control gates.

When such an erase pulse applying operation for batch erasing is performed, the time for applying a high voltage to the source becomes longer, and even if this time is appropriate, the thickness of the gate insulating film varies. , Small defects, variations in the size of the grain boundaries of the floating gate, etc., lower the threshold voltage,
An over-erased state in which the word line, that is, the control gate is in the on-cell state even when the control gate is at the non-selection level of the ground potential, easily occurs. In such a case, an on-cell current always flows through the digit line to which the over-erased memory cell transistor is connected, and normal data cannot be read.

Therefore, it is general to determine whether or not a memory cell transistor in an over-erased state exists after application of an erasing pulse. Since it takes too much time to determine the over-erased state by a normal data reading circuit, after applying the erasing pulse, a batch read is performed to determine whether or not a memory cell in the over-erased state exists. There is also an example (see, for example, JP-A-4-222994).

FIG. 5 shows an example (first example) of a conventional nonvolatile semiconductor memory device in which a batch read is performed after a batch erase pulse is applied to determine an over-erased state.

This nonvolatile semiconductor memory device has a plurality of memory cell transistors MC11x each having a floating gate, and a memory cell formed of a field effect transistor capable of electrically setting a threshold voltage and capable of erasing and writing data.
To MCmnx are arranged in a matrix in the row direction and the column direction, and is connected to the control gate of each memory cell transistor of the corresponding row provided corresponding to each row of the plurality of memory cell transistors MC11x to MCmnx. A plurality of word lines WL1 to WLm, a plurality of digit lines DL1 to DLn provided corresponding to each of the plurality of memory cell transistors MC11x to MCmnx and connected to a drain of each memory cell transistor in the corresponding column; A source line SL connected to the source of each of the memory cell transistors MC11x to MCmnx, and an erase voltage Ve having a predetermined voltage and a pulse width applied to the source line SL during an erase pulse application operation in accordance with an erase control signal ER. Except when the source line SL is ground potential Source voltage supply circuit 6, a word line voltage generation circuit 3x for generating a word line supply voltage during various operations in accordance with a voltage switching signal VRS, control signals ARS and ARN, a row address signal ADr, and a word line voltage generation circuit In response to the output voltage of 3x, one word line among a plurality of word lines WL1 to WLm is selected during a normal read operation and set to a selected level of a normal power supply voltage Vcc level, and one word line is set during a write operation. A plurality of word lines WL1 are selected and set to a writing voltage higher than the power supply voltage Vcc during the erase pulse applying operation and the over-erasing determining operation.
Row decoder 2x for setting all .about.WLm to the ground potential level
And control signals ACS and ACN and a column address signal ADc.
In response to this, one of a plurality of digit lines DL1 to DLn is selected during a normal read operation and a write operation, and a plurality of digit lines DL1 to DLn are selected when an erase pulse is applied.
The column decoder 4 and the column selection circuit 5 select all of the plurality of digit lines DL1 to DLn during the over-erasure determination operation by setting all of them to the non-selection state and the floating state, and are selected during the normal read operation and the over-erasure determination operation. Sense amplifier 8 for detecting and determining the level of the current flowing through the digit line
A write circuit 7x for supplying a predetermined write voltage to a selected digit line during a write operation; a write circuit 7x during a write operation; and a sense amplifier 8 connected to the selected digit line at other times. And a switching circuit 9.

In this nonvolatile semiconductor memory device, row decoder 2x includes inverter IV21 corresponding to each bit of row address signal ADr, NAND type logic gates G21 and G22, and N corresponding to each word line.
AND-type logic gate G23x and transistor Q2
1 and Q22, and the column decoder 4, like the row decoder 2x, includes an inverter IV41 corresponding to each bit of the column address signal ADc, NAND logic gates G41 and G42, and digit lines. Corresponding N
AND-type logic gate G43 and inverter IV42
And is provided.

Next, the operation of the nonvolatile semiconductor memory device will be described mainly on the erasing operation.

The erasing operation is performed by first controlling the control signals ARN and AC.
N are both low, all word lines WL1 to WLm are at the unselected level ground potential, and digit lines DL1 to DLn
All are set to a non-selection state and a floating state, the erase control signal ER is set to an activation level, and a predetermined pulse width and a predetermined high voltage for erasing voltage Ve are supplied to the source line SL. As a result, the memory cell transistors MC11x to MCmn
In all x, electrons are extracted from the floating gate by the tunnel effect due to the electric field between the source and the control gate, the threshold voltages of these memory cell transistors are lowered, and the memory cell transistor is in an erased state (erasing pulse applying operation).

Next, in order to determine whether or not there is a memory cell transistor in an overerased state, control signals ARN, A
CS is set to a low level, the control signal ACN is set to a high level, all the word lines WL1 to WLm are set to the non-selection level ground potential, all of the digit lines DL1 to DLn are set to a selected state, and all of these digit lines are switched by the switching circuit 9. Connect to sense amplifier 8. As a result, the control gates of the memory cell transistors MC11x to MCm
nx are all selected and connected to the sense amplifier 8, and their current levels are determined (over-erase determination operation).

The sensitivity of the sense amplifier 8 remains the same as in the normal read operation for determining the current level of the "1" data in the write state and the "0" data in the erase state of the 1-bit memory cell transistor. Therefore, if at least one of the memory cell transistors MC11x to MCmnx has an overerased state, the current level is detected,
A signal having a level indicating that a memory cell transistor in an overerased state exists is output from the sense amplifier 8.

In this nonvolatile semiconductor memory device, when it is determined that a memory cell transistor in an overerased state exists, the memory cell transistor MC1 is returned to restore the memory cell transistor in the overerased state to a normal erased state.
Writing is performed on all of 1x to MCmnx by the tunnel effect, and the above-described erase pulse applying operation and over-erase determining operation are repeated again. When it is determined that there is no over-erased state, the erasing operation ends.

The write operation (write operation after over-erase determination) when it is determined that an over-erase state exists exists, the control signals ARS and ACN are set to low level, ARN is set to high level, and all the word lines WL1 to WL are set. In the selected state, all the digit lines DL1 to DLn are set to a non-selected state and a floating state, and a high voltage from the word line voltage generation circuit 3x is applied to all the selected word lines. At this time, since the source line SL is at the ground potential, a high voltage is applied between the control gate and the source of the memory cell transistors MC11x to MCmnx, electrons are injected into the floating gate by a tunnel effect, and these memory cell transistors , The threshold voltage increases, and writing is performed.

After the over-erase determination, a write operation is performed, followed by an erase pulse application operation and an over-erase determination operation. When it is determined that there is no over-erase state in the over-erase determination operation, the erase operation is terminated. When it is determined that there is an overwrite, the operation from the write operation after the overerase determination is repeated.

In this nonvolatile semiconductor memory device, the over-erase discrimination operation after the erase pulse application operation and the write operation after the over-erase judgment are performed by the memory cell transistors MC11x to MC11.
mnx can be performed collectively, so that the time required for the erasing operation can be shortened.

Normally, a nonvolatile semiconductor memory device is rarely used alone, and is often used in a higher-level system in combination with a microprocessor or the like.
The power supply voltage of a high-level system such as a mamicroprocessor is wide, for example, from about 1.8 V to about 5 V, depending on the application, and the nonvolatile semiconductor memory device also receives the power supply voltage from the high-level system. Depending on how it works. However, during a writing operation or an erasing pulse application operation, a voltage higher than the power supply voltage, for example, 10
V, 12 V, etc. are required, and if these high voltages are generated from the power supply voltage, a circuit for that purpose becomes large-scale and the chip area increases. (Hereinafter referred to as a power supply voltage for high voltage) (hereinafter, referred to as a power supply voltage for high voltage).

In a nonvolatile semiconductor memory device, a high voltage higher than a normal power supply voltage is required because a voltage (for example, about 10 V) supplied to a control gate (word line) of a memory cell transistor and a drain voltage during a write operation. (For example, about 6 V) supplied to the (digit line),
A voltage (for example, a voltage higher by about 1 V than a normal selection level) supplied to the control gate during the write verify operation, a voltage (for example, 10 V) supplied to the source (source line) during the erase pulse applying operation, and the like.

These high voltages are generated from a high-voltage power supply voltage, and the circuit configuration thereof is as shown in FIGS. 6A and 6B (for example, Japanese Patent Application Laid-Open No. 61-255048). Gazette, JP-A-5-507576).

The circuit shown in FIG. 6A has one end connected to a resistor R35 for receiving a power supply voltage Vpp for high voltage, one end connected to the other end of the resistor R35, and the other end connected to a ground potential point. A resistor R36 and a resistor R receiving a power supply voltage Vpp at one end.
37, an N-channel transistor Q3 connecting the gate and the drain to the other end of the resistor R37, connecting the source to the connection point of the resistors R35 and R36, and connecting the substrate to the ground potential point.
6, a P-channel transistor Q37 whose source and substrate are connected to the source of the transistor Q36, one end is connected to the gate and drain (first reference potential point) of the transistor Q37, and the other end is connected to the ground potential point. Resistance R3
8, an N-channel transistor that receives the power supply voltage Vpp at the drain, connects the gate to the gate and drain (second reference potential point) of the transistor Q36, connects the source to the voltage output terminal, and connects the substrate to the ground potential point Q38,
A P-channel transistor Q39 having its source and substrate connected to a voltage output terminal, its gate connected to the gate and drain of transistor Q37, and its drain connected to a ground potential point.
And a configuration including

In this circuit, the transistors Q36, Q3
8 and the threshold voltages of the transistors Q37 and Q39 are equal to each other.
By making the resistance of the resistor 38 sufficiently larger than the resistance of the resistors R35 and R36, the output voltage Vo is reduced by the resistors R35 and R3.
6 and a constant output voltage Vo can be obtained even if the output current fluctuates.

The circuit shown in FIG. 6B corresponds to the circuit shown in FIG.
In which the resistors R35 and R35 are eliminated. In this circuit, the output voltage Vo is determined by the resistors R37 and R38.
And the threshold voltage of the transistors Q36 and Q37, the threshold voltage of the transistor is usually
The output voltage Vo is determined by the manufacturing process,
7, Set by R38.

In these circuits, the transistor Q3
8, the voltage applied between the gate of Q39, the source, the drain, and the substrate is Vpp / 2 or less when the output voltage Vo is の of the power supply voltage Vpp.
Are applied except for Vpp / 2, a voltage higher than Vpp / 2 is applied.
Reference numeral 39 denotes a high breakdown voltage transistor.

In the nonvolatile semiconductor memory device, all "0" (all-on cell) data, all "1" (all-off cell) data, and checkerboard data in which data of adjacent memory cell transistors are different from each other. Testing for inter-bit interference is indispensable. Of these, writing of all “0” data remains in the collectively erased state, and writing of all “1” data can be performed by selecting all word lines and all bit lines and applying a predetermined voltage to each. However, in the case of a checkerboard pattern, it is necessary to devise a device, and writing one bit at a time takes too much time. For example, as described in JP-A-5-334900, a plurality of words are required. There is an example (second example) in which every other line and digit line are selected, and selection and non-selection are switched. However, reading of these test pattern data is performed for each bit.

[0025]

In the above-mentioned conventional nonvolatile semiconductor memory device, in the first example, the batch erasing operation
All of the plurality of word lines WL1 to WLm are set to the non-selection level ground potential, and all of the plurality of digit lines DL1 to DLn are set to a non-selected state and a floating state. In this configuration, electrons are extracted from the floating gates of the memory cell transistors MC11x to MCmnx by a tunnel effect, so that the application time of the erasing voltage Ve and the manufacturing process of the gate insulating film and the like are reduced. The rate of occurrence of memory cell transistors in the over-erased state increases due to the variation in the memory cell transistors, and after the erase pulse applying operation, a collective over-erased determination operation is performed on all the memory cell transistors. If it is determined, writing by the tunnel effect is performed for all memory cell transistors at once. There, the erase pulse application operation, make bulk over-erase judgment operation, repeating the operation that, there is a disadvantage that the time to complete erase longer.

The voltage supplied to the word line and the digit line at the time of various operations is generated from the high-voltage power supply voltage Vpp in consideration of compatibility with the host system. N-channel and P-channel transistors are connected in series between the transistor and a ground potential point, and the gates of these transistors are applied with a reference voltage obtained by adding or subtracting about the threshold voltage of these transistors from the output voltage Vo. Therefore, when the output voltage Vo is other than Vpp / 2, Vpp / V is applied between the gate and the source, drain and substrate of these transistors.
Since a voltage higher than 2 is applied, there is a problem that these transistors need to be used for high breakdown voltage.

Further, in the second example, in order to write a checkerboard test data pattern, a plurality of word lines and digit lines are alternately selected, and selection and non-selection are switched. Therefore, although the writing time of the data pattern is shortened, the reading and confirmation of the data pattern is performed on a bit-by-bit basis, so that there is a problem that the entire test time including the reading becomes long. Further, the same problem exists for all “0” data and all “1” data.

A first object of the present invention is to provide a nonvolatile semiconductor memory device capable of shortening a time until completion of erasing. A second object of the present invention is to provide a non-volatile semiconductor memory device which performs various operations from a high-voltage power supply voltage. A third object of the present invention is to provide a nonvolatile semiconductor memory device in which a transistor for high withstand voltage need not be used in a circuit for generating a voltage at the time of reading, and a read operation by a test pattern such as a checkerboard pattern is performed. It is an object of the present invention to provide a nonvolatile semiconductor memory device capable of shortening the entire test time including the above.

[0029]

A nonvolatile semiconductor memory device according to the present invention comprises a plurality of memory cell transistors arranged in a matrix in a row direction and a column direction and capable of electrically erasing and writing data. And a plurality of word lines provided corresponding to each row of the memory cell transistors and connected to the control gates of the memory cell transistors of the corresponding row, and provided corresponding to each column of the plurality of memory cell transistors. A plurality of digit lines connected to the drains of the memory cell transistors in a column to be connected, a source line connected to the source of each of the plurality of memory cell transistors, and a first voltage during an erase pulse applying operation and an over-erasing determining operation A word line voltage generating circuit for generating various voltages corresponding to various operations including the second voltage of At the time of the erase pulse applying operation and the over-erase discriminating operation, all of the plurality of word lines are selected and the first and second voltages are supplied from the word line voltage generating circuit. A row decoder for selecting a predetermined word line among the plurality of word lines according to a row address signal and supplying a corresponding voltage from the word line voltage generation circuit; and an erase pulse of a predetermined voltage during the erase pulse applying operation. And a source potential supply circuit that supplies the source line to the ground potential except during the erase pulse applying operation, and deselects and floats all of the plurality of digit lines during the erase pulse applying operation. State during the over-erase discriminating operation, and selects all of the plurality of digit lines to perform a normal read and write operation. A digit line selection circuit for selecting a predetermined digit line among the plurality of digit lines in accordance with the address signal, and a digit line selection circuit for selecting the digit line among the plurality of digit lines during the over-erase determination operation and the normal read operation. A sense amplifier for determining a signal level; and a write circuit for supplying a predetermined voltage to a selected digit line of the plurality of digit lines during the normal write operation.

Further, each of the plurality of memory cell transistors is formed of an N-channel type field effect transistor having a floating gate and connects the substrate to a ground potential point. A positive first voltage is applied to the control gate and an erase pulse is applied to the source to inject hot carriers due to avalanche breakdown between the source and the substrate into the floating gate to collectively collect data of all of the plurality of memory cell transistors. At the time of over-erasing determination operation after the batch erasing, a positive second voltage is applied to the control gates of all of the plurality of memory cell transistors, and all of the plurality of digit lines are selected, and these sense lines are used by the sense amplifier. Memory cell transistor in over-erased state by determining the level of the total current flowing through the digit line It constituted whether as collectively determined.

The supplied power supply voltage is composed of a normal power supply voltage and a high-voltage power supply voltage higher than the normal power supply voltage, and generates various voltages in the word line voltage generation circuit and the write circuit. A first and second circuit connected in series between the high-voltage power supply voltage supply terminal and a ground potential point;
And an N-channel type first transistor having a gate connected to a series connection point of the first and second resistors, and a drain connected to the high potential side of the high voltage power supply voltage and the ground potential point. A transistor, a drain connected to the source of the first transistor, a source connected to the output terminal of the various voltages, an N-channel type second transistor receiving a first reference voltage at a gate, and a drain connected to the high level. A P-channel type third transistor connected to the power supply voltage supply terminal for voltage and the low potential side of the ground potential point, the source connected to the output terminal of the various voltages, and the gate receiving the second reference voltage; The drain of the second transistor is directly connected to the high-potential side of the high-voltage power supply voltage supply terminal and the ground potential point, and the drain of the third transistor is connected to the high-voltage power supply. The first transistor is connected to the drain of the third transistor, and the drain of the first transistor is connected to the power supply voltage supply terminal for high voltage and the ground. It is configured as a P-channel type which is connected to the lower potential side of the potential points and whose gate is connected to the series connection point of the first and second resistors.

Also, an OR circuit for performing an OR operation on all the signals of the plurality of digit lines and a pull-up resistor having a resistance value sufficiently larger than the on-resistance of the memory cell transistor are provided. And a pull-up circuit for supplying a normal power supply voltage.
And selecting all of the plurality of digit lines to connect the pull-up circuit, disconnect the sense amplifier from the plurality of digit lines, and output the one word line to the one word line by the output signal of the OR circuit. Erased state determining means for collectively determining whether the connected memory cell transistor is in the erased state is provided.

Each of the row decoder and the digit line selection circuit includes odd / even selection means for selecting all of the odd-numbered only and all of the even-numbered only ones of the plurality of word lines and the plurality of digit lines. And an OR circuit that performs an OR operation on all of the signals, and a pre-up circuit that has a pull-up resistor having a resistance value sufficiently larger than the ON resistance of the memory cell transistor and supplies a normal power supply voltage to the selected digit line through this resistor. And
A plurality of memory cell transistors are arranged in a checkered data pattern in an erase state and a write state so that adjacent ones are different from each other. In a read operation, all odd-numbered word lines are selected and written to connect to these word lines. All the currents of the memory cell transistors in the state and all the even-numbered word lines are selected, and all the currents of the memory cell transistors in the write state connected to these word lines are collectively detected and determined by the sense amplifier, and one word line is determined. The signal level of the digit line corresponding to each of the erased memory cell transistors connected to the word line is selected by the OR circuit, and the OR circuit further determines each of the plurality of digit lines with the ground potential. Connected to the point and have a resistance value sufficiently larger than the resistance for pull-up. A resistor for down period, and includes an OR gate for performing an OR operation of said plurality of digit lines all signals.

[0034]

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

In this embodiment, a plurality of memory cell transistors MC11 to MCmn which form a memory cell by a field effect transistor having a floating gate, which can electrically set a threshold voltage and can erase and write data are arranged. Cell array 1 arranged in a matrix in the direction and the column direction, and a plurality of memory cell transistors MC11 to MCm
n and a plurality of word lines WL1 to WLm connected to the control gates of the memory cell transistors in the corresponding row and provided in correspondence with the columns of the memory cell transistors MC11 to MCmn, respectively. And a plurality of digit lines DL1 to DL connected to respective drains of memory cell transistors in a corresponding column.
n and a plurality of memory cell transistors MC11 to MCm
n, a source line SL connected to each source, and various voltages corresponding to various operations including a first voltage during an erase pulse applying operation and a second voltage during an over-erase determining operation according to a voltage switching signal VRS. Word line voltage generating circuit 3
At the time of the erase pulse applying operation and the over-erase judging operation according to the control signal ARS and the row address signal ADr, all the plurality of word lines WL1 to WLm are selected and the first and second voltages from the word line voltage generation circuit 3 are selected. The row decoder 2 supplies one of the word lines designated by the row address signal ADr and supplies the corresponding voltage from the word line voltage generating circuit 3 during normal read and write operations, and the erase control signal ER. A predetermined voltage and
A source potential supply circuit 6 for supplying an erase voltage Vs having a predetermined pulse width to the source line SL and setting the source line SL to the ground potential except during an erase pulse application operation;
According to N and the column address signal ADc, all of the plurality of digit lines DL1 to DLn are set to a non-selected state and a floating state during an erase pulse applying operation, and all of the plurality of digit lines DL1 to DLn are selected during an overerase determination operation to perform a normal read operation and During the write operation, the column address signal AD
a column decoder 4 and a column selection circuit 5 for selecting one digit line designated by c, and a sense amplifier for detecting and determining the current level of the selected digit line at the time of over-erasure determination operation and normal read operation. 8, a write circuit 7 for supplying a predetermined voltage to a digit line selected during a normal write operation, and a write circuit 7 connected to the selected digit line during a normal write operation according to a write control signal W. The switching circuit 9 connects the sense amplifier 8 to the column selection circuit 5 except during the writing operation.

In this embodiment, the row decoder 2 includes an inverter IV21 corresponding to each bit of the row address signal ADr, and a NAND type logic gate G21,
G22, a NAND-type logic gate G23 corresponding to each word line, and transistors Q21 and Q22, which are different from the conventional row decoder 2x shown in FIG. Control signal A to G23x
In this embodiment, the control signal ARN is not input to the logic gate G23 while the RN is input, and the column decoder 4 and the column selection circuit 5 have the same configuration as the conventional example.

In this embodiment, the memory cell transistors MC11 to MCmn are formed of N-channel type field effect transistors having floating gates and transistors, and the substrate thereof is at the ground potential. When the control signals ARS and ACN are set to low level, a positive first voltage (for example, the normal power supply voltage is set to 3.3 V) is applied to all control gates of the plurality of memory cell transistors MC11 to MCmn, that is, all the word lines WL1 to WLm. Erasing voltage Vs (for example, 10 V) is applied to the source (source line SL).
Hot carriers due to avalanche breakdown between the substrates are injected into the floating gates, and these memory cell transistors MC11-MC
All Cmn are collectively erased.

By such an erase pulse applying operation, the threshold voltages of the memory cell transistors MC11 to MCmn are not affected by the threshold voltage before erasing, but depend on the first voltage for a predetermined constant value. It is possible to prevent the value from converging to a value and causing an overerased state. The over-erased state is considered to be rather defective, and therefore, the erase pulse applying operation and the subsequent over-erased determination operation can be completed only once.

The over-erase determination operation is performed by controlling the control signals ARS, AC
S is set to a low level, the control signal ACN is set to a high level, and all the word lines WL1 to WLm are selected, and a positive second voltage (for example, a voltage slightly lower than the first voltage) is applied from the word line voltage generation circuit 3. Supply and digit lines DL1 to DL1
All Ln are selected and connected to the sense amplifier 8 by the switching circuit 9. Therefore, the memory cell transistors MC11 to MC11
All the MCmns are selected, and the sense amplifier 8 detects and determines the entire current level.

Since the sensitivity of the sense amplifier 8 remains the same as that in the normal read operation for determining the current level of the "1" and "0" data of the 1-bit memory cell transistor, the memory cell transistors MC11 to MCmn If any one of them has an over-erased state, the current level is detected, and it is determined that there is an over-erased state.

In this embodiment, as described above, the erase pulse application operation and the subsequent over-erasure determination operation need only be performed once, and these operations can be performed collectively for all the memory cell transistors. The time until erasure is completed can be shortened.

In this embodiment, the word line voltage generating circuit 3 and the writing circuit 7 are designed to convert the high-voltage power supply voltage Vpp into
Various voltages to be supplied to word lines and digit lines are generated.

FIGS. 2A and 2B show specific examples of circuits for generating various voltages from the high-voltage power supply voltage Vpp. In the circuit shown in FIG. 2A, a voltage lower than 1/2 of the power supply voltage Vpp, for example, a normal power supply voltage (Vcc) is 3.
The circuit shown in FIG. 2B is used to generate various voltages at about 3 V or less.
It is used to generate a voltage higher than / 2, for example, a drain voltage during a write operation when the normal power supply voltage (Vcc) is about 5 V.

The circuit shown in FIG. 2A has a resistor R31 receiving a power supply voltage Vpp at one end, an N-channel type having a gate and a drain connected to the other end of the resistor R31, and a substrate connected to a ground potential point. A transistor Q31; a P-channel transistor Q32 having a source and a substrate connected to the source of the transistor Q31;
A resistor R32 connected to the gate and the drain and the other end connected to the ground potential point, a resistor R33 receiving the power supply voltage Vpp at one end, one end connected to the other end of the resistor R33, and the other end connected to the ground potential point. A resistor R34 and a power supply voltage V
pp, the gate of which is connected to the connection point of the resistors R33 and R34 and the substrate is connected to the ground potential point; the transistor Q33 of the N-channel type; the drain is connected to the source of the transistor Q33; 1 reference potential point), the source is connected to the voltage output terminal, and the substrate is connected to the ground potential point. The N-channel transistor Q34 is connected to the source and the substrate to the voltage output terminal. A P-channel transistor Q35 connected to the drain (second reference potential point) and the drain connected to the ground potential point.

In this circuit, the output voltage Vo is
As in the circuit shown in FIG. 7B, the resistance is determined by the resistors R31 and R32. Further, the drain-to-drain voltage (V5) of the transistors Q34 and Q35 can be reduced by the resistors R33 and R34 and the transistor Q33. For example, even if the output voltage Vo is near 0 V, this voltage is reduced to V
pp / 2, the transistors Q33 to Q33
The voltage between the gate and the source / drain of Q35 and the substrate can be suppressed to Vpp / 2 or less (the potential immediately below the gate insulating film of the substrate is a source potential and a drain because a current flows between the source and the drain). Therefore, these transistors need not be of a high breakdown voltage type.

In the circuit shown in FIG. 2B, a transistor Q33a for reducing the voltage between the drains of the transistors Q34 and Q35 is provided between the drain of the transistor Q35 and the ground potential point. In this circuit, for example, even if the output voltage Vo is near Vpp, the resistance R3
3, R34 and the transistor Q33a, the voltage between the drains of the transistors Q34, Q35 is set to about Vpp / 2, and the voltage between the gates, the source, the drain, and the substrate of the transistors Q33a, Q34, Q35 is Vpp / 2.
Therefore, these transistors need not be of a high breakdown voltage type.

FIG. 3 is a circuit diagram showing a second embodiment of the present invention.

The second embodiment differs from the first embodiment shown in FIG. 1 in that a resistance R10 having a value sufficiently larger than the resistance of the memory cell transistor when "0" data is written (on-cell state). During the all- "0" data read test operation, the selected digit line is connected to the normal power supply voltage V
a pull-up circuit 10 for pulling up in the cc direction;
An OR circuit 11 having a gate G11 and performing an OR operation on all the signals of the digit lines DL1 to DLn is provided. The switching circuit 9a is used to switch one of the write circuit 7, the sense amplifier 8 and the pull-up circuit 10 to various operations. This is a circuit which is selected in accordance with the above and connected to the column selection circuit 5.

Next, the operation of this embodiment will be described mainly on the data read operation.

For all "0" data, all of the memory cell transistors MS11 to MCmn remain in the ON state, that is, the batch erase state. This reading of all "0" data is performed by setting the control signals ARS and ACN to a high level, setting the control signal ACS to a low level, and setting the digit lines DL1 to DL
Ln are all selected, the pull-up circuit 10 is connected by the switching circuit 9a, one of the word lines WL1 to WLm is selected according to the row address signal ADr, and the word line voltage generation circuit 3 outputs a voltage for ON cell determination ( For example, when the word line selection level during a normal read operation is the normal power supply voltage Vcc level, a voltage equal to or slightly lower than this level is supplied.

As a result, a memory cell transistor (MC) connected to one selected word line (eg, WL1)
11 to MC1n) All the drains are connected to the input terminals of the OR gate G11 through the corresponding digit lines (DL1 to DL), and these digit lines (DL1 to DL1) are connected.
n) The pull-up circuit 10 is connected to all of them. Therefore, these memory cell transistors (MC11 to MC1
n) If all the data "0" is normally written (that is, the on-cell state and the erased state), all the digit lines (DL1 to DLn) are at the low level of the ground potential, and the OR gate G11 is turned on. The output signal goes low, and these memory cell transistors (MC11 to MC11)
It can be seen that the writing and reading of "0" data in 1) is normal.

The memory cell transistors (M
If any one of C11 to MC1n) is in the off state, the corresponding digit line is pulled up to the power supply voltage Vcc level by the pull-up circuit 10, so that O
The output signal of the R gate G11 becomes high level, and it can be determined that some of these memory cell transistors (MC11 to MC1n) cannot normally write and read data of "0".

By performing the same operation for all of the word lines WL1 to WLm, a "0" data read test of all memory cell transistors can be performed.

In this embodiment, a "0" data read test of all the memory cell transistors connected to one word line can be performed at one time.
The test time can be greatly reduced as compared with the case of performing the test for each bit.

After the erase pulse application operation, in addition to the over-erase determination operation, it is necessary to confirm whether all the memory cell transistors are in the erased state. Thus, the test can be performed in the same manner as in the above-described test for reading all “0” data.

FIG. 4 is a circuit diagram showing a third embodiment of the present invention.

This embodiment differs from the second embodiment shown in FIG. 3 in that digit lines DL1 to DLn connected to the input terminals of the OR gate of the OR circuit 11 and the ground potential point, respectively. And resistors R11o and R11e (o is an odd number, e indicates the following, the same applies hereinafter) having a resistance value sufficiently larger than the resistance R10 of the pull-up circuit 10 to form an OR circuit 11a, and the word lines WL1 to WL1 of the row decoder 2 are connected. One input is further added to the logic gate G23 corresponding to each of the WLm and the odd-numbered logic gate is set to G23o, the even-numbered logic gate is set to G23e, and the odd-numbered signal ODr and the logic are added to the added input terminal of the logic gate G23o. The even-numbered signal EVr is input to the added input terminal of the gate G23e to form the row decoder 2a, and the digit lines DL1 to DLn of the column decoder 4 are provided. Logic gate G corresponding to each
One more input is added to S43, and an odd-numbered logic gate is added to S43.
o, the even-numbered logic gate is G43e, and the logic gate G
An odd-numbered signal ODc is connected to the input terminal 43o, and an even-numbered signal EV is connected to the input terminal to which the logic gate G43e is added.
This is in that the column decoder 4a is formed by inputting c.

In this embodiment, to write a checkerboard data pattern, the control signals ARS and ACN are first set to low level to select all of the word lines WL1 to WLm and to apply a positive first voltage. Digit lines DL1 to DL
All of Ln are in a non-selected state and a floating state, an erasing voltage Vs is applied to the source line SL, and all of the memory cell transistors MC11 to MCmn are injected with hot carriers due to avalanche breakdown into the floating gate to be in an erasing state (all “ 0 "write).

Subsequently, the control signals ARS and ACS are set to low level, the control signal ACN is set to high level, and the odd-numbered signal OD is set.
r and ODc are set to low level, and the even-numbered signals EVr and EVc are set to high level to select all of the even-numbered (WLe, DLe) of the word lines WL1 to WLm and the digit lines DL1 to DLn. Then, a write voltage is applied to the digit lines, and "1" data is written to all even-numbered memory cell transistors MCee in both rows and columns. Subsequently, the odd-numbered signal OD remains unchanged while the control signal remains unchanged.
r and ODc are set to a high level, the even-numbered signals EVr and EVc are set to a low level, and all the odd-numbered (WLo, DLo) of the word lines WL1 to WLm and the digit lines DL1 to DLn are selected. Then, a write voltage is applied to the digit lines, and "1" data is written to all the odd-numbered memory cell transistors MCoo in both the row and the column.

As a result, "1" data is stored in the even-numbered and odd-numbered memory cell transistors MCee and the odd-numbered and odd-numbered memory cell transistors MCoo in the rows and columns.
A checkerboard data pattern is written by writing "0" data in eo and the odd-numbered and even-numbered memory cell transistors MCoe.

Next, the operation of reading the checkered pattern data will be described.

Since the memory cell transistors to which "1" data has been written are in the off-cell state, data reading of these memory cell transistors is performed in the same manner as writing of "1" data by first reading all even-numbered word lines. And all the digit lines are selected, a voltage of the same level as or slightly higher than the selected level in the normal read operation is supplied to all the selected word lines, and all the selected digit lines are connected to the sense amplifier 8. Then, with this sense amplifier 8,
The total current level of the even-numbered memory cell transistors in both the row and the column is detected and determined.

Subsequently, similarly, all the current levels of the odd-numbered memory cell transistors in both the row and the column are detected and determined.

Subsequently, "0" data is read.
Since the memory cell transistor in which the “0” data is written is in the on-cell state, the “0” data of the memory cell transistor connected to one digit line can be determined only one by one. Also, the sense amplifier 8 can determine only one by one.

Therefore, in the present embodiment, the pull-up circuit 10 and the O-up circuit 10 are provided so that the "0" data of the memory cell transistor connected to one word line can be simultaneously read and determined.
An R circuit 11a is provided.

The word lines are selected one by one to apply a predetermined read voltage, for example, a voltage approximately equal to or slightly lower than the voltage of the selected level for normal read. If the selected word line is an odd number, an even number is applied. If it is an even-numbered digit line, an odd-numbered digit line is selected, and a pull-up circuit 10 is connected through a column selection circuit 5 and a switching circuit 9a.

As a result, if the memory cell transistor connected to the selected digit line is normally in the "0" data state (on-cell state), a low level of the ground potential level is applied to the input terminal of OR gate G11. Appearing, if it is not in the state of "0" data normally, that is, if it is in the state of "1" data (off cell), it is pulled up to the high level of the power supply voltage Vcc by the pull-up circuit 10 and is not selected. Since the digit line in the state is pulled down to the ground potential level low by the pull-down resistors (R11o, R11e), the OR gate G
The output terminal 11 is set to a low level when all of the selected memory cell transistors are normally in the “0” data state, and set to a high level when at least one of the selected memory cell transistors has the “1” data state. It is possible to determine whether all the memory cell transistors are in the “0” data state.

In the above description, the writing of "1" data is performed first for the even-numbered rows and columns, and then for the odd-numbered rows, and the reading is performed in the same order. The order of even and odd may be reversed. After the batch erasure, "1" data is written into odd and even numbers (or vice versa) of rows and columns, and "1" data is subsequently written into even and odd numbers (or vice versa). Then, the above-mentioned checkerboard pattern can be a checkerboard pattern in which "1" and "0" are reversed.

In this embodiment, writing of all "1" (all-off cells) data is easy, and reading of the data can be determined through the sense amplifier 8. Further, the OR circuit 11a of this embodiment has all
It can also be used for reading and determining data.

As described above, in the second and third embodiments, all "0", all "1" and checkerboard data patterns are used to select all memory cell transistors, select rows,
Writing can be performed simultaneously by selecting all of the odd-numbered rows, all of the even-numbered rows, or a combination of these odd- and even-numbered rows. In addition to the above-described selection, in addition to the above-described selection, even in the case of "0" data, the word line unit Therefore, the entire test time including data writing and reading can be reduced.

[0072]

As described above, according to the present invention, at the time of the erase pulse applying operation, all the word lines are selected, a predetermined first voltage is supplied, and the erase pulse is applied to the source line to thereby apply the erase pulse to all the memory cell transistors. On the other hand, hot carriers due to avalanche breakdown between the substrate and the source at the ground potential are injected into the floating gate to erase all at once, and at the time of over-erasure determination operation, all word lines are selected and a predetermined second voltage is supplied. In addition, since all the digit lines are selected and all the currents of all the memory cell transistors are detected and determined by the sense amplifier, the threshold voltage of the memory cell transistors after the batch erasure can be converged to a constant value and the erase pulse The application operation and the over-erase discrimination operation can be performed only once, so that there is an effect that the time until the completion of erasure can be shortened.

A circuit for generating various voltages to be supplied to word lines and digit lines during various operations is provided between the high voltage power supply voltage supply terminal and the ground potential point in addition to the two output transistors. Since the transistors for reducing the power supply voltage supplied to these two transistors are provided, there is an effect that these transistors do not have to be of a high breakdown voltage type.

Further, the row decoder and the column decoder can select all word lines and all digit lines, and can select all odd-numbered word lines and all even-numbered word line digit lines.
Since an OR circuit and a pull-up circuit for detecting and determining the signal levels of all the digit lines, all of the odd-numbered digits, and all of the even-numbered digit lines are provided, all “0”, all “1”,
This has the effect of shortening the entire test time including writing and reading of a test pattern such as a checkered pattern.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a circuit for generating various voltages included in a word line voltage generation circuit and a write circuit of the embodiment shown in FIG.

FIG. 3 is a circuit diagram showing a second embodiment of the present invention.

FIG. 4 is a circuit diagram showing a third embodiment of the present invention.

FIG. 5 is a circuit diagram showing an example of a conventional nonvolatile semiconductor memory device.

6 is a circuit diagram showing an example of a circuit for generating various voltages included in a word line voltage generation circuit and a write circuit of the nonvolatile semiconductor memory device shown in FIG.

[Explanation of symbols]

1,1x memory cell array 2,2a, 2x row decoder 3,3x word line voltage generator 4,4a column decoder 5 column selection circuit 6 source potential supply circuit 7,7x writing circuit 8 sense amplifier 9,9a switching circuit 10 pull Up circuit 11, 11a OR circuit DL1 to DLn, DLe, DLo Digit line G11 OR gate G21 to G23, G23e, G23o, G23x, G4
1 to G43, G43e, G43o Logic gates IV21, IV41, IV42 Inverters MC11 to MCmn, MC11x to MCmnx, MCe
e, MCeo, MCoe, MCoo Memory cell transistors Q21, Q22, Q31-Q39, Q51-Q5n, Q
5e, Q5o Transistor R10, R11e, R11o, R31-R38 Resistance SL Source line WL1-WLm, WLe, WLo Word line

Claims (7)

(57) [Claims] 1. A plurality of memory cell transistors arranged in a matrix in a row direction and a column direction and capable of electrically erasing and writing data, and provided corresponding to each row of the plurality of memory cell transistors. A plurality of word lines connected to the control gates of the memory cell transistors in each row, and a plurality of word lines provided corresponding to each column of the plurality of memory cell transistors and connected to the drain of each memory cell transistor in the corresponding column. A digit line, a source line connected to a source of each of the plurality of memory cell transistors, and various kinds of operations corresponding to various operations including a first voltage during an erase pulse applying operation and a second voltage during an over-erased determining operation. A word line voltage generating circuit for generating a voltage, and at the time of the erase pulse applying operation and the over-erase determining operation. All of the plurality of word lines are selected and the first and second voltages are supplied from the word line voltage generation circuit to perform normal read and write operations. A row decoder for selecting a predetermined word line and supplying a corresponding voltage from the word line voltage generation circuit, and generating an erase pulse of a predetermined voltage during the erase pulse application operation to supply the generated erase pulse to the source line for erasing; A source potential supply circuit that sets the source line to the ground potential except during the pulse application operation; and a plurality of the digit lines during the erase pulse application operation, in which all of the plurality of digit lines are in a non-selected and floating state and the over-erase determination operation is performed. During normal read and write operations, all the lines are selected according to an external column address signal. A digit line selection circuit for selecting a digit line of the plurality of digit lines, a sense amplifier for determining a signal level of a digit line selected from the plurality of digit lines at the time of the over-erase determination operation and a normal read operation, and A non-volatile semiconductor memory device, comprising: a write circuit that supplies a predetermined voltage to a selected digit line among the plurality of digit lines during a write operation. 2. The semiconductor device according to claim 1, wherein each of the plurality of memory cell transistors is formed of an N-channel field-effect transistor having a floating gate and connects a substrate to a ground potential point. A positive first voltage is applied to the control gate and an erase pulse is applied to the source to inject hot carriers due to avalanche breakdown between the source and the substrate into the floating gate to collectively collect data of all of the plurality of memory cell transistors. At the time of over-erase determination operation after the batch erasure, positive second control signals are applied to the control gates of all of the plurality of memory cell transistors.
And all the plurality of digit lines are selected, the level of the total current flowing through the plurality of digit lines is determined by the sense amplifier, and whether or not there is a memory cell transistor in an overerased state is collectively determined. 2. The nonvolatile semiconductor memory device according to claim 1, wherein: 3. A power supply voltage to be supplied includes a normal power supply voltage and a power supply voltage for a high voltage higher than the normal power supply voltage, and generates various voltages in a word line voltage generation circuit and a write circuit. A circuit connects first and second resistors connected in series between the power supply voltage supply terminal for high voltage and a ground potential point, and connects a gate to a series connection point of the first and second resistors. An N-channel type first drain for connecting the drain to a high potential side of the high voltage power supply voltage and the ground potential point;
And an N-channel type second transistor having a drain connected to the source of the first transistor, a source connected to the output terminal of the various voltages, and a gate receiving a first reference voltage.
And a P-channel transistor having a drain connected to the power supply voltage supply terminal for high voltage and the low potential side of the ground potential point, a source connected to the output terminals for the various voltages, and a gate receiving a second reference voltage. 2. The nonvolatile semiconductor memory device according to claim 1, comprising a third transistor of a type. 4. A drain of the second transistor is directly connected to a high-potential side of a high-voltage power supply voltage supply terminal and a ground potential point, and a drain of the third transistor and the high-voltage power supply voltage are supplied. The first transistor is connected to the drain of the third transistor, and the drain is connected to the power supply voltage supply terminal for high voltage and the ground potential point. 2. The nonvolatile semiconductor memory device according to claim 1 , wherein said nonvolatile semiconductor memory device is of a P-channel type wherein said gate is connected to a low potential side and a gate is connected to a series connection point of said first and second resistors. 5. An OR circuit for performing an OR operation on all signals of each of a plurality of digit lines, and a pull-up resistor having a resistance value sufficiently larger than an on-resistance of the memory cell transistor. A pull-up circuit for supplying a normal power supply voltage, and after applying an erase pulse, selecting one word line to supply a third voltage and selecting all of the plurality of digit lines to perform the pull-up. The circuit is connected and the sense amplifier is disconnected from the plurality of digit lines. The erase state is determined by the output signal of the OR circuit whether the memory cell transistor connected to the one word line is in the erase state or not. 2. The nonvolatile semiconductor memory device according to claim 1, further comprising a determination unit. 6. The row decoder and the digit line selection circuit each include odd / even selection means for selecting all odd-numbered only and all even-numbered only ones of the plurality of word lines and the plurality of digit lines. And an OR circuit that performs an OR operation on all of the signals, and a pre-up circuit that has a pull-up resistor having a resistance value sufficiently larger than the ON resistance of the memory cell transistor and supplies a normal power supply voltage to the selected digit line through this resistor. And a plurality of memory cell transistors each having a checkerboard data pattern in an erase state and a write state so that adjacent ones are different from each other. During a read operation, all odd-numbered word lines are selected and these word lines are selected. And all the even-numbered word lines in the write state memory cell transistor connected to the The sense amplifier collectively detects and discriminates all the currents of the selected memory cell transistors in the written state connected to these word lines, selects the word lines one by one, and respectively selects the erased memory cell transistors connected to the word line. 2. The non-volatile semiconductor memory device according to claim 1, wherein the signal level of the digit line corresponding to the above is determined collectively by the OR circuit. 7. An OR circuit is connected between each of the plurality of digit lines and a ground potential point, and includes a plurality of pull-down resistors having a resistance value sufficiently larger than a pull-up resistor, and all of the plurality of digit lines. OR that performs signal OR operation
7. The nonvolatile semiconductor memory device according to claim 6, comprising a gate.