JP2771910B2 - Measurement circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a measuring circuit, and more particularly to a measuring circuit for displaying the frequency of an input signal on a display device.

[0002]

2. Description of the Related Art For example, a speedometer of an automobile, a tachometer of an engine, and the like are configured to convert the frequency of an input signal from a sensor into an analog or digital display value by a measurement circuit and display the converted value on a display device. .

A measuring circuit for supplying the frequency of an input signal to a display device has a function of counting the number of cycles within a predetermined time, and has a function of measuring the time of one cycle and converting it to a frequency. Object or frequency voltage (F /
V) Those using a converter are known.

[0004]

However, according to the above-described conventional measuring circuit, the characteristics of the individual display devices vary, and it is possible to correct the variations in the characteristics of the display devices and display an accurate display. It was extremely difficult.

The present invention has been made in view of the above problems, and has as its object to provide a measurement circuit capable of correcting variations in a display device with a simple circuit configuration.

[0006]

According to the first aspect of the present invention,
2 in the input signal measuring circuit for displaying on the measured display device by converting the amplitude of the signal corresponding to the frequency to the frequency of the (S ₁₎ (10), the input signal
Clock pulse generating means for generating a clock pulse (Cp) with a frequency higher than the frequency of the (S ₁₎ (24)
And the input signal (S ₁ ) and the clock pulse (C
edge detecting means for sampling at p) and outputting an edge detection signal synchronized with the clock pulse (Cp)
(23) , gate means (26) for outputting a first coefficient (Gx) when receiving an edge detection signal from the edge detection means (23), and sampling of the cycle of the clock pulse (Cp). Timing and the above input signal
A first digital filter (30) for outputting the amplitude of the signal (Fp) corresponding to the frequency of the (S _1), said gate hand
Addition of the output of the stage (26) and the second coefficient (Px)
Computing means (29), the first digital filter
The output of the adding means (29) is inputted to the data (30) .

According to a second aspect of the present invention, there is provided a waveform shaping means for shaping the waveform of the input signal into a substantially rectangular wave.
The edge detecting means detects an edge of the input signal shaped into a substantially rectangular wave by the waveform shaping means, samples the clock signal with the clock pulse, and outputs an edge detection signal synchronized with the clock pulse. The digital filter includes delay means for holding the input at the time of the previous sampling, first multiplication means for multiplying the input at the time of the previous sampling held by the delay means by a positive value smaller than 1, and the first filter. An adder for adding the output of the multiplying means to the input at the time of the current sampling and inputting the result to the delaying means; and a second multiplying means for multiplying the output of the delaying means by a third coefficient and outputting the result. An output of the second multiplying means, a second digital filter for filtering an output of the first digital filter, and a second digital filter;
And a driving means for receiving the output of the digital filter and converting the output of the second digital filter into a signal for driving the display device.

[0008]

Further, the invention according to claim 3 is provided with correction means for outputting a second coefficient changed according to the output of the first digital filter, and the adding means includes an output of the gate means and an output of the gate means. And the second output from the correction means.
Adding the second coefficient, the first digital filter, wherein an output of said adder means is input.

The invention according to claim 4 further comprises a correction means for outputting a second coefficient changed according to the output of the second digital filter, and the addition means includes an output of the gate means and an output of the gate means. And the second output from the correction means.
Adding the second coefficient, the first digital filter, wherein an output of said adder means is input.

[0011]

According to the first aspect of the present invention, the output of the gate means for outputting the first coefficient when receiving the edge detection signal is input to the first digital filter. Is a value obtained by multiplying the amplitude value according to the frequency of the input signal by the first coefficient. Further, the output of the gate means and the second coefficient are added.
Edge detection can be achieved by providing the addition means.
The first coefficient is replaced by the first coefficient when the output from the means is received.
Is added, otherwise the second coefficient is the first
Of the first digital filter.
The output of the filter changes to an amplitude value corresponding to the frequency of the input signal.
Multiplied by a coefficient of 1 and a value obtained by adding a second coefficient.
You.

According to the second aspect of the present invention, the input signal is shaped into a substantially rectangular wave by the waveform shaping means, so that the edge of the input signal is detected by the edge detecting means, whereby the input signal is formed. Sampled.
Further, the output of the first digital filter is filtered by the second digital filter, so that the output is filtered. Further, by providing the driving means, the display device can be directly driven.

[0013]

According to the third or fourth aspect of the present invention, a correction means for outputting a second coefficient changed according to the output of the first digital filter or the second digital filter is further provided. by the value of the first coefficient is added to the second coefficient when subjected to output from the edge detecting means, the second coefficient is input to the first digital filter in other cases , a second output of the first digital filter is changed in accordance with the output of the further first digital filter or the second digital filter first coefficient is multiplied to the amplitude value corresponding to the frequency of the input signal The value is the sum of the coefficients.

[0015]

2 and 3 show block diagrams including a measuring circuit according to a first embodiment and a second embodiment of the present invention.

The measuring circuit 10 in the block diagrams of FIGS.
Is an oscillation circuit 2 corresponding to the clock pulse generating means.
5, a clock generating circuit 24, a waveform shaping circuit 22 corresponding to the waveform shaping means, an edge detecting circuit 23 corresponding to the edge detecting means, a gate circuit 26 corresponding to the gate means, and a correcting circuit 27 corresponding to the correcting means. , 37
An addition circuit 29 corresponding to the addition means, an integration filter circuit 30 corresponding to the first digital filter, an integration filter circuit 40 corresponding to the second digital filter, and a drive circuit 21 corresponding to the drive means. Is done.

In the figure, the end of the line shown on the right side
Lead to the end of the indicated line on the left side of FIG. The only difference between the first embodiment and the second embodiment lies in the configuration of the correction circuit. The measurement circuit 10 of the first embodiment includes a correction circuit 27, and the measurement circuit 10 of the second embodiment includes a correction circuit. The configuration includes a circuit 37.

The numeral 1 on the right side of FIG. 3 shows a display device. In this embodiment, a cross-coil type display device is applied.

FIG. 4 is a perspective view of the display device.

The display device 1 shown in FIG. 4 is of a cross coil type, in which a pair of coils, a sine coil 2, a cos coil 3, and a coil 2 arranged so that the mechanical cross angle is 90 °. A movable magnet 4 disposed in the internal space of 3,
It comprises a pointer shaft 5 extending upward from the center of the movable magnet 4 and a pointer 6 fixed to the upper end of the pointer shaft 5.

In the display device 1 having the above-described structure, the sin coil 2 and the cos coil 3 correspond to the electric angles A of the sine wave 11 and the cosine wave 12 having the electric angles shown in FIG. The operation is performed when a level signal is supplied.

Here, in the case of the present embodiment, the input signal S ₁ having a frequency corresponding to the engine speed is output from the measuring circuit 10.
The signal is converted into an output signal Ax having an amplitude corresponding to the frequency of the input signal S ₁ by the measurement circuit 10, and the output signal Ax is further advanced by the drive circuit 21 in accordance with the increase or decrease of the output signal Ax. And is supplied to the display device 1. The phase angle of this signal corresponds to the electrical angle A of the display device 1.

[0023] Figure 2, in the block diagram of FIG. 3, for example, after the input signals S ₁ AC having a frequency f from linked tachometer is shaped into the input substantially square wave waveform shaping circuit 22 to the engine shaft , Are input to the edge detection circuit 23. In this embodiment, the frequency f of the input signals S ₁ is set to 1Hz with respect to the rotational speed 30rpm of the engine.

The clock generation circuit 24 generates a clock pulse Cp having a higher frequency than the input signal S ₁ based on the signal oscillated by the oscillation circuit 25, and this clock pulse Cp is input to the edge detection circuit 23. Is done.
In the case of the present embodiment, the frequency of the clock pulse Cp is 819
2 Hz, and the value of the output signal Ax of the measurement circuit 10 is 102
4, the electrical angle A of the display device 1 is set to be 90 °, and the value of Ax is 3072 with respect to the rotation speed of 9000 rpm (300 Hz).
Are set so that the electrical angle A of the becomes a ratio of 270 °.

In the edge detection circuit 23, the input signal S ₁ is generated by the clock pulse C generated by the clock generation circuit 24.
An edge detection signal sampled by p and synchronized with the clock pulse Cp is output.

FIG. 6 shows the input signal S ₁ input to the edge detection circuit 23, the clock pulse Cp and the edge detection circuit 2
3 shows a time chart with the output signal of FIG. As shown in FIG. 6, the output signal at the rising edge of the clock pulses Cp immediately substantially square wave input signals S ₁ becomes rising to a high level (hereinafter simply referred to as "H".) Is an H, the next clock pulse At the rise of Cp, the output signal is set to a low level (hereinafter simply referred to as “L”). Thus among the clock pulses Cp clock pulse by the edge detection circuit 23, an output signal as an edge detection signal during one cycle immediately after the rising edge of the input signals S ₁ are the H.

The gate circuit 26 is composed of, for example, an AND logic circuit, and has a function of outputting the sensitivity set value Gx corresponding to the first coefficient only when there is an output from the edge detection circuit 23. The sensitivity setting value Gx is a factor for determining the amplitude of the pointer 6 of the display device 1 with respect to the range of the input signal S _1.

FIG. 7 shows a configuration example of a logic circuit including the edge detection circuit 23 and the gate circuit 26. 7, 71, 7
2 is a D-type flip-flop, 73-82 are AND
It is a logic circuit. The D-type flip-flop has a configuration in which the value of the D input at the time of rising of the CK input is held at the Q output. The QB output has a value obtained by inverting the Q output.

The input signal S ₁ , the clock pulse Cp, and the sensitivity setting value Gx are input to the terminals 83 to 85 to the edge detection circuit 23 and the gate circuit 26 having the above-described configurations, respectively. Sometimes, the sensitivity setting value Gx is output.

Next, the operation of the edge detection circuit 23 and the gate circuit 26 having the above configuration will be described. First, while the input signal S ₁ inputted to the terminal 83 is L, the Q of the flip-flop 71
The output becomes L, the Q output of the flip-flop 72 becomes H, and the QB output becomes L. Therefore, the input of the AND logic circuit 73 becomes L and H, and the output thereof becomes L, and the outputs of the AND logic circuits 75 to 82 all become L.

Next, the input signal S ₁ rises to H,
At the next rising of the clock pulse Cp, the Q output of the flip-flop 71 becomes H. On the other hand, since the D input of the flip-flop 72 is still at L at the moment when the clock pulse Cp rises, the Q output remains at L and the QB output remains at H. Therefore, both inputs of the AND logic circuit 73 become H, and the output thereof becomes H. Therefore, the AND logic circuits 75 to 82 output the sensitivity setting value Gx input to the terminal 85 to the terminal 86.

At the next rising edge of the clock pulse Cp, the input signal S ₁ remains at H and the Q output of the flip-flop 71 is maintained at H, so that the Q output of the flip-flop 72 becomes H and the QB output becomes L. Therefore, the inputs of the AND logic circuit 73 are H and L, the output is L, and the outputs of the AND logic circuits 75 to 82 are all L.

Thereafter, when the input signal S ₁ is at the H level, the states of the flip-flops 71 and 72 do not change.
The states of the ND logic circuits 73 and 75 to 82 do not change. Further, when the input signal S ₁ becomes L, the flip-flop 7
1 becomes L, and the input of the AND logic circuit 73 becomes L
Is maintained. This state is maintained until the input signal S ₁ rises to H. Thereafter, the above operation is repeated. That is, the operation is as shown in the time chart of FIG. 6, and a substantially rectangular wave is output as the edge detection signal.

In the present embodiment, the rising edge of the input signal S ₁ is detected and the period of the clock pulse Cp corresponds. However, the period of the clock pulse Cp is changed by detecting the falling edge of the input signal S _1. The configuration may be compatible.

Since the clock pulse Cp generated by the clock generation circuit 24 has a higher frequency than the frequency of the input signal S ₁ as described above, the clock pulses Cp always have different periods from each other. It will be associated to each cycle of S _1.

Further, the edge detection circuit 23 outputs the substantially rectangular wave as an edge detection signal obtained by the above operation after dividing or multiplying the signal as necessary, and outputs the signal at the display stage. A configuration may be adopted in which an appropriate display magnification is set.

The correction circuits 27 and 37 change the offset set value Qx according to the value of the output Ax of the integration filter circuit 40, and output it as an offset value Px corresponding to the second coefficient. The offset value Px is used to correct a display error due to a variation in characteristics of the display device 1.
In the case of this embodiment, the offset set value Qx is equivalent to approximately 6 degrees of the electrical angle A, that is, Qx = 68.

That is, it is configured such that Px is defined as a function of Ax. If there is no need to perform correction by changing the offset set value Qx, Qx
May be output as Px. Further, by rotating the pointer 6 of the display device 1 with respect to the pointer shaft 5, the display device 1 is rotated.
When the offset adjustment (zero point adjustment) is possible, the offset set value Qx is unnecessary.

The adder circuit 29 is configured to add the outputs of the gate circuit 26 and the correction circuits 27 and 37 and output the result.

FIG. 8 is a block diagram of the integration filter circuit 30.

The integrating filter circuit 30 of FIG. 8 includes an adder 31 corresponding to the adding means, multipliers 32 and 33 corresponding to the first and second multiplying means, and a delay corresponding to the delay means. And a digital filter that uses the cycle of the clock pulse Cp generated from the clock generation circuit 24 as a sampling timing.

In the integrating filter circuit 30 having the above configuration, the value at the previous sampling is held by the delay unit 34 and the multiplier 3
The value is multiplied by 2 with a positive numerical value smaller than 1, added to the input at the time of the current sampling by the adder 31, and input to the delay unit.

For the number n updated as the sampling progresses, the input to the adder 31 is x (n), the input to the delay unit 34 is y (n), and the multiplication coefficient of the multiplier 32 is a1.
Then, the output of the delay unit 34 becomes y (n-1), and y
(N) is represented by y (n) = x (n) + a1 · y (n−1) (1). In the case of the present embodiment, a1 = 1023/1024.

The integrating filter circuit 30 includes a multiplier 32
By setting the multiplication coefficient a1 to 1>a1> 0 (2), the multiplication coefficient a1 functions as an integrator and forms an integration filter circuit.

That is, from the state of y (n-1) = 0, the signal P
When y is input, x (n) becomes a signal Py, and y (n) becomes a signal Py. After that, the signal Py is again
Is input until x is input, and n is updated one by one at each cycle of the clock pulse Cp.
(N) is multiplied by the coefficient a1, and y (n) is gradually reduced.

Here, when the input signal Py is input again, x
(N) becomes Px, and the signal Py is added as x (n) to y (n) reduced in the above process, and thereafter y (n) is reduced in the same manner as described above until the signal Py is input. .

The signal in which y (n) is increased or decreased so as to undulate as described above is output from the integration filter circuit 30. Note that the value of a1 determines the response characteristic of the measurement circuit 10, and can be set within the range of the above equation (2) as necessary. The multiplication coefficient a2 of the multiplier 33 corresponding to the third coefficient can be arbitrarily set, and is set to an appropriate value to be input to the integration filter circuit 40 in the next stage. In the case of the present embodiment, a2 = 1/1024.

The clock pulse Cp supplied to the integration filter circuit 30 is the same signal as the clock pulse Cp supplied to the edge detection circuit 23. Here, the frequency of the clock pulses Cp as described above are those higher than the frequency of the input signal S _1. Therefore, of the cycle of the clock pulse Cp, the edge detection circuit 23 detects the rising edge of the input signal S ₁ and outputs only the cycle corresponding to the cycle corresponding to the rising edge as the edge detection signal from the edge detection circuit 23. .

On the other hand, the input signal S
_If the rising edge of ₁ is not detected and therefore no edge detection signal is issued, no signal is input from the gate circuit 26 to the addition circuit 29, and the correction circuit 2
7 and 37, only the offset value Px is input.

The input signal S _{1 is} supplied to the edge detection circuit 23.
When the rising edge of the gate circuit 2 is detected, the gate circuit 2
6, the sensitivity setting value Gx is input to the addition circuit 29, added to the offset value Px from the correction circuit 29, and input to the integration filter circuit 30.

In the case of this embodiment, the frequency of the clock pulse Cp is 8192 Hz. Here, the frequency f of the input signal S ₁ is equal to the frequency of the clock pulse Cp 819.
Assuming a case of 2 Hz, the edge detection circuit 23
In this case, the edge detection signal is output for all periods of the clock pulse Cp.
x will be output. Gx is determined based on the above assumed conditions.

That is, as described above, the input signal S ₁ is 300H
Since the value of Ax is 3072 with respect to z, Gx = 83886 is set from the proportional expression of 300/8192 = 3072 / Gx.

Therefore, when the rising edge of the input signal S ₁ is detected, the output signal Fp of the integration filter circuit 30 has the sensitivity set value Gx above the offset value Px constantly output from the correction circuits 27 and 37. It is added, then the rising edge of the input signal S ₁ is a signal that is reduced in accordance with the multiplication coefficients a1 to be detected.

The output signal Fp of the integration filter circuit 30
Since the period is shortened the higher the frequency of the input signals S _1, the time from the detection of the rising edge of the input signal S ₁ is the next rising edge is detected becomes shorter. Accordingly, the number of times y (n) is reduced by multiplication by the multiplication coefficient a1 during the period of the clock pulse Cp during that period is reduced, and the level of the output signal Fp of the integration filter circuit 30 is increased on average.

Conversely, if the frequency of the input signal S ₁ becomes lower, the period becomes longer, the number of times y (n) is reduced by the multiplication coefficient a 1 increases, and the level of the output signal Fp of the integration filter circuit 30 becomes higher. Averagely lower.

As described above, the average level of the output signal Fp of the integration filter circuit 30 is continuously changed to a value obtained by integrating the intermittent input of the sensitivity set value Gx to have an amplitude proportional to the input signal S _1. The offset value Px is a value added.

[0057] Then the integrating filter circuit 40 in the case of this embodiment, has the same structure as the integral filter 3 0. The integrating filter circuit 40, particularly the output signal Fp of the input signal integrating filter circuit 30 when the low frequency S ₁ is greater vertical movement of the level, the display device 1 which is a ripple
In order to prevent the pointer 6 from vibrating, it is added to perform a filtering process for removing the ripple.

The output signal Ax of the integration filter circuit 40 is
The correction circuits 27 and 37 are input to the driving circuit 21 for driving the display device 1 and fed back as described above.
Has been entered.

[0059] Figure 9 shows a graph of the rising characteristics of the output signal Ax of the configuration of the integrating filter circuit 40 with respect to the frequency f of the input signal S _1.

In FIG. 9, the horizontal axis represents time (seconds), and the vertical axis represents engine speed (rpm). Curves 91 and 92 show f and Ax, respectively, which are converted into the number of revolutions.

FIG. 10 is a graph showing the rise characteristics of the output signal Ax with respect to the frequency f of the input signal when the input signal S ₁ has a very low frequency.

In FIG. 10, the horizontal axis represents time (seconds), and the vertical axis represents the value of Ax. Curves 93 and 94 are A
It shows f and Ax converted to x. The ripples in the curve 94 of Ax are the ripples described above.

Next, the configuration of the correction circuits 27 and 37 will be described.

FIG. 11 shows a measuring circuit 1 according to the first embodiment of the present invention.
FIG. 2 shows a block diagram of a correction circuit provided for the zero.

The correction circuit 27 in FIG. 11 is for changing the measurement characteristic Mp as shown in FIG.

In general, an analog display device often does not display a zero point even when a zero-point signal is supplied from a measurement circuit due to an influence of a display device error and a hysteresis characteristic of the display device. Therefore, as shown in FIG. 12, when the frequency f of the input signal S ₁ becomes fm near zero, the slope of the measurement characteristic Mp becomes steep, and when the frequency f of the input signal S ₁ becomes 0, the display device 1 The supplied signal is set to a value less than Am corresponding to the zero point, and the display device 1
Pointer 6 displays a zero point.

Here, by providing a mechanical stopper on the display device 1 so that the pointer 6 does not indicate a point below the zero point, the pointer 6 can reliably indicate the zero point.

In FIG. 12, the output to the drive circuit 21 is Ax, the frequency of the input signal S ₁ is f, the sensitivity of the normal measurement circuit 10 is K1, and the offset (the output signal when the frequency f of the input signal S ₁ is zero) Am the level Ax)
A coefficient for steepening the measurement characteristic Mp is K2, a characteristic Mp on the right side of the frequency fm at which the inclination of the measurement characteristic Mp is changed is Ax = K1 · f + Am (3), and the left side is Ax = K1 · f + K2 · Ax (4) As a result, from equation (4), the output signal Ax converges to Ax = K1 · f / (1−K2) (5), and 1>K2> 0 (6) ), The slope of the characteristic Mp on the left side from fm can be made steep.

In the case of this embodiment, the value of Am corresponds to the above-mentioned Qx, and is 68. Also, if the input signal f is 300
Ax value at Hz, 3068 offset A
Ax = 3072 + 68 = 3140 by adding m and 68. Therefore, from the above equation (3), K1 = 10.24 from 3140 = K1 · 300 + 68.

The frequency f at which the slope of the characteristic Mp changes
When m is set to 20 Hz, the value of fm is set to f, and the values of Am and K1 are substituted into the above equations (3) and (5) to solve, Ax = 272.8 K2 = 1/4 .

In the block diagram of FIG. 11, the Am determination circuit 41 determines that the level of the output signal Ax fed back from the integration filter circuit 40 corresponds to the frequency fm of the input signal S ₁ at the boundary that changes the slope of the measurement characteristic Mp. This is to determine whether the level is higher or lower. The result of the determination is output to the selection circuit 42. Further, the multiplication circuit 43 is configured to multiply the signal Ax by the coefficient K2 and output the result to the selection circuit 42.

[0072] The selection circuit 42, the input signals S ₁ of frequency f output from the Am decision circuit 41 the level of the signal Ax corresponding is set in advance Am to the selection circuit 42, if a determination that more than fm In this case, an instruction is given to select the set offset value Qx, and if the value is less than fm, an instruction is given to select the output from the multiplication circuit 43.

Accordingly, when the signal Ax is higher than the level corresponding to the frequency fm, the correction circuit 27 having the above-described configuration sets the offset set value Qx, that is, A, as the offset value Px.
m, and outputs an offset value Px obtained by multiplying the signal Ax by a coefficient K2 when the signal Ax is low. Further, the output signal Ax of the integration filter circuit 40 converges to a value to which the offset value Px is added. Therefore, the characteristic Mp of the measurement circuit 10
The frequency of the input signal S ₁ is a characteristic that matches the above equation (4) is less than fm in the above equation (3) in the above fm.

The measurement characteristics Mp can be changed by variously modifying the above equation, without being limited to the above configuration. That is, for example, B1 is a first offset value, B2 is a second offset value, a frequency fm at which the slope of the measurement characteristic Mp changes is a boundary, Ax = K1 · f + B1 + B2... value if (input signals S ₁ of frequency f the value of the output signal Ax when zero) as a function of the output signals Ax and, Ax = K1 · f + K2 · (Ax-B2) + B2 ... and (8) equation (7) , (8), Ax = K1 · f / (1-K2) + B2 (9). As described above, the configuration may be such that the second offset value B2 is always added.

FIG. 13 is a block diagram of a correction circuit provided in the measuring circuit 10 according to the second embodiment of the present invention.

The correction circuit 37 shown in FIG.
And an adder circuit 52.

Generally, it is difficult to increase the accuracy of an analog display device because of its nonlinearity. This embodiment is for use in correcting a display error due to non-linearity of the analog display device.

The memory circuit 51 shown in FIG. 13 receives the output signal Ax of the integration filter circuit 40 and outputs a correction value Bx stored in advance in accordance with the input value Ax.
Further, the correction value Bx is added to the offset set value Qx by the adding circuit 52, and is output as the offset value Px.

The memory circuit 51 can be constituted by a general memory element. Further, it may be programmable as necessary, or may be configured with a simpler logic circuit.

FIG. 14 is a graph showing an example of an error characteristic of the display device with respect to the output signal Ax of the integrating filter circuit 40 and a correction characteristic by the correction circuit 37 for correcting the error characteristic.

In FIG. 14, the error of the display device can be corrected very easily by setting the correction characteristic 62 which is inverted with respect to zero so as to have the characteristic which cancels the error characteristic 61 of the display device. Can be.

Here, actually, Ax is the correction circuit 37.
, And is recursively calculated and converged, a correction value Bx corresponding to the added output signal Ax is further superimposed and added to the output signal Ax to which the correction value Bx is added. Therefore, if the correction characteristic is obtained by inverting the error characteristic of the display device as shown in FIG. 14, an error occurs due to the superposition of the correction values. Therefore, in order to further improve the accuracy, it is only necessary to set a correction characteristic in the memory circuit 51 in which an error due to the superposition of the correction values is considered in advance.

By setting a value to which the offset set value Qx is added in advance as the correction value Bx in the memory circuit 51, the addition circuit 52 can be omitted.

Further, since an arbitrary correction characteristic can be obtained by the correction circuit 37, a special measurement characteristic or a highly accurate measurement characteristic can be easily realized.

In the above embodiment, the measuring circuit 10 is mainly constituted by a logic circuit. However, the present invention is not limited to this configuration.
A configuration using a logic circuit different from that described above may be used, or each of the circuits shown in the block diagrams related to the measurement circuit 10 and FIGS. 2, 3, 8, 11, and 13 may be configured using a microcomputer or the like. You may.

[0086]

As described above, according to the first aspect of the present invention, the output of the first digital filter is obtained by multiplying the amplitude value corresponding to the frequency of the input signal by the first coefficient. Thus, the sensitivity of the measurement circuit can be easily adjusted with a simple configuration by adjusting the first coefficient. Change
When the output from the edge detecting means is received,
The value obtained by adding the second coefficient to the number,
2 is input to the first digital filter.
By adjusting the second coefficient, a simple configuration can be achieved.
Can easily adjust the offset of the measuring circuit.
You.

According to the second aspect of the present invention, since the sampling is performed by detecting the edge by the edge detecting means, the cycle of the input signal can be easily detected. Further, since the output is filtered and the display device is directly driven, it is not necessary to prepare another driving means.

[0088]

According to the third or fourth aspect of the present invention, the second coefficient changed according to the output of the first digital filter or the second digital filter is
When the edge detection signal is received, the value added to the first coefficient is input to the first digital filter otherwise, and the second coefficient is input to the first digital filter. , The offset value can be changed in accordance with the output of the digital filter, and the error characteristics of the display device can be corrected. Therefore, the error characteristics of the display device can be easily corrected with a simple configuration, and any correction characteristics can be obtained by the correction means, so that special measurement characteristics and high-precision measurement characteristics can be easily realized. Can be.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of the present invention.

FIG. 2 is a block diagram (part 1) including a measurement circuit according to the first embodiment and the second embodiment of the present invention.

FIG. 3 is a block diagram (part 2) including a measurement circuit according to the first embodiment and the second embodiment of the present invention.

FIG. 4 is a perspective view of a display device.

FIG. 5 is a diagram illustrating a graph of a signal supplied to the display device of FIG. 3;

FIG. 6 is a diagram showing a time chart of a function of an edge detection circuit as a main part of the present invention.

FIG. 7 is a configuration diagram of an edge detection circuit and a gate circuit as main parts of the present invention.

FIG. 8 is a block diagram of the integration filter circuit of FIG. 3;

FIG. 9 is a graph showing a rising characteristic of an output of an integral filter circuit of a main part of the present invention.

10 is a diagram showing a graph when the frequency of the input signal in FIG. 9 is low.

FIG. 11 is a block diagram of a correction circuit of a main part of the first embodiment of the present invention.

12 is a diagram illustrating a graph of measurement characteristics of a measurement circuit to which the correction circuit in FIG. 11 is applied.

FIG. 13 is a block diagram of a main part of a correction circuit according to a second embodiment of the present invention.

FIG. 14 is a graph showing a correction characteristic graph of a measurement circuit to which the correction circuit of FIG. 13 is applied.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Display apparatus 10 Measurement circuit 21 Drive circuit 23 Edge detection circuit (edge detection means) 24 Clock generation circuit (clock pulse generation means) 25 Oscillation circuit (clock pulse generation means) 26 Gate circuit (gate means) 27, 37 Correction circuit ( Correction means 30 integration filter circuit (first digital filter) 31 adder (addition means) 32, 33 multiplier (first multiplication means, second multiplication means) 34 delay unit (delay means) 40 integration filter circuit (second digital filter) 100 measurement circuit 101, S ₁ input signal 102, Cp clock pulse 103 a clock pulse generating means 104 edge detection signal 105 edge detection means 106, Gx sensitivity setting value (first coefficient) 107 gate means 109 First digital filter Px offset value (third filter Number) a2 second coefficient

Claims (4)

(57) [Claims] 1. A measuring circuit for converting a frequency of an input signal into a signal having an amplitude corresponding to the frequency and measuring and displaying the signal on a display device, comprising: a clock generating a clock pulse having a frequency higher than the frequency of the input signal. A pulse generation unit, an edge detection unit that samples the input signal with the clock pulse and outputs an edge detection signal synchronized with the clock pulse, and receives a first edge detection signal from the edge detection unit. a gate means for outputting the coefficient, the period of the clock pulse signal and the timing of sampling a first digital filter for outputting the amplitude of the signal corresponding to the frequency of the input signal, output a second of said gate means Adder that adds the coefficient of
And the first digital filter receives the output of the adding means.
A measuring circuit characterized by being applied. 2. A waveform shaping means for shaping a waveform of the input signal into a substantially rectangular wave, wherein the edge detecting means detects an edge of the input signal shaped into a substantially rectangular wave by the waveform shaping means, and Sampling with a clock pulse to output an edge detection signal synchronized with the clock pulse; the first digital filter includes a delay unit that holds an input at the time of the previous sampling; First multiplying means for multiplying the input at the time of sampling by a positive numerical value smaller than 1, adding means for adding the output of the first multiplying means to the input at the time of the current sampling and inputting the result to the delay means; Second multiplication means for multiplying the output of the delay means by a third coefficient and outputting the result. The output of the second multiplication means is input, and the output of the first digital filter is filtered. A second digital filter to be processed, and an output of the second digital filter,
2. A measuring circuit according to claim 1, further comprising driving means for converting an output of said digital filter into a signal for driving said display device. 3. A correction means for outputting a second coefficient changed according to an output of the first digital filter, wherein the addition means outputs an output of the gate means and an output of the correction means. 2. The measuring circuit according to claim 1, wherein the first digital filter is added with the second coefficient, and the output of the adding means is input to the first digital filter. 4. A correction means for outputting a second coefficient changed according to an output of the second digital filter, wherein the addition means outputs the output of the gate means and the output of the correction means. 3. The measurement circuit according to claim 2, wherein the first coefficient is added to the second coefficient, and the output of the adding means is input to the first digital filter.