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JP2763446B2 - Package for storing semiconductor elements - Google Patents

Package for storing semiconductor elements

Info

Publication number
JP2763446B2
JP2763446B2 JP4134711A JP13471192A JP2763446B2 JP 2763446 B2 JP2763446 B2 JP 2763446B2 JP 4134711 A JP4134711 A JP 4134711A JP 13471192 A JP13471192 A JP 13471192A JP 2763446 B2 JP2763446 B2 JP 2763446B2
Authority
JP
Japan
Prior art keywords
semiconductor element
metal frame
frame
metal
package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP4134711A
Other languages
Japanese (ja)
Other versions
JPH05335433A (en
Inventor
義明 植田
泰 谷口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP4134711A priority Critical patent/JP2763446B2/en
Publication of JPH05335433A publication Critical patent/JPH05335433A/en
Application granted granted Critical
Publication of JP2763446B2 publication Critical patent/JP2763446B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/1615Shape
    • H01L2924/16195Flat cap [not enclosing an internal cavity]

Landscapes

  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は半導体素子を収容するた
めの半導体素子収納用パッケージの改良に関するもので
ある。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement in a semiconductor device housing package for housing a semiconductor device.

【0002】[0002]

【従来の技術】従来、半導体素子を収容するための半導
体素子収納用パッケージは図3に示すようにアルミナセ
ラミックス等の電気絶縁材料から成り、上面中央部に半
導体素子が搭載される搭載部11a 及び該搭載部11a 周辺
から底面にかけて導出するタングステン、モリブデン、
マンガン等の高融点金属粉末から成るメタライズ配線層
12を有する絶縁基体11と、前記絶縁基体11の半導体素子
が搭載される搭載部11aを囲繞するようにして銀ロウ等
のロウ材を介して接合された金属枠体13と、該金属枠体
13の上面に接合される金属製の蓋体14とから構成されて
おり、絶縁基体11の半導体素子搭載部11a に半導体素子
15をロウ材、ガラス、樹脂等の接着剤を介して搭載固定
した後、該半導体素子15の各電極をメタライズ配線層12
にボンディングワイヤ16を介して電気的に接続させ、し
かる後、前記金属枠体13の上面に蓋体14をシームウエル
ド法等の溶接法を採用することによって接合させ、絶縁
基体11と金属枠体13及び蓋体14とから成る容器内部に半
導体素子15を気密に収容することによって最終製品とし
ての半導体装置となる。
2. Description of the Related Art Conventionally, a semiconductor device housing package for housing a semiconductor device is made of an electrically insulating material such as alumina ceramic as shown in FIG. Tungsten, molybdenum derived from around the mounting portion 11a to the bottom surface,
Metallized wiring layer made of high melting point metal powder such as manganese
An insulating substrate 11 having a metal frame 13 joined via a brazing material such as silver brazing so as to surround a mounting portion 11a on which the semiconductor element of the insulating substrate 11 is mounted;
13 and a metal lid 14 bonded to the upper surface of the semiconductor substrate 13.
15 is mounted and fixed via an adhesive such as brazing material, glass, resin, etc., and then the respective electrodes of the semiconductor element 15 are connected to the metallized wiring layer 12.
Then, a lid 14 is joined to the upper surface of the metal frame 13 by employing a welding method such as a seam welding method, and then the insulating base 11 and the metal frame are connected. A semiconductor device as a final product is obtained by hermetically housing the semiconductor element 15 in a container including the lid 13 and the lid 14.

【0003】尚、前記金属枠体13は通常、コバール金属
や42アロイ等の金属から成り、コバール金属等のイン
ゴット(塊)を圧延加工法により所定厚みの板状に成形
するとともこれを打ち抜きプレス法により枠状に打ち抜
くことによって形成されている。
The metal frame 13 is usually made of a metal such as Kovar metal or 42 alloy, and is formed by rolling an ingot (lumps) of Kovar metal or the like into a plate having a predetermined thickness by a rolling process and punching out the same. It is formed by punching into a frame shape by a method.

【0004】[0004]

【発明が解決しようとする課題】しかしながら、この従
来の半導体素子収納用パッケージにおいては、金属枠体
13がコバール金属等から成る板を打ち抜きプレス法によ
り所定の枠状に打ち抜くことによって形成されており、
打ち抜きプレス法によって金属枠体13を形成する場合、
その打ち抜きの加工性の点から幅Wの広さを厚みtの厚
さよりも大きな値としなければならない。そのため、絶
縁基体11の上面に厚みtが厚い金属枠体13を接合させた
い際には金属枠体13の幅が必然的に広くなり、その結
果、半導体素子収納用パッケージの全体形状が大型化し
て、近時の小型化が進む通信機器等にはその実装が困難
となる欠点を有していた。
However, in this conventional package for housing a semiconductor element, a metal frame is required.
13 is formed by punching a plate made of Kovar metal or the like into a predetermined frame shape by a punching press method,
When forming the metal frame 13 by a punching press method,
In view of the workability of the punching, the width W must be larger than the thickness t. Therefore, when it is desired to join the metal frame 13 having a large thickness t to the upper surface of the insulating base 11, the width of the metal frame 13 is inevitably increased, and as a result, the overall shape of the semiconductor element storage package becomes large. Thus, there has been a drawback that the mounting of such devices on communication devices and the like, which are becoming smaller in recent years, becomes difficult.

【0005】そこで上記欠点を解消するために金属枠体
13を打ち抜きプレス法で形成するのに代えて幅Wの広さ
を厚みtの厚さより小さい値として加工することができ
るしぼりプレス加工法を採用することによって形成する
ことが考えられる。しかしながら、金属枠体13をしぼり
プレス加工法を採用することによって形成した場合、金
属枠体13の上部内表面が曲面となり、金属枠体13の上面
に蓋体14を載置させ、両者をシームウエルド法等の溶接
によって接合させる際、蓋体14が金属枠体13上を滑って
両者を確実に接合させることができず、その結果、絶縁
基体11と金属枠体13及び蓋体14とから成る容器の気密封
止が不完全となり、内部に収容する半導体素子15を長期
間にわたり正常、且つ安定に作動させることができない
という欠点を誘発した。
[0005] In order to solve the above-mentioned drawbacks, a metal frame
It is conceivable to use a squeeze press working method which can work with the width W smaller than the thickness t instead of forming the 13 by the punch press method. However, when the metal frame 13 is formed by squeezing and pressing, the upper inner surface of the metal frame 13 becomes a curved surface, and the lid 14 is placed on the upper surface of the metal frame 13, and both are seamed. When joining by welding such as a welding method, the lid 14 slides on the metal frame 13 and cannot join them securely. As a result, the insulating base 11 and the metal frame 13 and the lid 14 The hermetic sealing of the container thus formed is incomplete, causing a disadvantage that the semiconductor element 15 housed therein cannot be operated normally and stably for a long period of time.

【0006】[0006]

【発明の目的】本発明は上記諸欠点に鑑み案出されたも
ので、その目的は小型で、且つ内部に収容する半導体素
子を長期間にわたり正常、且つ安定に作動させることが
できる半導体素子収納用パッケージを提供することにあ
る。
SUMMARY OF THE INVENTION The present invention has been devised in view of the above-mentioned drawbacks, and has as its object to reduce the size of a semiconductor device and to allow the semiconductor device contained therein to operate normally and stably for a long period of time. To provide packages for

【0007】[0007]

【課題を解決するための手段】本発明は半導体素子が搭
載される搭載部を有する絶縁基体と、該搭載部を囲繞す
るようにして前記絶縁基体に接合された金属枠体と、前
記金属枠体の上面に接合される蓋体とから成る半導体素
子収納用パッケージであって、前記金属枠体は打ち抜き
プレス法により成形された枠部材を複数積層、あるいは
しぼりプレス加工法により成形された第1の枠部材の上
面に打ち抜きプレス法により成形された第2の枠部材を
積層して形成されていることを特徴とするものである。
SUMMARY OF THE INVENTION The present invention provides an insulating base having a mounting portion on which a semiconductor element is mounted, a metal frame joined to the insulating base so as to surround the mounting portion, and the metal frame. A package for storing semiconductor elements, comprising a lid joined to an upper surface of a body, wherein the metal frame is formed by laminating a plurality of frame members formed by a punching press method, or a first member formed by a pressing method. And a second frame member formed by a punching press method is laminated on the upper surface of the frame member.

【0008】[0008]

【作用】本発明の半導体素子収納用パッケージによれ
ば、金属枠体を打ち抜きプレス法により成形された枠部
材を複数積層、あるいはしぼりプレス加工法により成形
された第1の枠部材の上面に打ち抜きプレス法により成
形された第2の枠部材を積層して形成したことからその
幅を狭くして、且つ高さを高いものとなすことができ、
その結果、半導体素子収納用パッケージを必要最小限の
大きさとし小型化を図ることができる。
According to the semiconductor device storage package of the present invention, a plurality of frame members formed by punching and pressing a metal frame are punched on the upper surface of the first frame member formed by pressing and pressing. Since the second frame member formed by the pressing method is formed by lamination, the width can be reduced, and the height can be increased,
As a result, it is possible to reduce the size of the package for storing the semiconductor element to the required minimum size and to reduce the size.

【0009】また前記金属枠体はその上面が平坦なもの
になるとともに該金属枠体への蓋体の接合が確実とな
り、半導体素子の気密封止の信頼性が大幅に向上して半
導体素子を長期間にわたり正常、且つ安定に作動させる
こともできる。
In addition, the metal frame has a flat upper surface, and the lid is securely joined to the metal frame. The reliability of hermetic sealing of the semiconductor element is greatly improved, and It can be operated normally and stably for a long time.

【0010】[0010]

【実施例】次に本発明を添付図面に基づき詳細に説明す
る。図1は本発明の半導体素子収納用パッケージの一実
施例を示し、1 は電気絶縁材料から成る絶縁基体であ
り、2 は蓋体である。
BRIEF DESCRIPTION OF THE DRAWINGS FIG. FIG. 1 shows an embodiment of a package for housing a semiconductor element according to the present invention, wherein 1 is an insulating base made of an electrically insulating material, and 2 is a lid.

【0011】前記絶縁基体1 はその上面中央部に半導体
素子3 が搭載される搭載部1aを有し、該搭載部1aには半
導体素子3 が樹脂、ガラス、ロウ材等の接着剤を介して
搭載固定される。
The insulating base 1 has a mounting portion 1a on which the semiconductor element 3 is mounted at the center of the upper surface, and the semiconductor element 3 is mounted on the mounting portion 1a via an adhesive such as resin, glass, brazing material or the like. Mounted and fixed.

【0012】前記絶縁基体1 は例えば、アルミナセラミ
ックス等から成り、アルミナ(Al 2O 3 ) シリカ(SiO2 )
、カルシア(CaO) 、マグネシア(MgO) 等の原料粉末に
適当な有機溶剤、溶媒を添加混合して泥漿状となすとと
もにこれを従来周知のドクターブレード法やカレンダー
ロール法を採用することによってセラミックグリーンシ
ート( セラミック生シート) を形成し、しかる後、前記
セラミックグリーンシートに適当な打ち抜き加工を施す
とともに複数枚積層し、高温( 約1600℃) で焼成するこ
とによって製作される。
The insulating substrate 1 is made of, for example, alumina ceramics, and is made of alumina (Al 2 O 3 ) silica (SiO 2 ).
, Calcia (CaO), magnesia (MgO) and other suitable raw materials are mixed with an appropriate organic solvent and solvent to form a slurry, which is then formed into a ceramic green by employing a conventionally known doctor blade method or calender roll method. A sheet (ceramic green sheet) is formed, and thereafter, the ceramic green sheet is subjected to an appropriate punching process, a plurality of sheets are laminated, and fired at a high temperature (about 1600 ° C.).

【0013】また前記絶縁基体1 には半導体素子3 が搭
載される搭載部1a周辺から底面にかけて導出する複数個
のメタライズ配線層4 が形成されており、該メタライズ
配線層4 の半導体素子搭載部1a周辺部には半導体素子3
の各電極がボンディングワイヤ5 を介して電気的に接続
され、また絶縁基体1 の底面に導出させた部位は外部電
気回路基板の配線導体に半田等のロウ材を介して取着接
続される。
A plurality of metallized wiring layers 4 extending from the periphery of the mounting portion 1a on which the semiconductor element 3 is mounted to the bottom surface are formed on the insulating base 1, and the semiconductor element mounting portion 1a of the metallized wiring layer 4 is formed. Semiconductor element 3 around
These electrodes are electrically connected via bonding wires 5, and a portion led out to the bottom surface of the insulating base 1 is attached and connected to a wiring conductor of an external electric circuit board via a brazing material such as solder.

【0014】前記メタライズ配線層4 はタングステン
(W) 、モリブデン(Mo)、マンガン(Mn)等の高融点金属粉
末から成り、該高融点金属粉末に適当な有機溶剤、溶媒
を添加混合して得た金属ペーストを従来周知のスクリー
ン印刷法等の厚膜手法を採用し、絶縁基体1 となるセラ
ミックグリーンシートに予め被着させておくことによっ
て絶縁基体1 の半導体素子搭載部1a周辺から底面にかけ
て導出するように被着形成される。
The metallized wiring layer 4 is made of tungsten
(W), molybdenum (Mo), manganese (Mn) and other high melting point metal powder, a suitable organic solvent to the high melting point metal powder, a metal paste obtained by adding and mixing a solvent, a conventionally well-known screen printing method By adopting a thick film technique such as that described above and previously attaching the ceramic green sheet to be the insulating substrate 1, the insulating substrate 1 is formed so as to be led out from the periphery of the semiconductor element mounting portion 1a to the bottom surface.

【0015】尚、前記メタライズ配線層4 はその露出す
る外表面にニッケル、金等の良導電性で、且つ耐蝕性に
優れた金属をメッキ法により1.0 乃至20.0μm の厚みに
層着させておくと、メタライズ配線層4 の酸化腐食を有
効に防止することができるとともにメタライズ配線層4
とボンディングワイヤ5 との接続及びメタライズ配線層
4 と外部電気回路基板の配線導体の接続が極めて強固な
ものとなる。従って、前記メタライズ配線層4 の酸化腐
食を防止し、メタライズ配線層4 とボンディングワイヤ
5 との接続及びメタライズ配線層4 と外部電気回路基板
の配線導体の接続との接続を強固なものとなすにはメタ
ライズ配線層4 の露出外表面にニッケル、金等を1.0 乃
至20.0μm の厚みに層着させておくことが好ましい。
The metallized wiring layer 4 is formed by plating a metal having good conductivity and excellent corrosion resistance, such as nickel or gold, to a thickness of 1.0 to 20.0 μm on the exposed outer surface by plating. In addition, the oxidation corrosion of the metallized wiring layer 4 can be effectively prevented and the metallized wiring layer 4 can be effectively prevented.
Connection between metal and bonding wire 5 and metallized wiring layer
The connection between 4 and the wiring conductor of the external electric circuit board is extremely strong. Therefore, oxidation corrosion of the metallized wiring layer 4 is prevented, and the metallized wiring layer 4 and the bonding wire are prevented.
To ensure a strong connection between the metallized wiring layer 4 and the connection between the metallized wiring layer 4 and the wiring conductor of the external electric circuit board, the exposed outer surface of the metallized wiring layer 4 is made of nickel, gold or the like having a thickness of 1.0 to 20.0 μm. It is preferable to make a layer.

【0016】また前記絶縁基体1 の上面には金属枠体6
が半導体素子搭載部1aを囲繞するようにして接合されて
おり、該金属枠体6 は絶縁基体1 とともに半導体素子3
を収容するための空所を形成する作用を為す。
A metal frame 6 is provided on the upper surface of the insulating base 1.
Are joined so as to surround the semiconductor element mounting portion 1a, and the metal frame 6 is attached to the semiconductor element 3 together with the insulating base 1.
And acts to form a cavity for accommodating the air.

【0017】前記金属枠体6 は第1 の枠部材6aと第2 の
枠部材6bを積層した構造を有しており、第1 の枠部材6a
及び第2 の枠部材6bは例えば、コバール金属(Fe-Ni-Co
合金) や42アロイ(Fe-Ni合金) 等の金属板を打ち抜き
プレス法により幅及び厚みを同じ大きさとして打ち抜く
ことによって成形され、第 1及び第2 の枠部材6a、6bを
積層した金属枠体6 はその高さが幅に対し2 倍となって
いる。従って、この半導体素子収納用パッケージによれ
ば金属枠体6 の高さを高くしたとしても幅が大きく広が
ることは皆無でパッケージを必要最小限の小型のものと
なすことができる。
The metal frame 6 has a structure in which a first frame member 6a and a second frame member 6b are laminated, and the first frame member 6a
And the second frame member 6b is, for example, Kovar metal (Fe-Ni-Co
Alloy) or 42 alloy (Fe-Ni alloy), etc., formed by punching out a metal plate of the same size and width by a punching press method and laminating the first and second frame members 6a and 6b. Body 6 is twice as high as its width. Therefore, according to the package for housing a semiconductor element, even if the height of the metal frame 6 is increased, the width does not greatly expand, and the package can be made as small as possible.

【0018】また前記金属枠体6 は打ち抜きプレス法に
より成形した第1 及び第2 の枠部材6a、6bを積層するこ
とによって形成されており、その上面は平坦である。従
って、後述する金属枠体6 の上面に蓋体2 をシームウエ
ルト法等の溶接によって接合させる際、両者の接合が確
実、強固となり、その結果、半導体素子3 の気密封止の
信頼性が大幅に向上し、半導体素子3 を長期間にわたり
正常、且つ安定に作動させることもできる。
The metal frame 6 is formed by laminating first and second frame members 6a and 6b formed by a punching press method, and the upper surface thereof is flat. Therefore, when the lid 2 is joined to the upper surface of the metal frame 6 to be described later by welding such as a seam-welt method, the joining between the two becomes reliable and strong, and as a result, the reliability of hermetic sealing of the semiconductor element 3 is greatly improved. And the semiconductor element 3 can be operated normally and stably for a long period of time.

【0019】尚、前記金属枠体6 の絶縁基体1 上面への
接合は絶縁基体1 の上面外周部に予めメタライズ金属層
を被着させておき、該メタライズ金属層に銀ロウ等のロ
ウ材を介しロウ付けすることによって接合され、また第
1 の枠部材6aと第2 の枠部材6bとは同じく銀ロウ等のロ
ウ材により接合され金属枠体6 となっている。
The metal frame 6 is bonded to the upper surface of the insulating substrate 1 by previously applying a metallized metal layer to the outer peripheral portion of the upper surface of the insulating substrate 1 and then applying a brazing material such as silver brazing to the metallized metal layer. Joined by brazing, and
The first frame member 6a and the second frame member 6b are similarly joined by a brazing material such as silver brazing to form a metal frame 6.

【0020】また前記金属枠体6 は打ち抜きプレス法に
よって成形された複数の枠部材を積層することによって
形成されるものに限らず、図2 に示す如く、しぼりプレ
ス加工法によって成形された第1 の枠部材6cと打ち抜き
プレス法によって成形された第2 の枠部材6dを積層する
ことによって形成してもよい。この場合、しぼりプレス
加工法によって成形された第1 の枠部材6cはその上部内
表面が曲面となるものの、上面に打ち抜きプレス法によ
って成形された平坦な第2 の枠部材6dが接合されるため
金属枠体6 の上面は平坦となり、その結果、金属枠体6
の上面に蓋体2をシームウエルト法等の溶接によって接
合させる際、両者の接合が確実、強固となり、半導体素
子3 の気密封止の信頼性を大幅に向上させて半導体素子
3 を長期間にわたり正常、且つ安定に作動させることが
できる。
The metal frame 6 is not limited to one formed by laminating a plurality of frame members formed by a punching press method. As shown in FIG. The frame member 6c may be formed by laminating the second frame member 6d formed by the punching press method. In this case, the first frame member 6c formed by the squeezing press method has a curved upper inner surface, but the flat second frame member 6d formed by the punching press method is joined to the upper surface. The upper surface of the metal frame 6 becomes flat, and as a result, the metal frame 6
When the lid 2 is joined to the upper surface of the semiconductor device by welding such as a seam-welt method, the joining of the two becomes reliable and strong, and the reliability of hermetic sealing of the semiconductor device 3 is greatly improved.
3 can operate normally and stably for a long time.

【0021】更に金属枠体6 をしぼりプレス加工法によ
って成形された第1 の枠部材6cと打ち抜きプレス法によ
って成形された第2 の枠部材6dとを積層することによっ
て形成すると金属枠体6 の幅を極めて狭いものとして、
且つ高さを高くなすことができる。そのためこの金属枠
体6 を用いれば半導体素子収納用パッケージをより必要
最小限の小型となすことができる。
Further, when the metal frame 6 is formed by laminating a first frame member 6c formed by squeezing press working and a second frame member 6d formed by punching pressing, the metal frame 6 With a very narrow width,
In addition, the height can be increased. Therefore, if this metal frame 6 is used, the package for housing the semiconductor element can be made as small as possible.

【0022】かくして本発明の半導体素子収納用パッケ
ージによれば、絶縁基体1 の半導体素子搭載部1aに半導
体素子3 を接着剤を介して搭載固定するとともに半導体
素子3 の各電極をメタライズ配線層4 にボンディングワ
イヤ5 を介して電気的に接続し、しかる後、絶縁基体1
の上面に接合された金属枠体6 に金属製の蓋体2 を載置
するとともにこれをシームウエルド法等の溶接により接
合させ、絶縁基体1 と金属枠体6 及び蓋体2 から成る容
器内部に半導体素子3 を気密に収容することによって最
終製品としての半導体装置となる。
Thus, according to the package for housing a semiconductor element of the present invention, the semiconductor element 3 is mounted and fixed on the semiconductor element mounting portion 1a of the insulating base 1 via an adhesive, and each electrode of the semiconductor element 3 is connected to the metallized wiring layer 4a. Is electrically connected to the insulating substrate 1 via a bonding wire 5.
A metal lid 2 is placed on a metal frame 6 joined to the upper surface of the container, and the metal lid 2 is joined by welding such as a seam welding method, so that the inside of the container including the insulating base 1, the metal frame 6 and the lid 2 is formed. The semiconductor device as a final product is obtained by hermetically housing the semiconductor element 3 in the housing.

【0023】尚、本発明は上述の実施例に限定されるも
のではなく、本発明の要旨を逸脱しない範囲であれば種
々の変更は可能である。
The present invention is not limited to the above-described embodiment, and various changes can be made without departing from the gist of the present invention.

【0024】[0024]

【発明の効果】本発明の半導体素子収納用パッケージに
よれば、金属枠体を打ち抜きプレス法により成形された
枠部材を複数積層、あるいはしぼりプレス加工法により
成形された第1の枠部材の上面に打ち抜きプレス法によ
り成形された第2の枠部材を積層して形成したことから
金属枠体の高さを高くしたとしても幅が大きく広がるこ
とは皆無でパッケージを必要最小限の小型のものとなす
ことができる。
According to the semiconductor device housing package of the present invention, the upper surface of the first frame member formed by laminating a plurality of frame members formed by punching and pressing a metal frame or by squeezing press processing. Since the second frame member formed by the punching press method is laminated and formed, even if the height of the metal frame body is increased, the width does not greatly expand, and the package is reduced to the necessary minimum size. I can do it.

【0025】また金属枠体はその上面が平坦となり、金
属枠体の上面に蓋体をシームウエルト法等の溶接によっ
て接合させる際、両者の接合が確実、強固となり、その
結果、半導体素子の気密封止の信頼性が大幅に向上し、
半導体素子を長期間にわたり正常、且つ安定に作動させ
ることもできる。
The upper surface of the metal frame becomes flat, and when the lid is joined to the upper surface of the metal frame by welding such as a seam-welt method, the joining of the two becomes reliable and strong. The reliability of hermetic sealing is greatly improved,
The semiconductor element can be normally and stably operated for a long time.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の半導体素子収納用パッケージの一実施
例を示す断面図である。
FIG. 1 is a cross-sectional view showing one embodiment of a semiconductor element storage package according to the present invention.

【図2】本発明の他の実施例を示す断面図である。FIG. 2 is a sectional view showing another embodiment of the present invention.

【図3】従来の半導体素子収納用パッケージの断面図で
ある。
FIG. 3 is a cross-sectional view of a conventional semiconductor element storage package.

【符号の説明】 1・・・・・絶縁基体 1a・・・・半導体素子搭載部 2・・・・・蓋体 3・・・・・半導体素子 4・・・・・メタライズ配線層 6・・・・・金属枠体 6a,6c・・・第1の枠部材 6b,6d・・・第2の枠部材[Description of Signs] 1 ... Insulating base 1a ... Semiconductor element mounting section 2 ... Lid 3 ... Semiconductor element 4 ... Metalized wiring layer 6 ... ... metal frame 6a, 6c ... first frame member 6b, 6d ... second frame member

───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.6,DB名) H01L 23/00 - 23/26──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. 6 , DB name) H01L 23/00-23/26

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】半導体素子が搭載される搭載部を有する絶
縁基体と、該搭載部を囲繞するようにして前記絶縁基体
に接合された金属枠体と、前記金属枠体の上面に溶接に
よって接合される蓋体とから成る半導体素子収納用パッ
ケージであって、前記金属枠体はしぼりプレス加工法に
より成形された第1の枠部材の上面に打ち抜きプレス法
より成形された第2の枠部材を積層して形成されている
ことを特徴とする半導体素子収納用パッケージ。
An insulating base having a mounting portion on which the semiconductor element is mounted; a metal frame joined to the insulating base so as to surround the mounting portion; and an upper surface of the metal frame formed by welding.
Accordingly, a semiconductor element storage package comprising a lid body to be joined, wherein the metal frame body is subjected to a squeezing press working method.
Pressing method on the upper surface of the first frame member formed by pressing
A semiconductor element housing package formed by laminating second frame members formed by molding .
JP4134711A 1992-05-27 1992-05-27 Package for storing semiconductor elements Expired - Fee Related JP2763446B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4134711A JP2763446B2 (en) 1992-05-27 1992-05-27 Package for storing semiconductor elements

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4134711A JP2763446B2 (en) 1992-05-27 1992-05-27 Package for storing semiconductor elements

Publications (2)

Publication Number Publication Date
JPH05335433A JPH05335433A (en) 1993-12-17
JP2763446B2 true JP2763446B2 (en) 1998-06-11

Family

ID=15134817

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4134711A Expired - Fee Related JP2763446B2 (en) 1992-05-27 1992-05-27 Package for storing semiconductor elements

Country Status (1)

Country Link
JP (1) JP2763446B2 (en)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR0139694B1 (en) * 1994-05-11 1998-06-01 문정환 Method of manufacturing semiconductor using solder ball and manufacture method
JPH11251488A (en) * 1998-03-05 1999-09-17 Sumitomo Metal Electronics Devices Inc Ceramic package
JP4562301B2 (en) * 2001-02-27 2010-10-13 京セラ株式会社 Electronic component storage package
JP2002353350A (en) * 2001-05-28 2002-12-06 Kyocera Corp Package for storing electronic part
DE102008025202B4 (en) * 2008-05-27 2014-11-06 Epcos Ag Hermetically sealed housing for electronic components and manufacturing processes
JP2010010618A (en) * 2008-06-30 2010-01-14 Kyocera Kinseki Corp Container for electronic component
CN103165569A (en) * 2011-12-19 2013-06-19 同欣电子工业股份有限公司 Semiconductor airtight packaging structure and manufacturing method thereof
JP6291354B2 (en) * 2014-05-28 2018-03-14 日本特殊陶業株式会社 Wiring board

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5856357A (en) * 1981-09-30 1983-04-04 Fujitsu Ltd Package for semiconductor device
JPH0746705B2 (en) * 1985-08-02 1995-05-17 富士通株式会社 Semiconductor device
JPH03290952A (en) * 1990-04-06 1991-12-20 Hitachi Ltd Semiconductor package

Also Published As

Publication number Publication date
JPH05335433A (en) 1993-12-17

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