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JP2638561B2 - Mask formation method - Google Patents

Mask formation method

Info

Publication number
JP2638561B2
JP2638561B2 JP11152895A JP11152895A JP2638561B2 JP 2638561 B2 JP2638561 B2 JP 2638561B2 JP 11152895 A JP11152895 A JP 11152895A JP 11152895 A JP11152895 A JP 11152895A JP 2638561 B2 JP2638561 B2 JP 2638561B2
Authority
JP
Japan
Prior art keywords
pattern
mask
phase shift
exposure
region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP11152895A
Other languages
Japanese (ja)
Other versions
JPH0851068A (en
Inventor
宏 福田
恒男 寺澤
昇雄 長谷川
稔彦 田中
卓 大嶋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
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Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP11152895A priority Critical patent/JP2638561B2/en
Publication of JPH0851068A publication Critical patent/JPH0851068A/en
Application granted granted Critical
Publication of JP2638561B2 publication Critical patent/JP2638561B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Preparing Plates And Mask In Photomechanical Process (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は、寸法0.2μm〜0.1
μm以下の極微細パタンを有する半導体または超電導素
子の製造厘方法に係り、特にこれらの素子に好適なパタ
ン形成方法に関する。
BACKGROUND OF THE INVENTION The present invention relates to a size of 0.2 .mu.m to 0.1 .mu.m.
The present invention relates to a method for manufacturing a semiconductor or a superconducting element having an ultrafine pattern of μm or less, and particularly to a pattern forming method suitable for these elements.

【0002】[0002]

【従来の技術】パーミアブル・ベース・トランジスタ
(以下PBT)または各種量子井戸アレイデバイス、超
マトリクス固体発振子、ラテラル超格子FET、共鳴ト
ンネリング効果デバイス等の量子効果デバイスの作製に
おいては、素子内に極めて微細な格子状,縞状,又は点
状パタンの集合等を作製する必要がある。これらのデバ
イスの多くは量子効果をねらっており、そのパタン周期
は、0.1μm程度からそれ以下であることが望まれ
る。
2. Description of the Related Art In the manufacture of quantum effect devices such as permeable base transistors (PBT) or various quantum well array devices, super-matrix solid-state oscillators, lateral superlattice FETs, resonance tunneling effect devices, etc. It is necessary to produce a set of fine lattice, stripe, or point patterns. Many of these devices aim at the quantum effect, and the pattern period is desired to be about 0.1 μm or less.

【0003】従来、これらの素子はEB(電子ビーム)
又はFIB(集束イオンビーム)の直接描画により作製
されてきた。EBを用いた量子効果デバイスの作製に関
しては、例えば、ソリッド・ステート・テクノロジー,
1985年,10月号,第125頁から第129頁(So
lid State Technology/Octover,1985,pp125
−129)に論じられている。
[0003] Conventionally, these elements are EB (electron beam).
Alternatively, it has been manufactured by direct writing of FIB (focused ion beam). Regarding the fabrication of quantum effect devices using EB, for example, Solid State Technology,
October 1985, pages 125 to 129 (So
lid State Technology / Octover, 1985, pp125
-129).

【0004】一方、縮小投影光法による光リソグラフィ
の限界解像度は、露光波長に比例し、縮小レンズの開口
数に反比例する。現在エキシマレーザ(KrFレーザ,波
長248nm)と開口数0.4〜0.5の縮小レンズを用
いて0.3μm程度が達成されている。又、開口数0.5
の反射光学系とArFエキシマレーザ(波長193n
m)を用いて0.13μmを解像した例がある。(ジャ
ーナル オブ バキューム サイエンス アンド テク
ノロジー B5(1),1987年,1/2月号,第3
89頁から第390頁(J. Vac. Sci. Technol. B5(1),
Jan/Feb 1987,pp389−390))。
On the other hand, the limit resolution of photolithography by the reduced projection light method is proportional to the exposure wavelength and inversely proportional to the numerical aperture of the reduction lens. At present, about 0.3 μm is achieved by using an excimer laser (KrF laser, wavelength 248 nm) and a reducing lens having a numerical aperture of 0.4 to 0.5. The numerical aperture is 0.5
Reflective optical system and ArF excimer laser (wavelength 193n)
There is an example in which 0.13 μm is resolved using m). (Journal of Vacuum Science and Technology B5 (1), 1987, January / February, No.3
Pages 89 to 390 (J. Vac. Sci. Technol. B5 (1),
Jan / Feb 1987, pp 389-390)).

【0005】ところで、縮小投影露光法における解像限
界を向上する方法に位相シフト法がある。位相シフト法
によれば、その解像限界は通常の透過型マスクによる露
光法を用いた場合の2倍程度向上する。従って、これに
よれば0.15μmから0.1μm以下の微細パタンを形
成することが可能である。この位相シフト法は、特別な
露光装置を必要とせず、通常の縮小投影露光装置におい
て、従来の透過型マスク(レチクル)を位相シフトマス
ク(レチクル)に変更するだけで行なうことができる。
位相シフト法に関しては例えば、アイ・イー・イー・イ
ー;トランザクション オン エレクトロン デバイシ
ズ,イーデー31,ナンバー6(1984)第753頁
から第763頁(IEEE, Trans. Electron Devices, Vo
l, DE−31,No.6(1984),pp753−76
3)に論じられている。
Incidentally, there is a phase shift method as a method for improving the resolution limit in the reduced projection exposure method. According to the phase shift method, the resolution limit is improved about twice as much as the case where the exposure method using a normal transmission mask is used. Therefore, according to this, it is possible to form a fine pattern of 0.15 μm to 0.1 μm or less. This phase shift method does not require a special exposure apparatus, and can be performed only by changing a conventional transmission mask (reticle) to a phase shift mask (reticle) in a normal reduction projection exposure apparatus.
Regarding the phase shift method, see, for example, IEE, Transaction on Electron Devices, Eday 31, Number 6 (1984), pp. 753 to 763 (IEEE, Trans. Electron Devices, Vo.
1, DE-31, No. 6 (1984), pp. 753-76.
3).

【0006】また、光を用いて縮小投影露光法の解像限
界以下のパタンを形成する別の方法に、ホログラフィ法
があるが、このホログラフィ法は特殊な露光装置を必要
とし、しかもパタンはウエハの全面に形成され、そのパ
タンを、基板上に既に存在するパタンに対して位置合わ
せすることができない。この様なホログラフィ法につい
ては、例えば昭和59年秋季、第45回応用物理学会学
術講演会、講演予講集第242頁に論じられている。
Another method for forming a pattern below the resolution limit of the reduced projection exposure method using light is a holography method. This holography method requires a special exposure apparatus, and the pattern is a wafer. Cannot be aligned with the pattern already existing on the substrate. Such a holography method is discussed, for example, in the fall of 1984, in the 45th Annual Meeting of the Japan Society of Applied Physics, Preliminary Lecture Book, p. 242.

【0007】[0007]

【発明が解決しようとする課題】上記のEB,FIBに
よる極微細パタンの描画作製には、多大の時間を要し、
経済性が悪いという問題点があった。
It takes a lot of time to draw and form an ultra-fine pattern using the above-described EB and FIB.
There was a problem that the economy was poor.

【0008】一方、縮小投影露光法の限界解像度ではP
BT、量子効果デバイス等に必要な0.1μm以下のパ
タンを形成することは非常に困難である。
On the other hand, the limit resolution of the reduced projection exposure method is P
It is very difficult to form a pattern of 0.1 μm or less required for BTs, quantum effect devices and the like.

【0009】位相シフト法を用いればこれを達成するこ
とが可能である。しかしながら、位相シフト法の弱点と
して、実際のLSIパタンの様な複雑なマスクパタンに
対応するのが困難なことがあげられる。位相シフト法
は、単純なラインアンドスペースパタン(以下L/
S)、格子パタン、点状パタン等の作製に関して、非常
に有効な技術である。
This can be achieved by using the phase shift method. However, the weak point of the phase shift method is that it is difficult to deal with a complicated mask pattern such as an actual LSI pattern. The phase shift method uses a simple line-and-space pattern (hereinafter, L /
This is a very effective technique for producing S), lattice patterns, point patterns, and the like.

【0010】本発明の目的は、極微細パタンを有するデ
バイスのパタン形成において、上記問題点を解決し、簡
便かつスループットの大きい、経済性に優れた微細素子
の形成方法を提供することにある。
It is an object of the present invention to solve the above-mentioned problems in forming a pattern of a device having an extremely fine pattern, and to provide a simple and high-throughput method for forming a fine element excellent in economy.

【0011】[0011]

【課題を解決するための手段】上記目的は、上記デバイ
スのパタン形成に際して上記デバイスの極微細パタン領
域(例えばPBTのグリッド部分)の露光に対しては位
相シフトマスクを、また、その他のパタン領域の露光に
は通常の透過型マスクを用いた縮小投影露光で適用する
ことにより達成される。
The object of the present invention is to provide a phase shift mask for exposing an extremely fine pattern area (for example, a grid portion of a PBT) of the device when forming the pattern of the device, and to provide another pattern area. Is achieved by applying a reduced projection exposure using a normal transmission mask.

【0012】[0012]

【作用】本発明が対象とするデバイスのパタンは、単純
な繰り返し構造を有する極微細パタンの密集領域と、制
御電極や配線等の比較的複雑な構造を有する回路領域に
2分される。これらの2つの領域はデバイス製造プロセ
スにおける同一層内に混在する場合もあり、又、別々の
層として存在する場合もある。
The pattern of the device to which the present invention is applied is divided into two regions: a dense region of an extremely fine pattern having a simple repetitive structure, and a circuit region having a relatively complicated structure such as control electrodes and wirings. These two regions may coexist in the same layer in the device manufacturing process, or may exist as separate layers.

【0013】前者の極微細パタン領域は単純なL/S、
点状パタン集合、格子状パタンで、その寸法は0.1μ
m程度、もしくはそれ以下であり、その形状も比較的単
純である。この領域内のパタン形成は位相シフトマスク
(レチクル)を用いた縮小投影露光法により可能とな
る。
The former ultrafine pattern region has a simple L / S,
A set of point-like patterns and lattice-like patterns with dimensions of 0.1μ
m or less, and its shape is relatively simple. Pattern formation in this region can be performed by a reduced projection exposure method using a phase shift mask (reticle).

【0014】一方、後者の回路領域におけるパタンの寸
法は前者より大きく、従来の透過型マスク(レチクル)
を用いた縮小投影露光法により形成するのが適してい
る。
On the other hand, the size of the pattern in the latter circuit area is larger than that of the former, and the conventional transmission mask (reticle) is used.
It is suitable to form by a reduced projection exposure method using.

【0015】上記2つの領域を別々に露光する際には、
両者の位置合せを行なう必要がある。通常合せ精度は少
なくとも最小寸法の半分以下に抑えなければならない。
従って、0.1μmのパタンに対しては0.05μm以下
の合せ精度が必要となるが、現在この様な精度をもつ露
光装置はない。しかし、本発明における2つの領域間の
合せ精度は、通常の露光装置の保障する程度の値で十分
である。何故ならば、本発明の対象となるデバイスにお
ける極微細パタンは全体として機能し、従って極微細パ
タン領域と回路パタン領域の相対位置は所定の範囲内に
収める必要があるものの、極微細パタンの一つひとつの
位置精度はそれほど厳密さを要求されない。
When exposing the above two regions separately,
It is necessary to align both. Usually the alignment accuracy must be kept at least below half of the minimum dimension.
Therefore, an alignment accuracy of 0.05 μm or less is required for a 0.1 μm pattern, but there is no exposure apparatus having such an accuracy at present. However, the alignment accuracy between the two regions in the present invention is sufficient if the value is assured by a normal exposure apparatus. The reason is that the micropatterns in the device targeted by the present invention function as a whole, so that the relative positions of the micropattern region and the circuit pattern region need to be within a predetermined range, but each of the micropatterns Is not required to be so precise.

【0016】前記二つの領域が同一層内に混在する場合
には、一枚のマスク上に位相シフトマスク領域と透過型
マスク領域を混在させることもできる。これを用いれ
ば、上記極微細パタン領域と回路パタン領域を1枚のマ
スクで同時に露光することができる。但し、この場合、
二つの領域の接続部において解像不良の生じる恐れがあ
る。即ち、位相の異なる2つの透光部が接する場合、干
渉によりここで光強度が低下する。この様なパタンの配
置は避けなければならない。
When the two regions are mixed in the same layer, the phase shift mask region and the transmission type mask region can be mixed on one mask. If this is used, the extremely fine pattern region and the circuit pattern region can be simultaneously exposed with one mask. However, in this case,
There is a risk that poor resolution may occur at the connection between the two regions. That is, when two translucent portions having different phases come into contact with each other, the light intensity is reduced here due to interference. Such pattern arrangement must be avoided.

【0017】本発明によれば、パタンの露光は縮小投影
露光法により行なわれるので、電子ビーム,集束イオン
ビームの直接描画による方法に比してはるかに短時間で
これを完了することができる。
According to the present invention, since the exposure of the pattern is performed by the reduced projection exposure method, it can be completed in a much shorter time than the method of direct writing of the electron beam and the focused ion beam.

【0018】又、本発明によれば、特殊な露光装置を必
要とせず、露光フィールド内の所望の位置に極微細パタ
ンを形成することができるため、ホログラフィ法より有
利である。
Further, according to the present invention, it is possible to form an extremely fine pattern at a desired position in an exposure field without requiring a special exposure apparatus, which is more advantageous than the holographic method.

【0019】[0019]

【実施例】【Example】

(実施例1)以下、本発明を用いたPBTの製造方法の
実施例を示す。
(Embodiment 1) Hereinafter, an embodiment of a method for manufacturing a PBT using the present invention will be described.

【0020】まず、キャリア収集電極層に形成したGa
As基板上にさらにW薄膜を形成し、その上に、下層有
機膜/中間層無機膜/上層レジスト膜の3層構造からな
る、いわゆる3層レジストを形成した。上層レジストと
してはPMMA(ポリメチルメタクリシート)を用い
た。次に、図1(a)に示した様なPBTの制御電極領
域の極微細L/Sだけを有する位相シフトレチクルを用
いて露光を行なった。位相シフトレチクルの微細L/S
における隣り合う透光部は、照明光の位相を互いに18
0°反転させる様配置されている。次に、図1(b)に
示した様な制御電極周辺回路パタンを有する透過型レチ
クルに交換し、露光を行なった。
First, Ga formed on the carrier collecting electrode layer
A W thin film was further formed on an As substrate, and a so-called three-layer resist having a three-layer structure of a lower organic film / intermediate inorganic film / upper resist film was formed thereon. PMMA (polymethyl methacrylate sheet) was used as the upper resist. Next, exposure was performed using a phase shift reticle having only a very small L / S in the control electrode region of the PBT as shown in FIG. Fine L / S of phase shift reticle
Adjacent to each other, the phases of the illumination light
It is arranged to be inverted by 0 °. Next, the reticle was replaced with a transmissive reticle having a control electrode peripheral circuit pattern as shown in FIG.

【0021】上記2つの領域に対する露光は、基板を露
光装置の基板ステージ上に固定したままレチクルのみを
変更して、連続的に行なわれる。各々の露光において位
置合わせ操作を行なうことはいうまでもない。又は、上
記2つの領域に対する露光の順番は特に規定しない。使
用した露光装置の光源はKrFエキシマレーザ、光学系
の開口数は0.6である。1露光フィールドにおいて上
記2枚のレチクル各々の露光に要する時間は約5秒であ
った。一方、電子線描画装置を用いて同一パタンの露光
を行なったところ、これに要する時間は約600秒であ
った。
Exposure to the two regions is performed continuously while only the reticle is changed while the substrate is fixed on the substrate stage of the exposure apparatus. It goes without saying that a positioning operation is performed in each exposure. Alternatively, the order of exposure for the two regions is not particularly defined. The light source of the exposure apparatus used was a KrF excimer laser, and the numerical aperture of the optical system was 0.6. The time required for exposure of each of the two reticles in one exposure field was about 5 seconds. On the other hand, when the same pattern was exposed using an electron beam lithography apparatus, the time required for the exposure was about 600 seconds.

【0022】次に、上記上層レドストの現像を行ない、
図1(c)に示した様な上層レジストパタンを得た。こ
れを反応性イオンエッチングにより順次前記中間層、下
層へ転写した。その結果、上記下層有機膜において前記
極微細制御電極パタン領域におけるアスペクト比の高い
矩形断面形状を有するL/Sパタンと、前記周辺回路パ
タンの両方が得られた。
Next, the upper layer redest is developed,
An upper resist pattern as shown in FIG. 1 (c) was obtained. This was sequentially transferred to the intermediate layer and the lower layer by reactive ion etching. As a result, in the lower organic film, both the L / S pattern having a rectangular cross-sectional shape having a high aspect ratio in the ultrafine control electrode pattern region and the peripheral circuit pattern were obtained.

【0023】こうして形成した下層有機層パタンをマス
クとしてW膜のドライエッチングを行ない、制御電極パ
タンを形成した後、その上にGaAsを成長させ制御電
極を埋め込み、ひき続きキャリア注入電極、配線等を形
成してPBTを作製した。上記制御電極パタン以外の露
光は全て透過型マスクを用いた。作製したPBTの電気
特性を評価した結果、所期の性能が得られた。
Using the lower organic layer pattern thus formed as a mask, dry etching of the W film is performed to form a control electrode pattern. After that, GaAs is grown on the control electrode pattern, and the control electrode is buried. The PBT was formed. All the exposures other than the control electrode pattern used a transmission mask. As a result of evaluating the electrical characteristics of the produced PBT, the expected performance was obtained.

【0024】なお、図1は説明のための模式的な平面で
あり、必ずしも実際のトランジスタのレイアウトを表示
したものではない。また、デバイス構造、基板材料,制
御電極材料,レジスト材料およびプロセス,露光装置等
に関しても、本実施例に示したのに限らず使用すること
ができる。
FIG. 1 is a schematic plan view for explanation, and does not always show an actual transistor layout. Further, the device structure, substrate material, control electrode material, resist material and process, exposure apparatus, and the like can be used without being limited to those described in the present embodiment.

【0025】本実施例の露光過程は、PBTに限らず単
純な極微細L/Sパタンと周辺回路の混在する他のデバ
イス例えばラテカル1次元超格子FET等に対しても適
用できる。
The exposure process of this embodiment can be applied not only to PBT but also to other devices in which a simple ultrafine L / S pattern and peripheral circuits are mixed, such as a lateral one-dimensional superlattice FET.

【0026】(実施例2)PBTにおいては、極微細パ
タン領域と回路パタン領域が同一層(制御電極層)内に
混在するので、上記各領域に対応して位相シフトマスク
領域と透過型マスク領域の混在するレチクルによりパタ
ンを形成できる。このためのマスクを図2に示す。前記
実施例1においては、制御電極形状は図1(c)に示し
たごとくくし型であった。しかし本方法においては位相
シフトマスク領域と透過マスク領域を完全に分離するた
めに、透過型マスク領域内の完全な遮光部中に位相シフ
ト型マスク領域(図2中点線内)を配置した。
(Embodiment 2) In a PBT, since a very fine pattern region and a circuit pattern region are mixed in the same layer (control electrode layer), the phase shift mask region and the transmission type mask region correspond to each of the above regions. A pattern can be formed by a reticle in which is mixed. FIG. 2 shows a mask for this purpose. In Example 1, the shape of the control electrode was a comb shape as shown in FIG. However, in this method, in order to completely separate the phase shift mask region and the transmission mask region, the phase shift mask region (within a dotted line in FIG. 2) is arranged in a complete light shielding portion in the transmission mask region.

【0027】(実施例3)本発明を用いて超マトリクス
固体発振素子の製造方法に関する一実施例を示す。 G
aAs基板上にポジ型レジストPMMAを塗布し、図3
に示す様なドット状の透光部の集合をもつ位相シフトマ
スクで露光を行なった。その後現像して図3の透光部の
各々に対応したレジスト開口部を得た。位相シフトマス
クの各透光部は照明光の位相を上下左右の両方向に交互
に180°反転させる様に(市松模様状に)配置されて
いる。なお、位相シフトマスクには、図3に示したドッ
ト状透光部の各々の周囲に位相反転用のより微細な透光
部パタンを設けてもよい。
(Embodiment 3) An embodiment of a method for manufacturing a super-matrix solid-state oscillation device using the present invention will be described. G
A positive resist PMMA was applied on the aAs substrate, and FIG.
Exposure was performed using a phase shift mask having a set of dot-shaped translucent portions as shown in FIG. Thereafter, development was performed to obtain resist openings corresponding to each of the light transmitting portions in FIG. Each translucent portion of the phase shift mask is arranged (in a checkerboard pattern) so that the phase of the illumination light is alternately inverted by 180 ° in both the upper, lower, left and right directions. The phase shift mask may be provided with a finer light-transmitting portion pattern for phase inversion around each dot-shaped light-transmitting portion shown in FIG.

【0028】次に、メタライゼーションを行ない、レジ
スト上およびレジスト開口部の基板上に金属を蒸着した
後、レジストを除去してリフトオフ法により基板上にメ
タルドット行列を形した。ひき続き電極等を形成して超
マトリクス固体発振素子を製造した。
Next, metallization was carried out, and after depositing metal on the resist and on the substrate at the resist opening, the resist was removed and a metal dot matrix was formed on the substrate by a lift-off method. Subsequently, electrodes and the like were formed to manufacture a super-matrix solid-state oscillation device.

【0029】ここでは固体発振素子の製造への実施例を
示したが、本実施例のレジストパタン形成工程をGaA
s基板上のメタライゼーションに代えて、他の様々なプ
ロセスと組み合せることにより、種々のデバイスへの応
用が可能である。例えばGaAs基板上にGaAlAs
薄膜を成長させた後、ネガ型レジストと本実施例による
位相シフトマスクを用いてパタン形成を行なうと、図3
のドット状透光部の各々に対応してレジストパタンが残
る。これをマスクにGaAlAsの異方性エッチングを
行ない、適当な後処理を行なうことにより量子井戸行列
を形成することができる。同様に、ラテラルFET超格
子、共鳴トンネリング効果トランジスタ等への応用が可
能である。
Although the embodiment for manufacturing the solid-state oscillation element has been described here, the resist pattern forming step of this embodiment is performed by using GaAs.
Instead of metallization on the s-substrate, it can be applied to various devices by combining with various other processes. For example, GaAlAs on a GaAs substrate
After the growth of the thin film, pattern formation is performed using a negative resist and the phase shift mask according to the present embodiment.
The resist pattern remains corresponding to each of the dot-shaped light transmitting portions. The quantum well matrix can be formed by performing anisotropic etching of GaAlAs using this as a mask and performing appropriate post-processing. Similarly, application to a lateral FET superlattice, a resonant tunneling effect transistor, or the like is possible.

【0030】(実施例4)本発明を用いた超マトリクス
固体発振素子の製造方法に関する別の実施例を示す。
(Embodiment 4) Another embodiment relating to a method for manufacturing a super-matrix solid-state oscillation device using the present invention will be described.

【0031】前記実施例3におけるポジ型レジストをネ
ガ型レジストに置き換え、さらに、露光プロセスを以下
の様に変更した。まず図4に示す様なマスクA,マスク
B,マスクCを用意した。マスクA及びBはL/S位相
シフトマスクで、各々におけるL/Sは互いに直交して
いるか、もしくは基準方向に対して異なる角度をもって
いる。A,B及びCの3枚のマスクを用いて、同一レジ
スト膜上に重ね露光することにより、実施例3と同様の
レジストパタンを得た。即ちドット行列はマスクA及び
BにおけるL/Sの重なり部分に形成され、マスクCは
ドット行列領域の範囲を規定する。本実施例によれば、
実施例3と比べてドット行列の周期をより小さくするこ
とが可能で、しかもレジストの平面的形状を角ばらせる
ことができる。
The positive resist in Example 3 was replaced with a negative resist, and the exposure process was changed as follows. First, a mask A, a mask B, and a mask C as shown in FIG. 4 were prepared. The masks A and B are L / S phase shift masks, and the L / S in each is orthogonal to each other or has a different angle with respect to a reference direction. Using the three masks A, B, and C, the same resist film was overexposed to obtain the same resist pattern as in Example 3. That is, the dot matrix is formed at the overlapping portion of L / S in the masks A and B, and the mask C defines the range of the dot matrix area. According to the present embodiment,
The period of the dot matrix can be made smaller as compared with the third embodiment, and the planar shape of the resist can be made square.

【0032】本実施例のパタン形式工程が、実施例3と
同様様々なデバイスに応用可能であることはいうまでも
ない。
It goes without saying that the pattern type process of this embodiment can be applied to various devices as in the third embodiment.

【0033】[0033]

【発明の効果】以上本発明による半導体又は超電導体装
置の製造方法によれば、量子効果素子等における0.1
μm程度からそれ以下の寸法のパタンから成る極微細パ
タン領域を含む回路パタンの形成過程において、上記極
微細パタン領域の露光を位相シフト法を用いた縮小投影
露光法により、それ以外の回路パタンを通常の露光法に
より各々独立に行なうことにより、上記パタン形成に要
する時間を著しく短縮するとともに、装置コストを低減
することができる。
As described above, according to the method of manufacturing a semiconductor or superconductor device according to the present invention, 0.1% in a quantum effect element or the like is used.
In the process of forming a circuit pattern including a micropattern region composed of a pattern having a size of about μm or less, the exposure of the ultrafine pattern region is performed by a reduced projection exposure method using a phase shift method, thereby exposing other circuit patterns. By independently performing each of them by a normal exposure method, the time required for forming the pattern can be significantly reduced, and the cost of the apparatus can be reduced.

【0034】これにより、上記半導体・超電導体素子の
量産における経済性を向上させることができる。また、
上記素子が集積化された場合において、これらの効果は
一層顕著となる。
This makes it possible to improve the economical efficiency in mass production of the semiconductor / superconductor element. Also,
These effects become more remarkable when the above elements are integrated.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の実施例におけるマスクパタンの平面
図。
FIG. 1 is a plan view of a mask pattern according to an embodiment of the present invention.

【図2】透過型マスク領域内の遮光領域中に位相シフト
マスク領域を配置したことを示す図。
FIG. 2 is a diagram showing that a phase shift mask region is arranged in a light shielding region in a transmission type mask region.

【図3】ドット状透光部の集合を示す図。FIG. 3 is a diagram showing a set of dot-shaped light transmitting portions.

【図4】マスクパタンの平面図。FIG. 4 is a plan view of a mask pattern.

───────────────────────────────────────────────────── フロントページの続き (72)発明者 田中 稔彦 東京都国分寺市東恋ケ窪1丁目280番地 株式会社日立製作所中央研究所内 (72)発明者 大嶋 卓 東京都国分寺市東恋ケ窪1丁目280番地 株式会社日立製作所中央研究所内 (56)参考文献 特開 昭58−173744(JP,A) 特開 昭62−189468(JP,A) ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Toshihiko Tanaka 1-280 Higashi-Koikekubo, Kokubunji-shi, Tokyo Inside the Hitachi, Ltd. Central Research Laboratory (72) Inventor Taku Oshima 1-280 Higashi-Koikekubo, Kokubunji-shi, Tokyo Hitachi, Ltd. Central Research Laboratory (56) References JP-A-58-173744 (JP, A) JP-A-62-189468 (JP, A)

Claims (2)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】所望のパターンを与えるマスクパターンの
露光領域を、第1の露光領域と第2の露光領域に分解す
る工程、 第1の露光領域を含む第1のマスクと第2の露光領域を
含む第2のマスクを形成する工程、を含み上記第1のマ
スクと上記第2のマスクの少なくともどちらか一方は、
隣接する光透過部を通過する光の位相を反転させる位相
シフトパターンを含む位相シフトマスクであることを特
徴とするマスク形成方法。
A step of decomposing an exposure area of a mask pattern that gives a desired pattern into a first exposure area and a second exposure area; a first mask including the first exposure area and a second exposure area Forming a second mask including at least one of the first mask and the second mask,
A method for forming a mask, comprising: a phase shift mask including a phase shift pattern for inverting the phase of light passing through an adjacent light transmitting portion.
【請求項2】上記所望のパターンが、第1のマスクによ
り実質的に形成される非露光領域、及び第2のマスクに
より実質的に形成される非露光領域の和領域に一致す
る、ことを特徴とする請求項1記載のマスク形成方法。
2. The method according to claim 1, wherein the desired pattern coincides with a sum area of a non-exposure area substantially formed by the first mask and a non-exposure area substantially formed by the second mask. 2. The method according to claim 1, wherein the mask is formed.
JP11152895A 1995-05-10 1995-05-10 Mask formation method Expired - Lifetime JP2638561B2 (en)

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Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP11242288A Division JP2650962B2 (en) 1988-05-11 1988-05-11 Exposure method, element forming method, and semiconductor element manufacturing method

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JP2638561B2 true JP2638561B2 (en) 1997-08-06

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