JP2650962B2 - Exposure method, element forming method, and semiconductor element manufacturing method - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor or superconducting element having an ultrafine pattern having a size of 0.2 μm to 0.1 μm or less, and particularly to a pattern formation suitable for these elements. About the method.

[Conventional technology]

In the manufacture of quantum effect devices such as permeable base transistors (hereinafter PBT) or various quantum well array devices, super-matrix solid-state oscillators, lateral superlattice FETs, and resonant tunneling effect devices, extremely fine lattices are formed in the device. It is necessary to produce a set of striped or dotted patterns. Many of these devices aim at the quantum effect, and its pattern period is desired to be about 0.1 μm or less.

Conventionally, these devices have been manufactured by direct writing of EB (electron beam) or FIB (focused ion beam). EB
For the production of quantum effect devices using, for example,
Solid State Technology, October 1985, October
Pages 125 to 129 (Solid State Technology / October, 1
985, pp 125-129).

On the other hand, the limit resolution of optical lithography by the reduction projection exposure method is proportional to the exposure wavelength and inversely proportional to the numerical aperture of the reduction lens. Excimer laser (KrF laser, wavelength 248nm)
Using a reducing lens having a numerical aperture of 0.4 to 0.5, a thickness of about 0.3 μm has been achieved. There is also an example in which 0.13 μm is resolved using a reflective optical system having a numerical aperture of 0.5 and an ArF excimer laser (wavelength 193 nm). (Journal of Bakiyum Science and Technology B5 (1), 1987, January, pp. 389-390 (J. Vac. Sci. Technol. B5
(1), Jan / Feb 1987, pp 389-390)).

Incidentally, there is a phase shift method as a method for improving the resolution limit in the reduction projection exposure method. According to the phase shift method,
The resolution limit is improved about twice as much as the case where the exposure method using a normal transmission mask is used. Therefore, according to this, 0.15
It is possible to form a fine pattern of μm to 0.1 μm or less. This phase shift method does not require a special exposure apparatus, and a conventional transmission type mask (reticle) is replaced with a phase shift mask (reticle) in a normal reduction projection exposure apparatus.
It can be done simply by changing to Regarding the phase shift method, see, for example, IEE; Transaction on Electron Devices, E3
1, Number 6 (1984) pp. 753 to 763 (IEEE, Tran
s, Electron Devices, Vol, ED-31, No. 6 (1984), pp753-
763).

Another method of forming a pattern below the resolution limit of the reduced projection exposure method using light is a holographic method.
The holographic method requires a special exposure apparatus, and the pattern is formed on the entire surface of the wafer, and the pattern cannot be aligned with the pattern already existing on the substrate. Such a holographic method is discussed, for example, in the autumn of 1984, at the 45th Annual Conference of the Japan Society of Applied Physics, Preliminary Lecture Book, p. 242.

[Problems to be solved by the invention]

The above-described EB and FIB drawing and manufacturing of an extremely fine pattern requires a great deal of time, and has a problem of low economic efficiency.

On the other hand, it is very difficult to form a pattern of 0.1 μm or less required for a PBT, a quantum effect device or the like at the limit resolution of the reduced projection exposure method.

This can be achieved by using the phase shift method. However, the weak point of the phase shift method is that it is difficult to deal with a complicated mask pattern such as an actual LSI pattern. The phase shift method is a very effective technique for producing a simple line-and-space pattern (hereinafter, L / S), a lattice pattern, a point pattern, and the like.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above problems in forming a pattern of a device having an extremely fine pattern, and to provide a simple and large-throughput method for forming a fine element excellent in economy.

[Means for solving the problem]

The object of the present invention is to provide a phase shift mask for exposing an extremely fine pattern region (for example, a grid portion of PBT) of the device when forming a pattern of the device, and a normal transmission type mask for exposing the other pattern regions. This is achieved by applying with reduced projection exposure using

[Action]

The pattern of the device to which the present invention is directed is divided into a dense region of an extremely fine pattern having a simple repeating structure and a circuit region having a relatively complicated structure such as a control electrode and a wiring. These two regions may coexist in the same layer in the device manufacturing process, or may exist as separate layers.

The former ultrafine pattern region is a simple L / S, a set of point-like patterns, and a lattice-like pattern, and its dimensions are about 0.1 μm or less, and its shape is relatively simple. Pattern formation in this region can be performed by a reduced projection exposure method using a phase shift mask (reticle).

On the other hand, the size of the pattern in the latter circuit area is larger than that of the former, and it is suitable to form the pattern by a reduced projection exposure method using a conventional transmission mask (reticle).

When exposing the above two regions separately, it is necessary to align them. The image alignment accuracy must be kept at least less than half the minimum dimension. Therefore, 0.
An alignment accuracy of 0.05 μm or less is required for a 1 μm pattern, but there is currently no exposure apparatus having such an accuracy.
However, the alignment accuracy between the two regions in the present invention is sufficient if the value is assured by a normal exposure apparatus. This is because the ultrafine pattern in the device targeted by the present invention functions as a whole, so that the relative positions of the inverse fine pattern region and the circuit pattern region need to be within a predetermined range, Each position accuracy is not required to be so strict.

When the two regions are mixed in the same layer, the phase shift mask region and the transmission type mask region can be mixed on one mask. If this is used, the extremely fine pattern region and the circuit pattern region can be simultaneously exposed with one mask. However, in this case, there is a possibility that poor resolution may occur at the connection between the two regions. That is, when two translucent portions having different phases come into contact with each other, the light intensity is reduced here due to interference. Such pattern arrangement must be avoided.

According to the present invention, the pattern exposure is performed by the reduced projection exposure method, and can be completed in a much shorter time than the method using the direct drawing of the electron beam and the focused ion beam.

According to the present invention, no special exposure apparatus is required,
It is more advantageous than the holographic method because an extremely fine pattern can be formed at a desired position in the exposure field.

〔Example〕

Example 1 Hereinafter, an example of a method for manufacturing a PBT using the present invention will be described.

First, a W thin film is further formed on a GaAs substrate formed on a carrier collecting electrode layer, and a so-called three-layer structure of a lower organic film / intermediate inorganic film / upper resist film is formed thereon.
A layer resist was formed. PMMA (polymethyl methacrylate) was used as the upper resist. Next, exposure was performed using a phase shift reticle having only a very small L / S in the control electrode region of the PBT as shown in FIG. 1 (a).
Adjacent light-transmitting portions in the fine L / S of the phase shift reticle are arranged so as to invert the phase of the illumination light by 180 °. Next, the light was converted into a transmission type reticle having a control electrode peripheral circuit pattern as shown in FIG. 1 (b), and exposure was performed.

Exposure to the two regions is performed by changing only the reticle while the substrate is fixed on the substrate stage of the exposure apparatus.
It is performed continuously. It goes without saying that a positioning operation is performed in each exposure. The order of exposure for the two regions is not particularly defined. The light source of the exposure apparatus used was a KrF excimer laser, and the numerical aperture of the optical system was 0.6. The time required for exposure of each of the two reticles in one exposure field was about 5 seconds. On the other hand, when the same pattern was exposed using an electron beam lithography apparatus, the time required for the exposure was about 600 seconds.

Next, the upper resist was developed to obtain an upper resist pattern as shown in FIG. 1 (c). This was sequentially transferred to the intermediate layer and the lower layer by reactive ion etching. As a result, in the lower organic film, both the L / S pattern having a rectangular sectional shape with a high aspect ratio in the ultrafine control electrode pattern region and the peripheral circuit pattern were obtained.

Using the lower organic layer pattern thus formed as a mask, dry etching of the W film is performed to form a control electrode pattern. After that, GaAs is grown thereon and the control electrode is buried, and subsequently, a carrier injection electrode, wiring, etc. are formed. PBT
Was prepared. All the exposures other than the control electrode pattern used a transmission mask. As a result of evaluating the electrical characteristics of the produced PBT, the expected performance was obtained.

FIG. 1 is a schematic plan view for explanation, and does not necessarily show an actual transistor layout. Further, the device structure, the substrate material, the control electrode material, the resist material and the process, the exposure apparatus, and the like can be used without being limited to those described in this embodiment.

The exposure process of this embodiment is not limited to PBT,
The present invention can be applied to other devices in which patterns and peripheral circuits are mixed, such as a lateral one-dimensional superlattice FET.

Embodiment 2 In the PBT, since the extremely fine pattern region and the circuit pattern region are mixed in the same layer (control electrode layer), a reticle in which a phase shift mask region and a transmission type mask region are mixed corresponding to each of the above regions is used. A pattern can be formed. FIG. 2 shows a mask for this purpose. In the first embodiment, the shape of the control electrode was a comb shape as shown in FIG. 1 (c). However, in this method, in order to completely separate the phase shift mask area and the transmission mask area, the phase shift mask area (second
(Within the dotted line in the figure).

Example 3 An example of a method for manufacturing a super-matrix solid-state oscillation device using the present invention will be described.

A positive resist PMMA was applied on a GaAs substrate, and exposure was performed using a phase shift mask having a set of dot-shaped translucent portions as shown in FIG. Thereafter, development was performed to obtain a resist opening corresponding to each of the light-transmitting portions in FIG. The translucent portions of the phase shift mask are arranged (in a checkerboard pattern) so as to alternately invert the phase of the illumination light by 180 ° in both the upper, lower, left and right directions. The phase shift mask may be provided with a finer light-transmitting portion pattern for phase inversion around each of the dot-shaped light-transmitting portions shown in FIG.

Next, metallization was performed to deposit metal on the resist and on the substrate at the resist opening, and then the resist was removed to form a metal dot matrix on the substrate by a lift-off method. Subsequently, electrodes and the like were formed to manufacture a super-matrix solid-state oscillation device.

Here, an example of manufacturing a solid-state oscillation element has been described.
By combining the resist pattern forming step of this embodiment with other various processes instead of the metallization on the GaAs substrate, application to various devices is possible. For example, after a GaAlAs thin film is grown on a GaAs substrate and a pattern is formed using a negative resist and the phase shift mask according to the present embodiment, a resist pattern corresponding to each of the dot-shaped translucent portions in FIG. 3 is obtained. Remains. Use this as a mask for Ga
By performing anisotropic etching of AlAs and performing appropriate post-processing, a quantum well matrix can be formed. Similarly, the present invention can be applied to a lateral FET superlattice, a resonant tunneling effect transistor, and the like.

Embodiment 4 Another embodiment relating to a method of manufacturing a super matrix solid-state oscillation device using the present invention will be described.

The positive resist in Example 3 was replaced with a negative resist, and the exposure process was changed as follows. First, a mask A, a mask B, and a mask C as shown in FIG.
Was prepared. The masks A and B are L / S phase shift masks, and the L / S in each is orthogonal to each other or has a different angle with respect to the reference direction. Using the three masks A, B and C, the same resist film was overexposed to obtain the same resist pattern as in Example 3. That is, the dot row example is formed at the overlapping portion of L / S in the masks A and B, and the mask C defines the range of the dot matrix area. According to the present embodiment, it is possible to make the period of the dot matrix smaller than that of the third embodiment, and to make the planar shape of the resist square.

It goes without saying that the pattern type process of this embodiment can be applied to various devices as in the third embodiment.

〔The invention's effect〕

According to the method of manufacturing a semiconductor or superconductor device according to the present invention, in the process of forming a circuit pattern including an ultrafine pattern region including a pattern having a size of about 0.1 μm or less in a quantum effect element or the like, Exposure of the area is performed by the reduced projection exposure method using the phase shift method,
By independently performing other circuit patterns by a normal exposure method, the time required for forming the pattern can be significantly reduced, and the cost of the apparatus can be reduced.

Thereby, the economical efficiency in mass production of the semiconductor / superconductor element can be improved. Further, when the above elements are integrated, these effects become more remarkable.

[Brief description of the drawings]

1 to 4 are plan views of a mask pattern according to an embodiment of the present invention.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Toshihiko Tanaka 1-280 Higashi-Koikekubo, Kokubunji-shi, Tokyo Inside the Hitachi, Ltd. Central Research Laboratory (72) Inventor Taku Oshima 1-280 Higashi-Koikekubo, Kokubunji-shi, Tokyo Hitachi, Ltd. Central Research Laboratory (56) References JP-A-58-173744 (JP, A) JP-A-62-189468 (JP, A)

Claims (25)

(57) [Claims] An exposure for forming a resist layer on a workpiece layer, wherein exposure light is used to pattern a first region of the resist layer densely and a second region is patterned more coarsely than the first region. In the method, the first area is exposed with a mask pattern having a phase shift pattern for inverting the phase of the exposure light, and the second area is exposed with a mask pattern including a light transmitting area and a non-transmitting area. An exposure method comprising: 2. The exposure method according to claim 1, wherein said second pattern is a phase shift pattern. 3. The exposure method according to claim 1, wherein said first pattern is a control electrode. 4. The exposure method according to claim 1, wherein said first pattern is a wiring. 5. The exposure method according to claim 1, wherein the first pattern and the second pattern are formed on the same mask. 6. The apparatus according to claim 1, wherein said first pattern and said second pattern are formed on different masks.
5. The exposure method according to any one of items 1 to 4. 7. A step of applying a resist film on a substrate having a film to be processed, exposing a mask pattern by exposure light to the resist film through a projection optical system, and developing the resist film to form a resist pattern. A process of processing the film to be processed from the formed resist pattern, comprising: projecting and exposing a first pattern having a pattern dense in a predetermined region of the resist film; Projecting and exposing with a second pattern having a pattern coarser than the pattern, wherein at least one of the first pattern and the second pattern is a phase shift pattern for inverting the phase of exposure light. A method for forming an element, comprising: 8. The resist film is a positive resist,
8. The method for forming an element according to claim 7, wherein the post-development resist removal regions corresponding to the adjacent light transmitting portions whose phases are inverted are connected to each other. 9. The resist film is a negative type resist,
8. The method according to claim 7, wherein the post-development resist removal regions corresponding to the adjacent light transmitting portions whose phases have been inverted after the development are connected to each other. 10. The method according to claim 7, wherein the first pattern and the second pattern are exposed at the same position on the resist film. 11. The method according to claim 7, wherein both the first pattern and the second pattern are formed on a phase shift mask. 12. The method according to claim 7, wherein said first pattern is a phase shift mask, and said second pattern is formed on a transmission type mask. 13. The method according to claim 7, wherein the first pattern and the second pattern are formed on the same mask. 14. A step of forming a thin film on a substrate, a step of forming a resist layer on the thin film, a step of projecting and exposing a phase shift pattern for inverting the phase of exposure light to the resist layer, Projecting and exposing a mask pattern formed of a non-transmissive region onto a resist, developing after exposure, processing the thin film by etching, and forming a semiconductor element in the processed region. A method of manufacturing a semiconductor device. 15. The method according to claim 14, wherein the phase shift pattern is a control electrode. 16. The method according to claim 14, wherein the phase shift pattern is a wiring. 17. The method according to claim 14, wherein the step of projecting and exposing comprises exposing the same resist layer to the phase shift pattern and a mask pattern comprising the light transmitting area and the non-transmitting area. A method for manufacturing a semiconductor device. 18. The apparatus according to claim 14, wherein said phase shift pattern and said mask pattern comprising said light transmitting area and said non-transmitting area are formed on the same mask.
13. The method for manufacturing a semiconductor device according to any one of the above. 19. The apparatus according to claim 14, wherein said phase shift pattern and said mask pattern comprising said light transmitting area and said non-transmitting area are formed on different masks.
13. The method for manufacturing a semiconductor device according to any one of the above. 20. A first pattern having a first dimension,
A method of manufacturing a semiconductor device having a second pattern having a second dimension finer than the first dimension, wherein the first pattern projects a mask pattern including a light transmitting area and a light non-transmitting area. The second pattern is formed by projecting and exposing through a projection optical system a phase shift mask pattern that inverts the phase of light passing through an adjacent light transmitting portion. A method of manufacturing a semiconductor device. 21. The method according to claim 20, wherein the first pattern and the second pattern are formed in the same layer of the semiconductor element. 22. The method according to claim 20, wherein the first pattern and the second pattern are formed using different masks. 23. The method according to claim 20, wherein the first pattern and the second pattern are formed using the same mask. 24. The method according to claim 20, wherein the first pattern and the second pattern are formed in different layers of the semiconductor element. 25. The method according to claim 21, wherein the second pattern is a control electrode.