JP2622950B2 - Image display device - Google Patents

Description

The present invention relates to an image display device based on a cycle still display method suitable for a liquid crystal television.

B) Conventional technology A conventional liquid crystal display is divided into two upper and lower parts, and pixel information is inputted and displayed for each of the separated LCDs.
No. 83892, JP-A-58-193588 and JP-A-59-28192, all of which can be used for television images and the like.
These image display devices are mainly used to reduce the burden of time-sharing in driving due to the responsiveness of the liquid crystal display. However, as the number of pixels of the liquid crystal display increases, not only the response of the liquid crystal display but also the poor response including the driving elements surface, and for example, a television transmitted at a predetermined speed and transmitted as serial data. If the video signal is sent directly to the driving element, the image is likely to be coarse and fluctuate on the screen (bits fall due to inability to follow). Therefore, the video signal received using the screen memory is temporarily stored, the writing speed and the reading speed of the memory are changed, and the screen memory for two screens is used alternately for writing and reading, The video signal is selectively selected and sent to the driving element. However, these methods are not preferable because they require a large-capacity memory and deteriorate image quality (particularly, display roughness).

C) Problems to be Solved by the Invention The present invention has been made in view of the above points, and provides an image display device of high display quality that requires only a screen memory for one screen.

D) Means for Solving the Problems The present invention is a system in which the writing of the screen memory, the reading of the upper screen, the writing, and the reading of the lower screen are one cycle, and this is repeated a plurality of cycles to display one screen. In particular, the timing for reading is set during the writing timing of the writing means, and the pixel information corresponding to the upper screen and the pixel information corresponding to the lower screen are divided into a predetermined number of pixel information units. A reading means configured to send pixel information for one screen to the liquid crystal display by alternately reading a plurality of times from the upper screen memory and the lower screen memory.

E) Function By this, display data can be transferred at half the writing speed of the screen memory, and the screen memory has a capacity of one screen, and the reading of one screen can be performed in the writing time of one screen. Can be better.

F) Embodiment FIG. 1 is a block diagram of an image display device according to an embodiment of the present invention.
FIG. 2 is a timing chart of the main part of this case. Hereinafter, a case of displaying a monochrome image with 512 × 256 dots without gradation display will be described as an example, but the present invention is not limited to this. In FIG. 1, (1) is a twisted nematic liquid crystal display in which electrodes are arranged in a matrix, and a screen (or an electrode group) is divided into upper and lower parts which can be driven independently, and each has 256 × 256 dots ( The entire screen has pixels of 512 × 256 dots). (2) is a driver for the liquid crystal display (1), which is made up of HD44100H manufactured by Hitachi, etc., receives the image signal (pixel information of the video signal) serially transferred, sets a timing, applies a bias to the liquid crystal display, and controls the liquid crystal display. Drive.

(3) is a screen memory capable of storing pixel information corresponding to a dot (pixel) of the liquid crystal display (1) for one screen, and two random access memories of 8192 bits (65536 bits) static drive, that is, for an upper screen. It comprises a memory (3a) and a lower screen memory (3b). Note that data per dot is handled as one bit (white or black information).

(4) is a write address counter, and (5a) and (5b) are read address counters, each of which specifies an address of the screen memory (3) via selectors (6a) and (6b). (7) is a triple register for inputting the address of the start address to the address counters (4), (5a) and (5b). The address assigned to the upper screen memory (3a) of the screen memory (3) is from 0000 to 1FFF (hexadecimal,
The correspondence with decimal numbers is 0-9 for 0-9, and A-15 for 10-15.
And the address assigned to the lower screen memory (3b) is 20
If the address is 00 to 3FFF, the register (7) has "0000" for the write address counter (4) and "00" for the read address counter (5a) corresponding to the upper screen memory (3a).
00 ”and“ 20 ”for (5b) corresponding to the lower screen memory (3b).
00 ”is stored.

(8) is an image processing circuit for serially outputting a black-and-white video signal including a tuner, an intermediate frequency amplification, etc., but may be constituted by a buffer for receiving a video signal from a video or the like. (11) SP converter for serial-to-parallel conversion of video signals by 8 bits, (12) and (12) PS converters for converting parallel video signals to serial, (13) and (13)
Is a latch circuit for setting the timing of the video signal.

Further, (9) is a timing control circuit for monitoring and controlling all the above circuits to operate smoothly. In particular, the image processing circuit (8) outputs a vertical retrace signal (V) and a horizontal retrace signal (H). The read / write timing signal (R / W) is output to the screen memory (3) and the address counter (4)
Data transfer lines and count-up signals (ACD0) (ACD1) (ACD2) are output to (5a) and (5b), respectively.
The selector (6a) switches the address signal so as to receive and output the R / W signal, and the selector (6b) switches the address signal to half the frequency of the R / W signal obtained by the toggle flip-flop (14). The read address counters (5a) and (5b) are selectively switched by a signal.

The operation of the above configuration will be described with reference to FIG. First, the image processing circuit (8) sends out a vertical retrace signal (V) and a horizontal retrace signal (H) from a received radio wave or a transmitted video signal, and receives a horizontal retrace signal (H) to control timing. While the display signal (D) is output from the circuit (9), the video signal is output. This video signal is a black-and-white image signal equivalent to 256 dots during one scan, but is converted into 8-bit parallel signals by the SP converter (11) and stored in the latch circuit (13) to write the R / W signal. It is output in time. The contents of the register (7) are stored in the address counter (4) based on the vertical blanking signal (V).
(5a) and (5b) are forwarded respectively.

Now, the screen memory (3) is a timing control circuit (9)
Are controlled by a two-phase clock signal φ1φ2 inside the memory, and a writing state and a reading state of stored contents are alternately switched by the clock signal φ1. The address ("0000" to "3FFF") of the screen memory (3) to be written is determined by the write address counter (4) and the address corresponding to the upper screen in the screen memory (3) to be read. ("0000" ~
"1FFF") is determined by the read address counter (5a).
The addresses ("2000" to "3FFF") corresponding to the lower screen in the screen memory (3) to be read are selectively given by the read address counter (5b). ) (5b) is advanced in synchronization with the clock signal φ2.

Taking the first frame as an example and referring to FIG. 2, the contents of the write address counter (4) are "0000" and the read address counter (5a) is set by the vertical retrace signal (V).
It starts from the time when “0000” and “2000” are stored in (5b), respectively.

At the first timing (t1), the R / W signal outputs the "L" level as a write state, and the video signal is sent from the latch (13) to the screen memory (3). Since the contents of the address counter (4) are output and the address is designated, the video signal is stored in the address "0000", that is, in the upper screen memory (3a) of the screen memory (3).

At the next timing (t2), the R / W signal outputs the "H" level as a read state, and the address at this time is "0000" based on the contents of the read address counter (5a).
In this case, the memory contents which have just been written and stored in the screen memory (3a) for the upper screen at the timing (t1) are read out and stored in the latch (13). During this timing, the fall of ACD0 causes the write address counter (4) indicating the next write destination to advance by one step to "0001".

At the next timing (t3), the writing state is resumed, and the video signal is stored in the address "0001", that is, the upper screen memory (3a) of the screen memory (3).

At the timing (t4) following the timing (t3), the R / W signal outputs the "H" level as the read state. Here, the address is designated based on the contents of the read address counter (5b), so that the address "2000", that is, the contents of the lower screen memory (3b) is output. At this point in the first frame, the writing to the screen memory (3) has been completed only up to the address "0001" as described above, so that no video signal is contained at the address "2000". After the second frame, the video signal written by the immediately preceding frame is stored, so that the content is output. In this state, the video signal read from the lower screen memory (3b) and the video signal read from the upper screen memory (3a) at timing (t2) and stored in the latch circuit (13) for timing. The video signals are sent to the PS converters (12) and (12), respectively, and are input to the driver (2) as an upper image signal and a lower image signal, and are displayed.

After the timing (t5), the above timings (t1) to (t)
In the same manner as in 4), writing and reading are performed alternately, but writing is performed starting from address “0000” and stepping by one address, and reading is performed for the upper screen starting from address “0000”. Data and lower screen data starting from address "2000" are alternately read.

That is, writing to the screen memory (3) is performed as described above.
The writing is performed at the address designated by the write address counter (4). As shown in FIG. 2, the contents of the write address counter (4) are sequentially incremented by one from address "0000". Until the contents of the address counter (4) are advanced to the address "1FFF" assigned to the upper screen memory (3a), the video signals are sequentially stored in the upper screen memory (3a) of the screen memory (3). Will be remembered. When the content of the write address counter (4) is incremented by one from address "1FFF" to address "2000", the address thereafter becomes the address assigned to the lower screen memory (3b), and the write address becomes The contents of the counter (4) are stored in the lower screen memory (3
The video signal is sequentially stored in the lower screen memory (3b) of the screen memory (3) until the address advances to the address "3FFF" assigned to b). When writing for one screen is completed, the contents of the write address counter (4) become "0000" by the next vertical retrace signal (V) as described above, and the next frame starts.

Reading from the screen memory (3) is performed at the timings (t2), (t4),... Set between the writing timings (t1), (t3), (t5),. , Based on the address specified by the read address counters (5a) and (5b). Then, as shown in FIG. 2, the read address counter (5a) for the upper screen memory (3a) starting from “0000” is incremented by one at timings (t5), (t9). The read address counter (5b) for the lower screen memory (3b) starting from "2000" is incremented by one to "3FFF" at timings (t7), (t11). In addition, since the read address counters (5a) and (5b) are incremented alternately, the increment speed of the read address counters (5a) and (5b) is half that of the write address counter (4). For example, "000
When the contents of the write address counter (4) starting from “0” are “2000”, the contents of the read address counter (5a) starting from “0000” are half of “1000” and the read address starting from “2000”. Counter (5b)
Is "3000".

Therefore, the video signal (address is 1FFF) of the upper screen of the first screen is read at the timing immediately before the writing of the first screen is completed (the last address is 3FFF), and the video signal (address of the lower screen) is read immediately after the writing. Will read 3FFF). That is, the writing time and reading time for one screen are equal, and in reading, the video signal of the screen currently being written is read for the upper screen, and the video signal of the previous screen is read for the lower screen. become.

The input of the image signal to the driver (2) is performed at a speed which is half the writing speed to the screen memory (3) (although the timing is adjusted vertically by the latch 13 in the above example, the timing may be different). (That is, the serial clock frequency of the SP converter (11) = the serial clock frequency of the PS converter (12) × 2), and the continuity of the video signal is maintained in each of the upper and lower screens (the video signal is a serial data Therefore, the second half of the (n-1) th screen and the first half of the nth screen are continuous.)
Therefore, in the display of the n-th screen, the n-th screen data is displayed on the upper screen, such as the n-th screen data in the upper i-th row and the (n-1) th screen data in the lower i-th row at the i-th row timing. Although the (n-1) th screen data is displayed on the lower screen, the display of the immediately preceding lower screen data and the next upper screen data is data within a very short and continuous time, and practically, When the last line of the upper screen is displayed, the last line of the lower screen is displayed, and at the next line timing, the first line of the lower screen is displayed with the n-th screen data. It does not give a feeling of strangeness.

In the above description, a case where one pixel is treated as one bit (white or black information) and writing and reading are performed in units of 8 bits is shown. Is shown. If the image processing circuit (8) includes an AD converter, 2 pixels per pixel
Bit (four gradations), four bits (eight gradations), eight bits (16
Gray scale) can be displayed in exactly the same procedure as video information such as gray scale. In this case, writing and reading are performed in a predetermined number of pixel information units such as four pixels, two pixels, and one pixel. Further, color display can be performed by using color signals instead of gradations, or by having screen memories for three screens corresponding to the color signals and performing the same procedure for each color.

G) Advantages of the Invention As described above, the present invention provides writing, upper screen reading, and writing of a dot matrix display that is divided into upper and lower parts from the standpoint of a display signal as the use timing of the screen memory for one screen. Since the lower screen reading is repeated as one cycle and driven by the read signal, the capacity of the screen memory can be relatively small, and in each of the upper and lower screens, the writing speed to the screen memory can be reduced. Since the pixel information read from the screen memory can be transferred at half the speed, the display time is doubled, the screen does not flicker, and one screen can be read with one screen writing time, and the video signal can be read. Therefore, a display device with good image quality can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram of an image display device according to an embodiment of the present invention, FIG. 2 is a timing chart of main parts thereof, and FIG. 3 is an explanatory diagram showing write / read timing of a memory. (1) Liquid crystal display (2) Driver (3)
... screen memory, (4) ... (write) address counter,
(5a) (5b) ... (read) address counter, (6a)
(6b) ... selector, (7) ... register, (8) ...
Image processing circuit, (9)... Timing control circuit.

Claims (1)

(57) [Claims] 1. A liquid crystal display comprising a dot matrix divided into upper and lower parts, and a screen having an upper screen memory and a lower screen memory for storing pixel information corresponding to dots of the liquid crystal display for one screen. A memory, and writing means for sequentially storing video signals sequentially sent for one screen in the screen memory consisting of an upper screen memory and a lower screen memory in a predetermined number of pixel information units in pixel order; Reading means for sequentially reading screen information used for displaying both lower screens from a screen memory in units of a predetermined number of pixel information; and a writing timing of the writing means and a reading timing of the reading means. The timing is set alternately, and the reading means alternately stores pixel information corresponding to the upper screen and pixel information corresponding to the lower screen in a predetermined number of pixel information units for the upper screen memory and the lower screen memory. From memory The image display apparatus characterized by the pixel information for one screen by issuing several Kaidoku was configured to send the liquid crystal display device.