JP2693513B2 - Active matrix type liquid crystal display device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Object of the Invention (Industrial field of application) The present invention relates to a thin film transistor.
er, TFT) as a switching element to constitute a display pixel electrode array.

(Related Art) In recent years, as a display element using liquid crystal, a large-capacity, high-density active matrix display element for television display, graphic display, and the like has been actively developed and put into practical use. In such a display element, a semiconductor switch is used as a means for driving and controlling each pixel so that high-contrast display without crosstalk can be performed. As the semiconductor switch, a TFT or the like formed on a transparent insulating substrate is usually used because it can be used for a transmissive display and can be easily enlarged.

FIG. 2 is a simple circuit diagram showing one pixel of a liquid crystal display element using a display pixel electrode array equipped with a TFT. In the figure, at the intersections of the intersecting scanning line 1 and signal line 2,
A TFT3 is provided, the gate of the TFT3 is connected to the scanning line 1 for each row, and the drain of the TFT3 is connected to the signal line 2 for each column. The source of the TFT 3 is connected to the display pixel electrode 4, and the liquid crystal layer 6 is sandwiched between the display pixel electrode 4 and the counter electrode 5.

Next, a method of driving this liquid crystal display element will be described. That is, the potential of the display pixel electrode 4 is set to the same potential as the video signal potential during the period (switching period) in which the scanning line selection voltage (Vg, on) is applied to the gate of the TFT3.
While the scanning line non-selection voltage (Vg, off) is applied to the gate of the display pixel electrode 4, the display pixel electrode 4 holds this potential. As a result, a potential difference according to the video signal voltage is applied to the liquid crystal layer 6 sandwiched between the display pixel electrode 4 and the counter electrode 5 set to a predetermined potential. Then, the arrangement state of the liquid crystal layer 6 changes in accordance with this potential difference, so that the light transmittance of this portion also changes and an image is displayed. When the liquid crystal layer 6 is driven by direct current, it is deteriorated by electrolysis of liquid crystal molecules and its life is shortened. Therefore, alternating current driving is performed. In general, AC driving is performed by setting the potential of the counter electrode 5 to a DC potential and setting the video signal voltage with respect to the potential of the counter electrode 5 in positive and negative symmetry in even and odd frames. That is, the video signal voltage is a sum of a certain DC voltage (Vsc) and a positive / negative symmetrical AC voltage (Vsa) corresponding to the video signal.

By the way, as shown in FIG. 2, a parasitic capacitance (Cgs) exists between the gate and source of the TFT3. Because of this Cgs
When the scanning signal voltage is switched from Vg, on to Vg, off, the capacitance division shifts the display pixel electrode 4 by ΔVp to the negative side. This shift amount has a relationship of ΔVp to ΔVg * Cgs / (Cgs + Clc). Here, ΔVg = Vg, on−Vg, off, and Clc represents the capacitance of the liquid crystal layer 6. Therefore, the voltage applied to the liquid crystal layer 6 is made equal in the even and odd frames by shifting the potential of the counter electrode 5 to the negative side by the amount of ΔVp.

(Problem to be Solved by the Invention) However, since Clc exhibits a capacitance change with respect to the applied voltage, the value of ΔVp differs for each video signal. That is, the optimum counter electrode potential differs for each video signal. In general, since the counter electrode potential is set to the same potential for all pixels at the same time, it is not possible to set the optimum counter electrode potential for all pixels at the same time in a display screen to which various video signal voltages are applied. . As a result, flicker, which is flicker on the display screen, occurs.

FIG. 3 is a simple circuit diagram showing one pixel of a liquid crystal display element which is described in, for example, Japanese Patent Laid-Open No. 56-162793 and which can solve the above-mentioned problems. In the figure,
The parts corresponding to those in FIG. 3 are denoted by the same reference numerals, and by inserting a new storage capacitor (Cs) that does not change in capacitance with respect to the applied voltage in parallel with Clc, the video signal voltage dependence of ΔVp can be obtained. Can be reduced. As a result, flicker can be reduced as compared with the case of the example shown in FIG.

FIG. 4 is a plan view for explaining the planar structure of one pixel on the display pixel electrode array substrate in the liquid crystal display element shown in FIG. As shown in the figure, the TFT10
The gate electrode 12 integrated with the scanning line 11, the drain electrode 14 integrated with the signal line 13, and the source electrode 1 connected to the display pixel electrode 15
6 and the semiconductor layer 17. Also, scan line 1
In a direction substantially parallel to 1, a storage capacitor forming wiring 18 is formed so as to partially face the display pixel electrode 15 with an insulating film (not shown) interposed therebetween. Additional storage capacitance (Cs) at the portion where it overlaps with the forming wiring 18
Is obtained.

In FIG. 4, the auxiliary capacitance forming wiring 18 is formed of a transparent conductive film or a light-shielding metal film. When the auxiliary capacitance forming wiring 18 is formed of a transparent conductive film, the number of film forming steps and photolithography steps increases, and there are many defects in the manufacturing process. On the other hand, when the auxiliary capacitance forming wiring 18 is formed of a light-shielding metal film, the opening area, which is the area of the portion through which light is transmitted, is reduced, which directly leads to a reduction in the light transmittance of the liquid crystal display element.

The present invention has been made in view of such circumstances.

[Structure of the Invention] (Means for Solving the Problems) The present invention has a structure in which one pixel composed of a TFT and a pixel electrode connected to the TFT is arranged in a matrix on one main surface of an insulating substrate, and An array substrate provided with a capacitance-forming electrode made of a light-shielding material that faces the pixel electrode via an insulating film; and a counter substrate having a common electrode and a light-shielding layer formed on one main surface of the insulating substrate, The present invention relates to an active matrix liquid crystal display element including a liquid crystal sandwiched in a gap obtained by combining an array substrate and a counter substrate so that their main surfaces are opposed to each other. Then, in a projection view of one pixel on one main surface of the counter substrate, the array configuration is such that the contour line of the opening defined by the pattern of the light shielding layer fits within the pattern of the capacitance forming electrode.

(Function) In the active matrix type liquid crystal display element using TFT, when the capacitance forming electrode is not formed, or
In the case of the example shown in the figure, even if the bonding of the array substrate and the counter substrate is deviated within the accuracy range, the light shielding layer pattern on the counter substrate has the display pixel electrode in order to prevent the contrast ratio from being lowered. It is formed so as to cover a portion other than the pattern, that is, a portion through which light not modulated by the liquid crystal layer passes. Specifically, the light shielding layer pattern on the counter substrate is formed so as to overlap the peripheral portion of the display pixel electrode pattern by the bonding accuracy. Therefore, there is an invalid area that does not contribute to the display in the outer peripheral portion of the display pixel electrode pattern. In the present invention, this invalid area is used for forming an additional storage capacity (Cs).

Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a diagram showing an embodiment of the present invention. FIG. 1A is a plan view of one pixel portion on an array substrate, FIG. 1B is a schematic sectional view of one pixel portion, and FIG. c) is a schematic projection view of one pixel portion. In FIG. 1A, the thin film transistor (TFT) 20 is connected to the gate electrode 22 integrated with the scanning line 21, the drain electrode 24 integrated with the signal line 23, and the display pixel electrode 25, as in the case of FIG. And the semiconductor layer 27. Also, TF
A capacitor forming electrode 28 is formed near T20 so as to extend linearly in a direction substantially parallel to the scanning line 21 and surround the periphery of the display pixel electrode 25 via an insulating film (not shown). An additional storage capacitance (Cs) can be obtained at the overlapping portion of the display pixel electrode 25 and the capacitance forming electrode 28.

FIG. 1B corresponds to a cross section taken along the line AA ′ in FIG. In FIG. 1 (b), on one main surface of the insulating substrate 30 made of glass, for example,
For example, a gate electrode 22 and a capacitance forming electrode 28 are simultaneously formed by coating a Cr (chromium) film, which is a light-shielding material, by a sputtering method, and then photoetching it into a predetermined shape. Silicon oxide (SiO
The gate insulating film 31 made of x) is formed by the plasma CVD method. Here, although not shown, the gate electrode
When the electrodes 22 and the capacitance forming electrodes 28 are formed, the scanning lines 21 are also formed in the same step. Further, the gate insulating film 31 is an insulating film interposed between the capacitance forming electrode 28 and the display pixel electrode 25 in FIG. The semiconductor layer 27 made of, for example, i-type hydrogenated amorphous silicon (a-Si: H) is formed on the portion of the gate insulating film 31 facing the gate electrode 22.
Of the n-type a-Si: H electrically isolated from each other on the semiconductor layer 27.
A drain region 32 and a source region 33 consisting of are also provided by using the plasma CVD method. Then, for example, an ITO (indium tin oxide) film is coated on the gate insulating film 31 adjacent to the source region 33 side of the semiconductor layer 27 by a sputtering method, and then photoetched into a predetermined shape to display pixels. An electrode 25 is provided. Further, one end of the source electrode 26 is connected to the source region 33,
The other end of the source electrode 26 extends on and is connected to the display pixel electrode 25. Further, in the drain region 32, the drain electrode 24
Are connected at one end. Here, the drain electrode 24 and the source electrode 26 are formed in the same process in which, for example, a Mo (molybdenum) film and an Al (aluminum) film are sequentially coated by a sputtering method and then photoetched into a predetermined shape. Although not shown, the signal line 23 in FIG. 1A is also formed in the same process as the drain electrode 24 and the source electrode 26. Thus, the desired array substrate 34 is obtained. On the other hand, on the one main surface of the insulating substrate 35 made of, for example, glass, the common electrode 36 made of, for example, ITO and, for example, Al
The counter substrate 38 is formed by sequentially forming the light shielding layer 37 as a black matrix made of (aluminum). Then, on one main surface of the array substrate 34,
Further, an alignment film 39 made of, for example, low temperature cure type polyimide (PI) is formed on the entire surface, and an alignment film 40 made of, for example, low temperature cure type polyimide is also formed on the entire main surface of the counter substrate 38. Are formed. Then, on the main surfaces of the array substrate 34 and the counter substrate 38, the respective alignment films 39, 4 are formed.
By rubbing 0 in a predetermined direction with a cloth or the like, the alignment treatment by rubbing is performed. Further, the array substrate 34 and the counter substrate 38 are combined such that their main surfaces are opposed to each other and their alignment axes are substantially 90 °, and a liquid crystal 41 is sandwiched in the gap thus obtained. Polarizing plates 42 and 43 are attached to the other main surface side of the array substrate 34 and the counter substrate 38, respectively, and illumination is performed from the other main surface side of either the array substrate 34 or the counter substrate 38. It has a shape.

FIG. 1 (c) is a schematic projection view of the portion corresponding to FIG. 1 (a) on one main surface of the counter substrate 38.
In FIG. 1 (c), the light shielding layer 37 has a predetermined opening corresponding to the display pixel electrode 25 in FIG. 1 (a), and completely covers the portion excluding the display pixel electrode 25. Further, the contour line 44 of the opening defined by the pattern of the light shielding layer 37 is adapted to fit within the pattern of the capacitance forming electrode 28. Further, in FIG. 1C, the width L1 indicates the distance between the outer circumference of the capacitance forming electrode 28 and the contour line 44, while the width L2 indicates the inner circumference of the capacitance forming electrode 28 and the contour line 44. And shows the interval. The widths L1 and L2 are both the array substrate 3
It is desirable to set the size to be equal to or higher than the bonding accuracy between the 4 and the counter substrate 38. The reason for this is that if the width is L1, the array substrate
This is to prevent a decrease in the contrast ratio due to the misalignment between the 34 and the counter substrate 38, and to eliminate or reduce the variation of the opening area due to the misalignment between the array substrate 34 and the counter substrate 38 in the case of the width L2.

In this embodiment, the shapes of the capacitance forming electrode 28 and the light shielding layer 37 are devised so that the contour line 44 of the opening defined by the pattern of the light shielding layer 37 fits within the pattern of the capacitance forming electrode 28. This makes it possible to form an ineffective region (Cs) that does not contribute to the display of the pattern of the display pixel electrode 25. As a result, the opening area can be increased even when a metal film is selected as the material of the capacitance forming electrode 28 instead of the transparent conductive film in which the photolithography process is increased. Therefore, in this embodiment, an image with a brighter display and less flicker can be obtained as compared with the prior art.

In this embodiment, the capacitance forming electrode 28 is connected to the scanning line 21.
Although it is formed at the same time as the gate electrode 22 and the gate electrode 22, it goes without saying that it may be formed at the same time as the signal line 23 and the like as long as it is opposed to the display pixel electrode 25 via the insulating film.

EFFECTS OF THE INVENTION According to the present invention, an additional storage capacitor (Cs) is formed by a metal film by defining an opening region with a pattern of a capacitance forming electrode made of a light-shielding material formed on an array substrate. Even at this time, it is possible to minimize the decrease in light transmittance and obtain an image with a bright display and less flicker.

[Brief description of the drawings]

FIG. 1 is a diagram showing an embodiment of the present invention, FIGS. 2 and 3 are schematic circuit diagrams showing an example of a pixel of a conventional active matrix type liquid crystal display element, and FIG. 4 is a conventional active matrix type. It is a figure for demonstrating the planar structure of one pixel in the array substrate of a liquid crystal display element. 20 …… Thin film transistor 25 …… Display pixel electrode 28 …… Capacitance forming electrode 30, 35 …… Insulation substrate 34 …… Array substrate 36 …… Common electrode 37 …… Shading layer 38 …… Counter substrate 41 …… Liquid crystal 44… …Outline

Claims (1)

(57) [Claims] 1. A pixel comprising a thin film transistor and a display pixel electrode connected to the thin film transistor is arranged in a matrix on one main surface of an insulating substrate, and each pixel is opposed to the display pixel electrode via an insulating film. Opposed to an array substrate provided with a capacitance forming electrode made of a light-shielding material, and a light-shielding layer having a common electrode and a predetermined opening corresponding to the display pixel electrode on one main surface of the insulating substrate. In an active matrix type liquid crystal display element comprising a substrate, a liquid crystal sandwiched in a gap obtained by combining the array substrate and the counter substrate so that the one main surface sides thereof face each other, In the projection view of the counter substrate onto the one main surface, the outline of the opening defined by the pattern of the light shielding layer is included in the pattern of the capacitance forming electrode. Active matrix type liquid crystal display device.