JP2679285B2 - Off-delay timer - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an off-delay timer (hereinafter simply referred to as a timer) that delays the operation of an output contact in, for example, sequence control. The present invention relates to a timer adapted to supply power to a circuit.

[Prior Art] An example of a conventional timer is shown in FIG. Here, the timer detects the voltage of the relay circuit 1 which opens and closes the output contact, the time circuit 2 which operates the relay circuit 1 after a predetermined time after the power supply is cut off, and the voltage of the power supply, and when this voltage exceeds a predetermined value, the time circuit 2 It consists of the power supply voltage detection circuit 3 that prohibits starting,
The relay circuit 1 mainly includes a set coil 6a, a reset coil 6b, and a latching relay 6 having an output contact (not shown), and the set coil 6a is connected to a DC power supply device 4 via a current suppressing resistor 7 and a switch 5. Reset coil
The reset capacitor 8 for exciting 6b is connected in series with the diode 9 and in parallel with the set coil 6a.
In addition, a series circuit of a reset coil 6b and a transistor 10 is connected in parallel with the capacitor 8. The time limit circuit 2 includes an oscillation circuit 13, a counting circuit 14 and an output circuit 15, and is driven by a driving capacitor 11 connected to the DC power supply device 4 via a diode 12, a resistor 7 and a switch 5. The oscillator circuit 13 is a part of a known IC circuit (for example, Japanese Utility Model Publication No. 60-2676), and includes an upper limit voltage detection comparator 20, a lower limit voltage detection comparator 21, and a set reset flip-flop (hereinafter, this flip-flop Simply referred to as FF) 22, transistor 23, voltage dividing resistors 24 and 25 for applying reference voltage V _L to the + input terminal of comparator 21, series discharge resistor 26 of transistor 23,
Capacitor 27 for determining the oscillation cycle of this oscillator circuit 13
And a variable resistor 28 in series, a variable resistor 29 for applying a reference voltage V _H to the negative input terminal of the comparator 20, and the like. The output of the oscillation circuit 13 is the counting circuit 14 and the output circuit 15.
Is connected to the base of the transistor 10 of the relay circuit 1 via. The power supply voltage detection circuit 3 is connected to the DC power supply device 4 via the switch 5, and its output end is connected to the counting circuit 14.

When the switch 5 is turned on, the latching relay 6 is set and the output contact (not shown) is closed. When the drive capacitor 11 is charged and the voltage across it reaches a predetermined value, the capacitor is set according to the time constants of the variable resistor 28 and the capacitor 27.
When the voltage of 27 rises and the voltage of the + input terminal of the comparator 20 rises to reach the upper limit reference voltage V _H determined by the variable resistor 29, a high level signal is sent from the comparator 20 and the FF 22 is set. Then, the Q output of FF22 becomes high level, the transistor 23 is turned on, and the capacitor 27 is discharged through the resistor 26. Therefore, the voltage of the capacitor 27 rapidly drops, the negative input voltage of the comparator 21 drops, and when the lower limit reference voltage V _L of the comparator 21 is reached, a high level signal is sent from the comparator 21 and the FF 22 is reset. , Its Q output shifts to the low level, so that the transistor 23 is turned off. Therefore, from this time, the capacitor 27 is charged via the variable resistor 28, and the above operation is repeated. In this way, the oscillator circuit 1 oscillates at a constant cycle. Switch 5 here
When is turned off, the power supply voltage detection circuit 3 cancels the counting operation of the counting circuit 14, so that the output of the FF 22 is counted by the counting circuit 14, and when this count value reaches a predetermined value, the output voltage of the transistor 10 of the transistor 10 is output. Signal is given to the base and transistor
When 10 is turned on, the reset coil 6b is energized to reset the latching relay 6 and open the output contact to end the function of the timer.

[Problems to be solved by the invention]

In the conventional timer as described above, since the current consumption of the two comparators 20 and 21 is large, the current consumption of the time circuit 2 becomes large, and the electrostatic capacitance of the driving capacitor 11 must be increased, and the timer is downsized. It was an obstacle to doing.

An object of the present invention is to provide a timer capable of operating for a long time with a small-capacity drive capacitor by reducing the current consumption of the time circuit.

[Means for solving the problem]

In order to solve the above-mentioned problems, the present invention provides a set coil connected to a DC power supply device, a reset coil connected in series with a first switching element, and excited by a reset capacitor charged with the voltage of the DC power supply device. A relay circuit including a two-winding latching relay, which is driven by a driving capacitor charged with the voltage of the DC power supply device, outputs a signal after a predetermined time has passed since the DC power supply device was shut off, and turns on the first switching element. In an off-delay timer including a power supply voltage detection circuit that detects a voltage of a time limit circuit and the DC power supply device and prohibits the start of the time limit circuit when this voltage exceeds a predetermined value, the time limit circuit has both ends of the drive capacitor. A series circuit of the connected variable resistor and oscillation capacitor, the anode is connected to the connection point of the variable resistor and oscillation capacitor. A PUT whose gate is connected to the divided voltage of the drive capacitor, a second switching element connected in parallel with the oscillation capacitor, and a first signal which emits a signal when the PUT is turned on and turns on the second switching element. And an counting circuit for counting the number of oscillations of the oscillating circuit, and a second signal for turning on the first switching element when a count value counted by the counting circuit reaches a predetermined value. It is composed of output means.

[Action]

In the off-delay timer according to the present invention, the oscillation circuit is configured by a series circuit of a variable resistor and an oscillation capacitor, PUT, a second switching element, etc. to reduce the current consumption of the time circuit, and a power cutoff signal generated by the power voltage detection circuit Then, the counting circuit is started, and when the count value of the counting circuit reaches a predetermined value, the reset circuit is energized via the second output means to reset the latching relay.

〔Example〕

The structure of the timer according to the present invention is shown in FIG. 1, and the same parts as those in FIG. 3 are designated by the same reference numerals as those in FIG. In FIG. 1, the timer comprises a relay circuit 1, a time limit circuit 2 and a power supply voltage detection circuit 3 as in the conventional one, but only the time limit circuit 2 is different from the conventional one, and only this part will be described in detail. The time limit circuit 2 includes an oscillation circuit 30 and a one-chip microcomputer (hereinafter simply referred to as a microcomputer) 50. The oscillation circuit 30 includes a variable resistor 31 and an oscillation capacitor 32 in a series circuit, and a variable resistor 33 and a fixed resistor 34 in a series circuit. A series circuit of the resistor 35 and the collector / emitter of the transistor 36 is connected in parallel and connected to both ends of the driving capacitor 11. PUT37 has its anode connected to the connection point of resistor 31 and capacitor 32, and its gate connected to resistor 33 and resistor 34.
Is connected to the negative terminal of the capacitor 11 via a series circuit of two resistors 38 and 39, and the connection point of both resistors 38 and 39 is connected to the base of the transistor 36. The resistor 41 and the collector / emitter of the transistor 42 are connected in series and are connected to both ends of the capacitor 32. Further, the connection point between the resistor 35 and the collector of the transistor 36 is connected to the microcomputer 50 via the inverting circuit 43. The microcomputer 50 mainly has a control calculation unit 60, and has only a function of counting the number of oscillations of the oscillation circuit 30 and holding the same, and having a standby function of stopping the operation at all times to obtain a low current consumption value. That is, the output terminal of the inverting circuit 13 is connected to the standby canceling means 51. The control calculation section 60 comprises a counting means 52 to which the output terminal of the standby canceling means 51 is connected, and a comparing means 54 for comparing the count value of this counting means 52 with the count value of the set value storage means 53. The end is connected to the base of the transistor 10 via the output means 55. Further, the control calculation unit 60 is connected so as to perform a counting operation by the power supply cutoff signal of the power supply voltage detection circuit 3, and further output means
It is connected to the base of the transistor 42 via 56.
In addition, it is also connected to the base of the transistor 42 via the standby release means 51.

Next, the operation of the timer will be described with reference to the flowcharts of FIGS. The P number in the flowchart indicates each step number. First, in FIG. 1, when the switch 5 is turned on, the set coil 6a is energized, and the set coil 6a operates to close the main contact (not shown). Further, the charging voltage of the drive capacitor 11 rises, and the time limit circuit 2 becomes operable, but the voltage of the power supply voltage detection circuit 3 exceeds a predetermined value, so counting by the control calculation unit 60 is prohibited. However, the output means 56 is turned on (P1) and the transistor
Since 42 is turned on, the capacitor 32 is discharged through the resistor 41. Therefore, since the PUT 37 does not turn on and the transistor 36 does not turn on, the input signal of the inverting circuit 43 becomes high level and the output signal becomes low level, and the standby canceling means 51 does not operate. Therefore, the microcomputer 50 is in the standby state, and the control calculation unit 60 stops its operation to reduce the current consumption of the microcomputer 50. In this state, it is checked whether or not the power supply device 4 is cut off by the power supply cutoff signal which is the output signal of the power supply voltage detection circuit 3 (P2). If the power supply device 4 is not cut off, the check is continued, and if the power supply device 4 is cut off, the output means 56 is turned off (P3). As a result, the transistor 42 is turned off, so that the oscillation capacitor 32 has a variable resistor 31.
And is charged and rises at a rate determined by the time constant of the oscillation capacitor 32. When this voltage rises, the PUT 37 turns on, the transistor 36 turns on, the input of the inverting circuit 43 turns to low level, its output turns to high level, and it is sent to the standby release means 51 to release the standby (P4) microcomputer. The control calculation unit 60 of 50 restarts the operation. Then, the output means 56 is turned on (P5) and the capacitor 32 is PUT37.
At the same time, it is discharged by the transistor 42. Where the resistance
41 is for protecting the transistor 42 from the flow of excessive current, and its resistance is small, so it is a capacitor.
32 discharges rapidly. In this way, the count value of the counting means 52 is incremented by 1 (P6). Then, the comparing means 54 determines whether or not the result of incrementing the count value has reached the set value of the set value storage means 53 (P7). If the set value has not been reached, it is determined whether or not a predetermined time has elapsed since the standby state was released (P8). When a predetermined time has passed, the process returns to step (P3), the output means 56 is turned off, the transistor 42 is turned off, and the capacitor 32 resumes charging. When the count value reaches the set value in step (P7), the output means 55 is turned on (P9)
A tie-up signal is issued to turn on the transistor 10, reset the latching relay 6 and open the main contact.

Next, the current consumption of the time limit circuit 2 will be described. The current flowing through both variable resistors 31 and 33 can be set to several μA, which is almost the same as the current flowing through both variable resistors 28 and 29 in FIG. The current flowing through the microcomputer 50 is the microcomputer
A relatively large current flows when 50 is in the operating state, but becomes several μA in the standby state. Therefore, by lengthening the oscillation cycle of the PUT 37 by selecting the constants of both variable resistors 31 and 33, the average value of the current consumption of the microcomputer 50 can be made approximately the same as the current consumption during standby.

〔The invention's effect〕

According to the present invention, a variable resistor, an oscillation capacitor and a PU
Since the number of oscillations of the oscillator circuit including T is counted, the current consumption of the time circuit is reduced, and the capacity of the drive capacitor that supplies power to the time circuit can be reduced. Also, because the oscillation capacitor connected to the anode of the PUT is discharged not only by the PUT but also by the transistor, even if the resistance value of the variable resistor connected to the anode of the PUT becomes small and the ON current of the PUT increases, By bypassing this current with a transistor, the PUT can be reliably turned off, and oscillation can be stabilized.

[Brief description of the drawings]

1 and 2 show an embodiment of an off-delay timer according to the present invention. FIG. 1 is a block diagram in which a main part is a wiring diagram, and FIG. 2 is a flow chart showing the operation of the microcomputer in FIG. FIG. 3 is a block diagram showing an example of a conventional off-delay timer, the main part of which is a wiring diagram. 1: Relay circuit, 2: Timed circuit, 3: Power supply voltage detection circuit, 4: DC power supply device, 6: Latching relay, 6a: Set coil, 6
b: reset coil, 8: reset capacitor, 10: transistor, 11: drive capacitor, 30: oscillator circuit, 31: variable resistor, 32: oscillator capacitor, 37: PUT, 42: transistor, 5
2: Counting circuit, 55, 56: Output means.

Claims (1)

(57) [Claims] 1. A two-winding latching relay in which a set coil is connected to a DC power supply device, a reset coil is connected in series with a first switching element, and which is excited by a reset capacitor charged with the voltage of the DC power supply device. A relay circuit provided with the relay circuit, a time circuit which is driven by a driving capacitor charged with the voltage of the direct current power supply device, outputs a signal after a predetermined time period after the direct current power supply device is cut off, and turns on the first switching element, and the direct current power supply. In an off-delay timer including a power supply voltage detection circuit that detects a voltage of a device and prohibits starting of the time limit circuit when this voltage exceeds a predetermined value, the time limit circuit includes a variable resistor connected to both ends of the drive capacitor. A series circuit of oscillation capacitors, the anode is connected to the connection point between the variable resistor and the oscillation capacitor, and the gate is driven. PU divided voltage of capacitor is applied
T, an oscillating circuit comprising a second switching element connected in parallel with the oscillating capacitor, a first output means for emitting a signal when the PUT is turned on, and turning on the second switching element, oscillation of this oscillating circuit An off-delay timer comprising a counting means for counting the number of times and a second output means for emitting a signal when the count value counted by the counting means reaches a predetermined value to turn on the first switching element.