JP2667416B2 - Pattern defect inspection method - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pattern defect inspection apparatus, and more particularly to an apparatus for inspecting a pattern defect in which a plurality of identical patterns repeatedly appear at a constant pitch. (Prior Art) For example, the present applicant has made various proposals regarding a defect inspection technique for a pattern of a photomask used in the manufacture of a semiconductor integrated circuit, but the basic technique is to form a pattern on such a photomask. Paying attention that the same pattern appears many times repeatedly, comparing the image signals obtained by optically scanning the same part of two patterns at the same time,
If they do not match, it is determined that there is a defect. In the above-described conventional defect inspection method, a light beam emitted from a light source is divided, projected as a spot on a test object by two objective lenses, and reflected light from the test object is guided to a light receiving element. Image signals are output simultaneously. In this case, in order to improve the inspection accuracy, it is desirable that the two patterns are as close as possible. Therefore, for example, the same pattern on two chips separated by several chips is compared with each other. This is impossible because the lens barrels of the objective lens mechanically interfere with each other. On the other hand, in a semiconductor integrated circuit, in a large-scale memory,
Many cells with the same pattern are arranged in a matrix in one chip, and each cell has a fine structure. If this is attempted, it is very difficult to match the cell pattern, and if the detection is performed with an increased detection sensitivity, a part that is not originally a defect is also detected as a defect, and there is a disadvantage that the accuracy is significantly reduced. That is, it is very difficult to determine whether the pattern is a pattern or a defect. The present inventor has developed a defect inspection apparatus capable of eliminating such defects and detecting pattern defects with high sensitivity and accuracy even when fine patterns are adjacent to each other. That is, in order to inspect a pattern defect of a test object having a large number of the same pattern at a constant repetition pitch,
An image signal obtained by optically scanning the test object is compared with a signal delayed by a time required to scan this image signal by a distance equal to the pitch of the pattern. We have proposed a defect inspection device that determines that there is a defect when there is a significant difference. FIG. 1 is a diagram showing a basic configuration of a defect inspection apparatus developed by the inventor of the present application in a process leading to the present invention. Light emitted from the light source 1 is made incident on the objective lens 4 via the half mirror 2 and the total reflection mirror 3, and is projected as a beam spot on a test object 6 mounted on an XY table 5. The light reflected by the object 6 to be inspected is made incident on the light receiving element 7 by the objective lens 4 via the mirrors 3 and 2, and an image signal is output from the light receiving element. After the image signal is delayed via the delay circuit 8, it is supplied to one input terminal of the comparison circuit 9. An image signal without delay is supplied to the other input terminal of the comparison circuit 9. For example, in a semiconductor integrated circuit memory, many cells 11 having the same pattern as shown in FIG. 2 are arranged in a matrix. Now, assuming that the main scanning is performed while the stage 5 is moved in the X direction with respect to the optical axis of the objective lens 4 and the sub scanning is performed by moving the stage 5 in the Y direction, the image signal obtained from the light receiving element 7 is the third signal. As shown in FIG. A, a fixed time T _P required for main scanning in the X direction by a distance corresponding to the cell pitch P appears repeatedly as a cycle. The signal obtained by delaying the image signal by a time tau = T _P is as shown in Figure 2 B. Now, assuming that a defect D exists in a certain cell, when the delayed signal and the non-delayed signal are compared in the comparing circuit 9, no defective signal appears in the same pattern portion, but in the pattern mismatch portion, The defect D is detected as shown in FIG. 2C. In this case, when the cell having the defect D is compared with the cell adjacent to the right side and the cell adjacent to the left side, the defect signals D appear with opposite polarities. Therefore, it is possible to determine which cell has a defect from these defect signals. Although the cell region where the cell is formed and the cell in the peripheral circuit region are not compared twice as described above, since they are compared once, the presence or absence of a defect can be inspected. FIG. 4 is a diagram showing a configuration of a defect inspection apparatus proposed by the present inventors based on the above-described principle. For example, in manufacturing a large-scale memory composed of semiconductor integrated circuits, a large number of cells are arranged in a matrix on one wafer, and a large number of cells having the same pattern as described above are arranged in a matrix on each chip. However, inspection of defects in circuit portions other than cells cannot be performed by the delay means as described above. Therefore, in this defect inspection apparatus, two objective lenses are arranged in the X direction by an integral multiple of the chip arrangement pitch in the X direction, and a pattern defect in a portion other than the cell is a defect in a corresponding portion of the two chips. It is detected by comparison. For this purpose, two objective lenses 21 and 22 are provided to make the light emitted from the light source 23 incident on the objective lens 21 via the half mirrors 24 and 25, and the half mirror 24, the mirror 26 and the half mirror 27 are provided.
After that, the beam spot is made incident on the objective lens 22 so that the beam spot is made incident on the wafer 29 placed on the XY table 28. The reflected light from the wafer 29 is
232 through half mirrors 25 and 27
Inject into 0 and 31. In this way, two image signals on the wafer can be obtained simultaneously. The output signal of one light receiving element 30 and the output signal of the other light receiving element 31 are supplied to a differential amplifier 32. As mentioned above,
The distance between the optical axes of the two objective lenses 21 and 22 is
Since the pitch is an integral multiple of the pitch of the semiconductor chips formed on the chip, if the pattern of the two chips scanned at the same time matches, there is no output from the differential amplifier. If the two do not match, a signal corresponding to the difference is supplied to the determination circuit 33 as a defect detection signal. As a result, it is possible to detect a defect in a pattern of a circuit portion other than the cell region of each chip. An output image signal of one light receiving element 30 is supplied to one input terminal of a differential amplifier 35 via a delay circuit 34 having a delay time τ required for scanning by a pitch distance between cells formed in a chip. . An image signal without delay is supplied to the other input terminal of the differential amplifier 35. In this manner, the differential amplifier 35 supplies an error signal indicating the difference between the patterns of two successive cells. This error signal is supplied to the first and second slice circuits 36 and 37 simultaneously. First
The slice circuit 36 has a slice level (+) shown in FIG. 3C.
The second slice circuit passes an error signal that exceeds
37 passes an error signal exceeding the level (-) in the negative direction, and the output signals of these slice circuits are supplied to the judgment circuit 33 via the first and second gate circuits 38 and 39. Now, when scanning inside the cell area, an output is generated only from the first and second slice circuits 37 and 38 when there is a defect, but at least one of the light beams scans a part other than the cell area. During scanning, a pseudo defect signal is output even if there is no defect. In order to eliminate such a problem, a control signal is supplied from the determination circuit 33 to these gate circuits 38 and 39, and when the objective lenses 21 and 22 are scanning the peripheral circuit portion surrounding the cell region, and When scanning a cell at a boundary position adjacent to the above, both gate circuits 38 and 39 are closed. During this period, a defect in the peripheral circuit pattern can be detected from the output signal of the differential amplifier 32. When the objective lenses 21 and 22 are further inside the cell area for scanning, the gate circuits 38 and 39 are opened to supply an error signal as shown in FIG. In this case, the judgment circuit
In 33, the cell adjacent to the peripheral circuit portion is subjected to the pattern comparison with the adjacent cell only once, but the other cells are compared with the cells adjacent to each other twice. (Problems to be Solved by the Invention) In the defect inspection apparatus shown in FIG. 4, the determination circuit 33 constantly monitors where the objective lenses 21 and 22 are scanning the object to be inspected, as described above. The first and second gate circuits 38 and 39 are closed when the objective lens is scanning the peripheral circuit portion surrounding the cell region and when scanning the cell at the boundary position adjacent to the peripheral region. It is necessary to supply a control signal to these gate circuits that opens the gate circuits 38 and 39 when scanning the area. However, it is not easy to generate such a control signal, and when the pattern structure of the target test object is changed, the control signal also needs to be changed, which is extremely troublesome. In addition, if there is an error in the control signal, the defect cannot be inspected correctly. In order to improve the inspection accuracy, it is necessary to generate a control signal that exactly matches the scanning by the objective lens. In addition, the cost required for inspection also increases. An object of the present invention is to solve the above-described drawbacks, and to generate a control signal according to the pattern structure of a test object even when a fine pattern scans a peripheral area of an adjacent cell area. It is an object of the present invention to provide a defect inspection apparatus capable of detecting a pattern defect in both the cell region and the peripheral region with high accuracy and sensitivity without any problem. (Means and Action for Solving the Problems) The present invention provides a unit having a first pattern portion having a large number of the same pattern at a first constant repetition pitch, and a second pattern portion having no repetition pattern. An apparatus for inspecting a defect of a pattern of a test object in which a large number of patterns are arranged at a second constant repetition pitch, wherein the first and second light beams are separated by a distance that is an integral multiple of the second repetition pitch of the unit pattern. Scanning means for irradiating the test object with a beam to scan the test object, and first and second light receiving means for receiving light beams from the test object and outputting first and second image signals, respectively A first comparing means for comparing the first and second image signals to detect a significant difference therebetween, and a first and a second signal outputted from the first and second light receiving means. of First and second delays of the image signal by the time required to scan the image signal by an integral multiple of the first repetition pitch of the first pattern portion, respectively.
Delay means, and second comparison means for comparing the first image signal and the delayed first image signal output from the first delay means to detect a significant difference therebetween, A third comparing unit that compares the second image signal with the delayed second image signal output from the second delay unit and detects a significant difference therebetween; and the second comparing unit. First gate means connected to the output of the means and closed when a difference is detected by the third comparing means; and second gate means connected to the output of the third comparing means. Receiving the signals output from the first comparing means, the first and second gate means, and outputting the signals output from the first comparing means. A defect in the second pattern portion based on the first and second gates. That it comprises a determination means for determining defects of the first pattern portion based on a signal from is characterized in. In such a pattern defect inspection apparatus according to the present invention, a large number of unit patterns each having a first pattern portion having the same pattern at a first constant repetition pitch and a second pattern portion having no repetition pattern are provided. When inspecting the defects of the test objects arranged at the second constant repetition pitch, when scanning the first pattern portion, the defect is simultaneously detected in the portions scanned by the first and second light beams. Is very small, so
The possibility that defect signals are simultaneously output from the second and third comparing means is extremely small, and the defect signal is output from only one of the comparing means.
When scanning the pattern portion of the second and third patterns,
By supplying the output signals of the second and third comparison means to the second and first gate circuits, respectively, based on the fact that a signal is always output from the comparison means, When scanning the second pattern portion without generating a control signal based on where the scanning is being performed, both the first and second gate circuits are closed, and a pseudo defect signal is output. Never. (Embodiment) FIG. 5 is a circuit diagram showing an embodiment of the defect inspection apparatus according to the present invention, in which parts corresponding to those shown in FIG. In this example, the first and second
The first and second image signals output from the light receiving elements 30 and 31 are supplied to a first comparison circuit 32. A first and second delay circuit 34 for delaying the first and second image signals output from the first and second light receiving elements 30 and 31 by the time τ required to scan the cell pitch, respectively.
And 40 via the second and third differential amplifiers 35 and 41
, And directly to the other input terminals of these differential amplifiers. In this way, the second and third differential amplifiers 35 and 41 output the error signal corresponding to the difference between the successive cell patterns. The error signal output from the second differential amplifier 35 is supplied to the first and second slice circuits 42 and 43, and the output error signal of the third differential amplifier 41 is output to the third and fourth slice circuits 44. And supply to 45. Output signals of the first and third slice circuits 42 and 44 are supplied to first and second gate circuits 46 and 47, respectively. As shown in FIG. 4, each of the slice circuits 42 to 45 and the gate circuits 46 and 47 has a slice circuit for detecting a positive-direction error signal, a slice circuit for detecting a negative-direction error signal, and a slice circuit for detecting these error signals. Although it has a gate circuit connected to the output side, FIG. 5 shows one slice circuit and one gate circuit respectively for the sake of simplicity of the drawing. In the present invention, the output signal of the second slice circuit 43 is supplied to the second gate circuit 47 as a control signal, and the output signal of the fourth slice circuit 45 is supplied to the first gate circuit 46 as a control signal. When the output signals are supplied from the fourth slice circuits 43 and 45, the gate circuits 46 and 47 are closed. Therefore, a defect signal is output from gate circuits 46 and 47 only when there is a pattern defect in the cell region. These defect signals are supplied to the judgment circuit 33. The determination circuit 33 is basically a circuit that takes the logical sum of the output signal of the first differential amplifier 32 and the output signals of the first and second gate circuits 46 and 47. A defect is detected from the output signal of the differential amplifier 32, and a defect is detected from the output signals of the first and second gate circuits 46 and 47 in the cell area. The first and second delay circuits 34 and 40 are variable delay circuits and are configured to be adjustable according to the time required to scan the cell pitch of the chip to be inspected.
These may be adjusted in conjunction with each other, or may be individually adjusted. The present invention is not limited only to the above-described embodiments, and various changes and modifications can be made. For example,
In the above-described embodiment, a pattern defect of a large number of chips formed on a wafer is detected. However, a defect of a pattern formed on a photomask can be inspected. In this case, light transmitted through the mask is received. What is necessary is just to make it inject into an element. Further, in the above-described example, the image signal is delayed by a time required for scanning by a distance equal to one pitch of the repetitive pattern. However, the image signal may be delayed by an integral multiple of this time. In the above-described example, the arrangement pitch of cells formed in the chip is assumed to be all equal. However, there is a memory in which a number of cells are formed in different regions at different arrangement pitches. When inspecting such a chip, a plurality of processing circuits including a delay circuit having a delay time corresponding to each pitch may be connected in parallel. (Effect of the Invention) According to the above-described defect inspection apparatus of the present invention, the image signal obtained by optically scanning the object to be inspected is converted by the time required to scan a distance that is an integral multiple of the repetition pitch of the same pattern. Since the signal is delayed and compared with the non-delayed signal, a defect of a fine repetitive pattern can be accurately detected with high sensitivity. Further, the output signals of the two comparing means for comparing the delayed signal and the non-delayed signal are supplied as control signals to the gate circuits connected to the output side of the other comparing means, respectively. These gate circuits can be closed when scanning a region other than the cell region without separately generating a control signal, so that the structure is simple and inexpensive.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram showing a basic configuration of a defect inspection apparatus derived in a process leading to the present invention, FIG. 2 is a plan view showing a pattern of a memory cell to be inspected, FIG. 4A to 4C are signal waveform diagrams for explaining a defect detection operation, FIG. 4 is a diagram showing a defect inspection device derived in a process leading to the present invention, and FIG. 5 is an example of a defect inspection device according to the present invention. FIG. 3 is a diagram illustrating a configuration of an example. 23 light source 21, 22 objective lens 28 XY stage 29 test object 30, 31 first and second light receiving elements 32 first comparison circuit 33 judgment circuit 34, 40 first and second delay circuits 35 and 41 second and third comparison circuits 42 to 45 first to fourth slice circuits 46 and 47 first and second slice circuits Gate circuit

Claims (1)

(57) [Claims] A test object in which a large number of unit patterns each having a first pattern portion having the same pattern at a first constant repetition pitch and a second pattern portion having no repetition pattern are arranged at a second constant repetition pitch. Scanning for irradiating the object with first and second light beams separated by a distance that is an integral multiple of the second repetition pitch of the unit pattern, and scanning the object. A first means for receiving a light beam from the test object and outputting first and second image signals, respectively;
And second light receiving means, first comparing means for comparing the first and second image signals to detect a significant difference therebetween, and output from the first and second light receiving means. First and second delay means for respectively delaying the first and second image signals by a time required to scan by an integral multiple of a first repetition pitch of the first pattern portion; and Second comparing means for comparing the image signal with the delayed first image signal output from the first delay means and detecting a significant difference therebetween; and the second image signal and the second image signal. A third comparing means for comparing a delayed second image signal outputted from the second delay means and detecting a significant difference therebetween, and a third comparing means connected to an output side of the second comparing means, A first gate which is closed when a difference is detected by the third comparing means; And second gate means connected to the output side of the third comparison means and closed when a difference is detected by the second comparison means; and A signal output from the second gate means is received, a defect of the second pattern portion is determined based on a signal output from the first comparison means, and a defect is determined based on signals from the first and second gate means. And a determining means for determining a defect in the first pattern portion.