JP2538245Y2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2538245Y2 JP2538245Y2 JP1988120044U JP12004488U JP2538245Y2 JP 2538245 Y2 JP2538245 Y2 JP 2538245Y2 JP 1988120044 U JP1988120044 U JP 1988120044U JP 12004488 U JP12004488 U JP 12004488U JP 2538245 Y2 JP2538245 Y2 JP 2538245Y2
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- wiring
- film
- semiconductor device
- concave portion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
【考案の詳細な説明】 以下の順序に従って本発明を説明する。DETAILED DESCRIPTION OF THE INVENTION The present invention will be described in the following order.
A.産業上の利用分野 B.考案の概要 C.従来技術[第3図] D.考案が解決しようとする問題点 E.問題点を解決するための手段 F.作用 G.実施例[第1図、第2図] H.考案の効果 (A.産業上の利用分野) 本考案は半導体装置、特に周辺部における歪による断
線を生じにくくした半導体装置に関する。A. Industrial applications B. Overview of the invention C. Conventional technology [Fig. 3] D. Problems to be solved by the invention E. Means to solve the problems F. Action G. Example [ 1 and 2] H. Effect of the Invention (A. Industrial Application Field) The invention relates to a semiconductor device, particularly to a semiconductor device in which disconnection due to distortion in a peripheral portion is hardly caused.
(B.考案の概要) 本考案は、半導体装置において、 周辺部において歪により配線が配線を生じるのを防止
するため、 絶縁膜表面に形成した第1の凹部内に配線を形成し、
更に絶縁膜表面に配線の幅と略同じ間隔を措いてダミー
用の第2の凹部を形成したものである。(B. Outline of Invention) In the present invention, in a semiconductor device, wiring is formed in a first concave portion formed on a surface of an insulating film in order to prevent wiring from being generated due to distortion in a peripheral portion,
Further, a second concave portion for a dummy is formed on the surface of the insulating film at an interval substantially equal to the width of the wiring.
(C.従来技術)[第3図] 第3図はLSIチップのパッド部における断面構造の従
来例を示すものである。図面において、1はシリコン半
導体基板、2は該半導体基板1を選択的に加熱酸化する
ことにより形成されたフィールド絶縁膜、3は該フィー
ルド絶縁膜2上を覆う表面平坦化用絶縁膜(リフロー
膜)、4は第1層目のアルミニウム配線膜で、図面に現
われている部分はパッドの下地である。5は第1層目の
アルミニウム配線膜4上を覆う層間絶縁膜(インターレ
イヤー)、6は該層間絶縁膜5に形成されたコンタクト
ホール、7は第2層目のアルミニウム配線膜で、コンタ
クトホール6を通して第1層目のアルミニウム配線膜4
と接続されている。8は第2層目のアルミニウム配線膜
7を保護する保護絶縁膜、9は該絶縁膜に形成されたパ
ッド用窓開部である。(C. Prior Art) [FIG. 3] FIG. 3 shows a conventional example of a sectional structure in a pad portion of an LSI chip. In the drawings, 1 is a silicon semiconductor substrate, 2 is a field insulating film formed by selectively heating and oxidizing the semiconductor substrate 1, and 3 is a surface planarizing insulating film (reflow film) covering the field insulating film 2. ), 4 is the first-layer aluminum wiring film, and the portion shown in the drawing is the base of the pad. Reference numeral 5 denotes an interlayer insulating film (interlayer) covering the first aluminum wiring film 4, reference numeral 6 denotes a contact hole formed in the interlayer insulating film 5, and reference numeral 7 denotes a second aluminum wiring film. 6 through the first layer aluminum wiring film 4
Is connected to Reference numeral 8 denotes a protective insulating film for protecting the second-layer aluminum wiring film 7, and reference numeral 9 denotes a pad window opening formed in the insulating film.
(D.考案が解決しようとする問題点) ところで、LSIチップはサイズが大きくなる傾向にあ
るが、LSIチップが巨大化すると大きな歪がLSIチップ周
辺部にかかり、その結果、アルミニウム配線膜4、7が
層間絶縁膜5等の応力によりずれを生じ断線する事故の
発生率が高くなるという問題が発生した。(D. Problems to be Solved by the Invention) By the way, the size of the LSI chip tends to be large. However, when the LSI chip becomes large, a large distortion is applied to the periphery of the LSI chip. As a result, the aluminum wiring film 4, 7 has a problem that the rate of occurrence of an accident of disconnection due to the stress of the interlayer insulating film 5 or the like is increased.
本願考案者はこの問題を解決すべく研究をしたとこ
ろ、層間絶縁膜等半導体基板1上に形成される膜の厚さ
の総和hがLSIチップの周辺部において不必要に厚くな
っており、そして、そのことがアルミニウム配線膜に加
わる応力を大きくする要因となっていることに気付い
た。即ち、層間絶縁膜等絶縁膜は配線間に加わる電圧に
対する耐圧を充分に確保するためにLSIチップの中心部
の微細ルールに従って成長させている。しかし、元来LS
Iチップの周辺部は中心部と異なりバラエティーに富ん
だ回路が組み込まれており、微細ルールではない。にも
拘わらず層間絶縁膜がLSIチップ周辺部においても微細
ルールに従って成長せしめられているので、必要以上に
層間絶縁膜の膜厚、そして、層間絶縁膜のほか半導体基
板1上に形成される各膜の膜厚の総和hが厚くなり、そ
の結果、アルミニウム配線膜4、7にかかる応力が非常
に大きくなってしまうのである。The inventor of the present application has studied to solve this problem. As a result, the total thickness h of the films formed on the semiconductor substrate 1 such as the interlayer insulating film is unnecessarily thick at the peripheral portion of the LSI chip, and It has been found that this is a factor that increases the stress applied to the aluminum wiring film. That is, an insulating film such as an interlayer insulating film is grown in accordance with a fine rule at the center of an LSI chip in order to sufficiently secure a withstand voltage against a voltage applied between wirings. But originally LS
Unlike the central part, the peripheral part of the I chip incorporates a variety of circuits and is not a fine rule. Nevertheless, since the interlayer insulating film is grown in accordance with the fine rules also in the peripheral portion of the LSI chip, the thickness of the interlayer insulating film is more than necessary, The total thickness h of the films becomes large, and as a result, the stress applied to the aluminum wiring films 4 and 7 becomes extremely large.
そこで、本願考案者は配線の形成前に半導体装置の周
辺部において絶縁膜を適宜カットしておくことにより絶
縁膜の実質的な薄膜化を図り、配線に加わる応力を緩和
するという着想を得て本考案を為すに至ったのである。Therefore, the inventor of the present application has obtained the idea that the insulating film is appropriately cut in the peripheral portion of the semiconductor device before the wiring is formed, whereby the insulating film is substantially thinned, and the stress applied to the wiring is reduced. This led to the invention.
しかして、本考案は周辺部において歪により配線が断
線を生じるのを防止することを目的とする。Accordingly, an object of the present invention is to prevent the wiring from being disconnected due to distortion in the peripheral portion.
(E.問題点を解決するための手段) 本考案半導体装置は上記問題点を解決するため、半導
体基板表面を覆うフィールド絶縁膜上の平坦化絶縁膜
に、該半導体基板周辺部であって上層配線からなるパッ
ド電極を形成すべき各位置を占有する第1の凹部が形成
され、該第1の凹部の略中心部に電極パッドの下地とな
る下層配線が形成され、上記平坦化絶縁膜の第1の凹部
の外側の部分に、上記下層配線の幅と略等しい間隔を措
いて少なくとも1つのダミー用の第2の凹部が形成さ
れ、上記平坦化絶縁膜上に上記下層配線を覆い且つ各凹
部を埋める、該下層配線と上記上層配線との間を絶縁す
る層間絶縁膜が形成されたことを特徴とする。(E. Means for Solving the Problems) In order to solve the above problems, the semiconductor device of the present invention includes a planarizing insulating film on a field insulating film covering the surface of a semiconductor substrate, and A first concave portion occupying each position where a pad electrode composed of a wiring is to be formed is formed, and a lower layer wiring serving as a base of an electrode pad is formed substantially at the center of the first concave portion. At least one second concave portion for dummy is formed in a portion outside the first concave portion at an interval substantially equal to the width of the lower wiring, and covers the lower wiring on the flattening insulating film. An interlayer insulating film that fills the recess and insulates between the lower wiring and the upper wiring is formed.
(F.作用) 本考案半導体装置によれば、絶縁膜に第1の凹部を形
成し、該第1の凹部内に配線を形成するので、第1の凹
部の深さ分半導体基板上に形成される各膜の膜厚の総和
が薄くなり、延いては配線に加わる応力の低減を図るこ
とができる。(F. Function) According to the semiconductor device of the present invention, since the first concave portion is formed in the insulating film and the wiring is formed in the first concave portion, the semiconductor device is formed on the semiconductor substrate by the depth of the first concave portion. Thus, the total thickness of the films to be formed is reduced, and the stress applied to the wiring can be reduced.
そして、絶縁膜の第1の凹部の外側にダミー用の第2
の凹部が形成されているので、配線上の層間絶縁膜をバ
イアスCVDあるいはバイアススパッタあるいはAr逆スパ
ッタにより形成した場合回路的には疎となる半導体装置
周辺部上においても層間絶縁膜を比較的薄く且つ平坦化
することができる。従って、この点も半導体基板上に形
成される各膜の膜厚の総和を小さくする要因となり、延
いては配線にかかる応力をより緩和することができる。Then, a second dummy portion is formed outside the first concave portion of the insulating film.
When the interlayer insulating film on the wiring is formed by bias CVD, bias sputtering, or Ar reverse sputtering, the interlayer insulating film is relatively thin even on the periphery of the semiconductor device, which is sparse in circuit. In addition, it can be flattened. Therefore, this point also causes a reduction in the sum of the thicknesses of the respective films formed on the semiconductor substrate, so that the stress applied to the wiring can be further reduced.
(G.実施例)[第1図、第2図] 以下、本考案半導体装置を図示実施例に従って詳細に
説明する。(G. Embodiment) [FIGS. 1 and 2] Hereinafter, the semiconductor device of the present invention will be described in detail with reference to the illustrated embodiments.
第1図は本考案半導体装置の一つの実施例を示す周辺
部の断面図である。同図において、1は半導体基板、2
は該半導体基板1を選択的に加熱酸化することにより形
成されたフィールド絶縁膜、3は該フィールド絶縁膜上
に形成された平坦化用絶縁膜(リフロー膜)、10は該絶
縁膜3に形成された第1の凹部で、該第1の凹部10の略
中央部に第1層目のアルミニウム配線膜4のパッドの下
地となる部分が形成されている。11、11はそのアルミニ
ウム配線膜4のパッド下地部分と第1の凹部10の内側面
との間隙部分である。12、12は平坦化用絶縁膜3の第1
の凹部10の外側に形成されたダミー用の第2の凹部で、
第1の凹部10からパッド下地部分の幅Wと等しく間隔を
措いて少なくとも1個、好ましくは数個乃至数十個形成
されている。該ダミー用の第2の凹部12、12の幅は上記
間隙部分11、11の幅と略等しくされている。この第1の
凹部10、配線膜4、ダミー用の第2の凹部12、12の形成
は半導体装置の中央部の微細ルールに従って形成されて
いる。FIG. 1 is a sectional view of a peripheral portion showing one embodiment of the semiconductor device of the present invention. In the figure, 1 is a semiconductor substrate, 2
Is a field insulating film formed by selectively heating and oxidizing the semiconductor substrate 1, 3 is a planarizing insulating film (reflow film) formed on the field insulating film, and 10 is formed on the insulating film 3. In the first recess thus formed, a portion serving as a base of a pad of the first-layer aluminum wiring film 4 is formed substantially in the center of the first recess 10. Numerals 11 and 11 denote gaps between the pad base portion of the aluminum wiring film 4 and the inner side surface of the first recess 10. 12 and 12 are the first of the planarization insulating film 3.
A second concave portion for dummy formed outside the concave portion 10 of
At least one, preferably several to several tens, are formed from the first recess 10 at an interval equal to the width W of the pad base portion. The width of the dummy second concave portions 12 is substantially equal to the width of the gap portions 11. The formation of the first concave portion 10, the wiring film 4, and the second concave portions 12 for dummy are formed in accordance with a fine rule in the center of the semiconductor device.
5は平坦化用絶縁膜3及びアルミニウム配線膜4上を
覆うSiO2からなる層間絶縁膜、6は該層間絶縁膜5に形
成されたところのアルミニウム配線膜4のパッド下地部
分を露出させるコンタクトホール、7は第2層目のアル
ミニウム配線膜で、コンタクトホール6を通して第1層
目のアルミニウム配線膜4のパッド下地部分の表面にコ
ンタクトせしめられている。8は第2層目のアルミニウ
ム配線膜7を保護する保護絶縁膜、9は該保護絶縁膜8
に形成されたパッド用窓開部で、アルミニウム配線膜7
の該窓開部9に露出する部分がボンディングパッドとな
る。Reference numeral 5 denotes an interlayer insulating film made of SiO 2 which covers the planarizing insulating film 3 and the aluminum wiring film 4, and reference numeral 6 denotes a contact hole for exposing a pad base portion of the aluminum wiring film 4 formed on the interlayer insulating film 5. Reference numeral 7 denotes a second-layer aluminum wiring film, which is in contact with the surface of the pad base portion of the first-layer aluminum wiring film 4 through the contact hole 6. 8 is a protective insulating film for protecting the second-layer aluminum wiring film 7, and 9 is the protective insulating film 8.
Aluminum wiring film 7 in the pad opening formed in
The portion exposed to the window opening 9 becomes a bonding pad.
このような半導体装置によれば、平坦化用絶縁膜3の
アルミニウム配線膜4のパッド下地部分を形成すべき部
分がカットされて第1の凹部10とされ、その第1の凹部
10内にアルミニウム配線膜4のパッド下地部分が形成さ
れている。従って、そのことによって、第3図に示す従
来の半導体装置に比較してチップ周辺部における半導体
基板1上に形成される各膜の膜厚の総和hをその第1の
凹部10の深さ(本実施例においては略平坦化用絶縁膜3
の厚さ)分薄くできる。According to such a semiconductor device, a portion of the flattening insulating film 3 where the pad base portion of the aluminum wiring film 4 is to be formed is cut into the first concave portion 10, and the first concave portion 10 is formed.
In 10, a pad base portion of the aluminum wiring film 4 is formed. Accordingly, as compared with the conventional semiconductor device shown in FIG. 3, the sum h of the thicknesses of the respective films formed on the semiconductor substrate 1 in the peripheral portion of the chip is thereby reduced by the depth of the first concave portion 10 ( In the present embodiment, the substantially planarizing insulating film 3 is used.
Thickness).
また、絶縁膜の第1の凹部10内側面とアルミニウム配
線膜4のパッド下地部分との間に間隙部分11が設けら
れ、更に第1の凹部10の外側にパッド下地部分の幅Wと
略等しい間隔を措いてダミー用の第2の凹部12、12、…
形成されているので、絶縁膜3及びアルミニウム配線膜
4上を覆う層間絶縁膜5の膜厚もより薄くすることがで
きる。A gap portion 11 is provided between the inner surface of the first concave portion 10 of the insulating film and the pad base portion of the aluminum wiring film 4, and is substantially equal to the width W of the pad base portion outside the first concave portion 10. The second recesses 12, 12,... For the dummy are spaced apart.
Since it is formed, the film thickness of the interlayer insulating film 5 covering the insulating film 3 and the aluminum wiring film 4 can be further reduced.
というのは、層間絶縁膜5は表面を平坦化するうえで
バイアススパッタ法によりあるいはバイアスECR法によ
りSiO2で形成することが好ましいといえるが、このよう
な方法においても下地の凹凸が疎の部分上における層間
絶縁膜の膜厚が密の部分上におけるそれよりも厚くなる
という傾向がある。従って、従来のように層間絶縁膜5
の下地が周辺部において疎であった場合にはその周辺部
における層間絶縁膜5の膜厚が中央部におけるそれより
も稍厚くなりがちであり、層間絶縁膜5の周辺部におけ
る膜厚を薄くすることが難しかった。しかるに第1図に
示した本半導体装置においては絶縁膜3にダミー用の第
2の凹部12、12を設け、更に第1の凹部10とアルミニウ
ム配線膜4のパッド下地部分との間にも間隙部分11、11
を設けて、層間絶縁膜5の下地が半導体装置中央部にお
ける微細ルールと同じルールに従った凹凸を有するよう
にしたので、層間絶縁膜5の半導体装置周辺部における
膜厚を半導体装置中央部における膜厚と同程度に薄くす
ることができる。このように層間絶縁膜5についても従
来よりも半導体装置周辺部における膜厚を薄くすること
ができる。そして、このことも半導体基板1上に形成さ
れた各膜の膜厚の総和を薄くすることを可能にする要因
となる。This is because it is preferable that the interlayer insulating film 5 is formed of SiO 2 by the bias sputtering method or the bias ECR method in order to flatten the surface. There is a tendency that the thickness of the upper interlayer insulating film becomes thicker than that of the dense portion. Therefore, as in the prior art, the interlayer insulating film 5
If the underlayer is not sparse in the peripheral portion, the film thickness of the interlayer insulating film 5 in the peripheral portion tends to be slightly thicker than that in the central portion, and the film thickness in the peripheral portion of the interlayer insulating film 5 is reduced. It was difficult to do. In the present semiconductor device shown in FIG. 1, however, the second recesses 12 and 12 for dummy are provided in the insulating film 3, and a gap is provided between the first recess 10 and the pad base portion of the aluminum wiring film 4. Parts 11, 11
Is provided so that the underlayer of the interlayer insulating film 5 has irregularities in accordance with the same rule as the fine rule in the central portion of the semiconductor device. It can be made as thin as the film thickness. As described above, the thickness of the interlayer insulating film 5 at the peripheral portion of the semiconductor device can be reduced as compared with the related art. This also becomes a factor that makes it possible to reduce the total thickness of each film formed on the semiconductor substrate 1.
このように半導体基板1上の各膜の膜厚の総和を薄く
することができるので、歪によってアルミニウム配線膜
4、7の特に半導体装置周辺部に存在する部分に加わる
応力を軽減することができ、半導体装置の断線を防止す
ることができる。また、第1層目と第2層目のアルミニ
ウム配線膜7・4間に介在する層間絶縁膜5の応力によ
る割れに起因する絶縁不良を防止することもできる。As described above, since the total thickness of the films on the semiconductor substrate 1 can be reduced, the stress applied to the aluminum wiring films 4 and 7 due to the strain, particularly at the portions existing around the semiconductor device, can be reduced. In addition, disconnection of the semiconductor device can be prevented. Further, it is also possible to prevent insulation failure due to cracking of the interlayer insulating film 5 interposed between the first and second aluminum wiring films 7 and 4 due to stress.
第2図(A)乃至(F)は第1図に示した半導体装置
の製造方法を工程順に示すところのパッド部及びその近
傍の断面図である。2 (A) to 2 (F) are cross-sectional views of a pad portion and its vicinity showing a method of manufacturing the semiconductor device shown in FIG. 1 in the order of steps.
(A)普通の製造プロセスで、平坦化用絶縁膜(リフロ
ー膜)3を形成し終えた第2図(A)に示す状態にす
る。(A) The state shown in FIG. 2 (A) in which the flattening insulating film (reflow film) 3 has been formed by the ordinary manufacturing process.
(B)次に、絶縁膜3のコンタクトホール形成のための
エッチング工程で、第1層目のアルミニウム配線膜を形
成すべき部分に第1の凹部10を形成し、その近傍にダミ
ー用の第2の凹部12、12をも形成することとする。即
ち、従来においては絶縁膜3形成後それに対してコンタ
クトホールを形成するエッチング処理を施していたが、
後でアルミニウム配線膜を形成すべき部分をエッチング
して第1の凹部10を形成したり、ダミー用の第2の凹部
12、12、…を形成したりすることは為されていなかっ
た。しかし、本考案半導体装置を製造する場合にはそれ
を行うのである。これはエッチング用のフォトマスクの
パターンを変えるだけで実現でき、工程を増やすことは
必要としない。第2図(B)はこの平坦化用絶縁膜に対
するエッチグ工程の終了後の状態を示す。(B) Next, in an etching step for forming a contact hole in the insulating film 3, a first concave portion 10 is formed in a portion where a first aluminum wiring film is to be formed, and a dummy concave portion 10 is formed in the vicinity thereof. Two concave portions 12 are also formed. That is, in the related art, an etching process for forming a contact hole is performed on the insulating film 3 after the insulating film 3 is formed.
A portion where an aluminum wiring film is to be formed is later etched to form a first concave portion 10 or a second concave portion for a dummy.
No formation of 12, 12, ... was made. However, when manufacturing the semiconductor device of the present invention, it is performed. This can be realized only by changing the pattern of the photomask for etching, and does not require additional steps. FIG. 2B shows a state after the etching step for the planarizing insulating film is completed.
(C)次に、同図(C)に示すようにアルミニウム配線
膜4をスパッタリングにより形成する。アルミニウム配
線膜4の膜厚は平坦化用絶縁膜3の膜厚と同程度が良
い。(C) Next, as shown in FIG. 3C, an aluminum wiring film 4 is formed by sputtering. The thickness of the aluminum wiring film 4 is preferably about the same as the thickness of the planarizing insulating film 3.
(D)次に、同図(D)に示すようにアルミニウム配線
膜4をエッチングによりパターニングする。(D) Next, the aluminum wiring film 4 is patterned by etching as shown in FIG.
(E)次に、同図(E)に示すように例えばSiO2からな
る層間絶縁膜5をバイアススパッタ法あるいはバイアス
ECRCVD法あるいはAr逆スパッタ法により形成する。する
と、半導体装置5の周辺部上においても層間絶縁膜5の
膜厚を比較的薄くすることができる。なぜならば、前述
のとおり半導体装置の周辺部には中央部と同じように微
細な凹凸が形成され、それを下地として層間絶縁膜5が
形成されるからである。(E) Next, as shown in FIG. 7E, the interlayer insulating film 5 made of, for example, SiO 2 is formed by bias sputtering or bias.
It is formed by ECRCVD or Ar reverse sputtering. Then, the film thickness of the interlayer insulating film 5 can be made relatively thin even on the peripheral portion of the semiconductor device 5. This is because, as described above, fine irregularities are formed in the peripheral portion of the semiconductor device as in the central portion, and the interlayer insulating film 5 is formed using the fine irregularities as a base.
(F)次に、同図(F)に示すように層間絶縁膜5に対
するエッチングを行うことによりコンタクトホール6を
形成する。(F) Next, as shown in FIG. 2F, the contact hole 6 is formed by etching the interlayer insulating film 5.
その後は第2層目のアルミニウム配線膜を形成すると
周辺部が第1図に示すような断面構造を有する半導体装
置が得られる。Thereafter, when a second-layer aluminum wiring film is formed, a semiconductor device having a peripheral portion having a cross-sectional structure as shown in FIG. 1 is obtained.
(H.考案の効果) 以上に述べたように、本考案半導体装置は、半導体基
板表面を覆うフィールド絶縁膜上の平坦化絶縁膜に、該
半導体基板周辺部であって上層配線からなるパッド電極
を形成すべき各位置を占有する第1の凹部が形成され、
該第1の凹部の略中心部に電極パッドの下地となる下層
配線が形成され、上記平坦化絶縁膜の第1の凹部の外側
の部分に、上記下層配線の幅と略等しい間隔を措いて少
なくとも1つのダミー用の第2の凹部が形成され、上記
平坦化絶縁膜上に上記下層配線を覆い且つ各凹部を埋め
る、下層配線と上記配線との間を絶縁する層間絶縁膜が
形成されたことを特徴とする。(H. Effect of the Invention) As described above, the semiconductor device of the present invention includes a pad electrode formed of an upper layer wiring at a peripheral portion of the semiconductor substrate on the flattening insulating film on the field insulating film covering the surface of the semiconductor substrate. A first recess occupying each position to be formed is formed,
A lower layer wiring serving as a base of the electrode pad is formed at a substantially central portion of the first recess, and an interval substantially equal to the width of the lower layer wiring is provided on a portion of the planarization insulating film outside the first recess. At least one dummy second recess is formed, and an interlayer insulating film that covers the lower wiring and fills each recess and that insulates between the lower wiring and the wiring is formed on the planarization insulating film. It is characterized by the following.
従って、本考案半導体装置によれば、絶縁膜に第1の
凹部を形成し、該第1の凹部内に配線を形成するので、
第1の凹部の深さ分半導体基板上に形成される各膜の膜
厚の総和が薄くなり、延いては配線に加わる応力の低減
を図ることができる。Therefore, according to the semiconductor device of the present invention, the first recess is formed in the insulating film, and the wiring is formed in the first recess.
The sum of the thicknesses of the films formed on the semiconductor substrate is reduced by the depth of the first concave portion, so that the stress applied to the wiring can be reduced.
そして、絶縁膜の第1の凹部の外側にダミー用の第2
の凹部が形成されているので、配線上の層間絶縁膜をバ
イアスCVDあるいはバイアススパッタあるいはAr逆スパ
ッタにより形成した場合回路的には疎となる周辺部上に
おいても層間絶縁膜の下地に密な凹凸が形成できる。従
って、層間絶縁膜配線を比較的薄く且つ平坦化すること
ができる。従って、この点も半導体基板上に形成される
各膜の膜厚の総和を小さくする要因となり、延いては配
線にかかる応力を緩和することができる。Then, a second dummy portion is formed outside the first concave portion of the insulating film.
When the interlayer insulating film on the wiring is formed by bias CVD, bias sputtering, or Ar reverse sputtering, dense unevenness is formed on the underlayer of the interlayer insulating film even on the peripheral portion, which is sparse in circuit. Can be formed. Therefore, the interlayer insulating film wiring can be made relatively thin and flat. Therefore, this point also causes a reduction in the sum of the film thicknesses of the films formed on the semiconductor substrate, and thus can reduce the stress applied to the wiring.
第1図は本考案半導体装置の一つの実施例を示す周辺部
の断面図、第2図(A)乃至(F)は第1図に示した半
導体装置の製造方法を工程順に示す半導体装置周辺部の
断面図、第3図は従来例を示す半導体装置周辺部の断面
図である。 符号の説明 2、3……絶縁膜、4……配線、5……層間絶縁膜、10
……第1の凹部、11……間隙部、12……第2の凹部。FIG. 1 is a sectional view of a peripheral portion showing one embodiment of the semiconductor device of the present invention, and FIGS. 2 (A) to 2 (F) are diagrams showing a method of manufacturing the semiconductor device shown in FIG. FIG. 3 is a sectional view of a peripheral portion of a semiconductor device showing a conventional example. Reference numerals 2, 3,..., Insulating film, 4,.
... First recess, 11 gap, 12 second recess.
Claims (1)
の平坦化絶縁膜に、該半導体基板周辺部であって上層配
線からなるパッド電極を形成すべき各位置を占有する第
1の凹部が形成され、 上記第1の凹部の略中心部に電極パッドの下地となる下
層配線が形成され、 上記平坦化絶縁膜の第1の凹部の外側の部分に、上記下
層配線の幅と略等しい間隔を措いて少なくとも1つのダ
ミー用の第2の凹部が形成され、 上記平坦化絶縁膜上に上記下層配線を覆い且つ各凹部を
埋める、該下層配線と上記上層配線との間を絶縁する層
間絶縁膜が形成された ことを特徴とする半導体装置A first concave portion which occupies a peripheral portion of the semiconductor substrate and occupies a position where a pad electrode composed of an upper wiring is to be formed in a planarizing insulating film on a field insulating film covering a surface of the semiconductor substrate; A lower layer wiring serving as a base of the electrode pad is formed substantially at the center of the first recess, and a gap substantially equal to the width of the lower layer wiring is formed at a portion of the planarizing insulating film outside the first recess. At least one dummy second concave portion is formed, and the interlayer insulating film covers the lower wiring and fills each concave portion on the planarization insulating film, and insulates between the lower wiring and the upper wiring. Semiconductor device characterized by forming
Priority Applications (1)
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---|---|---|---|
JP1988120044U JP2538245Y2 (en) | 1988-09-12 | 1988-09-12 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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JP1988120044U JP2538245Y2 (en) | 1988-09-12 | 1988-09-12 | Semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH0241442U JPH0241442U (en) | 1990-03-22 |
JP2538245Y2 true JP2538245Y2 (en) | 1997-06-11 |
Family
ID=31365798
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JP1988120044U Expired - Lifetime JP2538245Y2 (en) | 1988-09-12 | 1988-09-12 | Semiconductor device |
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JP (1) | JP2538245Y2 (en) |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
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JPS6325951A (en) * | 1986-07-17 | 1988-02-03 | Nec Corp | Semiconductor device |
JPS63211739A (en) * | 1987-02-27 | 1988-09-02 | Nec Corp | Semiconductor device |
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1988
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