JP2570953B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a multilayer wiring structure, and more particularly, to a method of manufacturing a semiconductor device in which an interlayer film is planarized.

[0002]

2. Description of the Related Art An example of a conventional multilayer wiring structure of this type will be described with reference to FIG. First, as shown in FIG. 6A, an insulating film 42 is formed on a semiconductor substrate 41 on which a semiconductor element is formed, and after opening necessary portions, a metal film 43 such as aluminum or an alloy of aluminum and copper is formed. To form
Further, as shown in FIG. 6B, a resist 4 is formed on the metal film 43.
4 is formed in a required pattern. Then, as shown in FIG. 6C, the metal film 43 is etched using the resist 44 as a mask, and the resist is removed, so that the wiring pattern 45 actually used and the upper interlayer film are flattened. A dummy wiring pattern 46 to be used is formed. The steps of the wiring pattern 45 are reduced by the dummy wiring pattern 46, and the surface of the interlayer film formed thereon is planarized.

[0003] As another conventional flattened structure, there is a structure in which no dummy wiring is provided as shown in FIG. In this example, a liquid phase growth method (LPD: Liquid
An oxide film (SiO ₂ ) formed by Phase Deposition is used. First, as shown in FIG. 7A, an insulating film 52 is formed on a semiconductor substrate 51 on which a semiconductor element is formed, a necessary portion is opened, and a metal film such as aluminum or an alloy of aluminum and copper is formed. Form. Further, a resist (not shown) is formed in a required pattern on the metal film, the metal film is etched using the resist as a mask, and the resist is removed, thereby forming a wiring pattern 53 actually used. Here, the wiring pattern 53 may be formed by electrolytic plating of gold, copper, or the like. Next, as shown in FIG. 7B, a CVD oxide film 54 is grown on the entire surface, and as shown in FIG. 7C, an LPD oxide film 55 is grown to form an interlayer film. 55 reduces the level difference of the wiring pattern 53 to achieve flattening.

[0004]

In the semiconductor device having the structure shown in FIG. 6, there is a problem that the wiring capacitance between the dummy wiring pattern and the wiring layer immediately above or below is increased. For example, in a three-layer wiring, a first layer and a third layer are parallel to each other, and a second layer perpendicularly intersects the first and third layers, and a floating dummy is provided between fixed potential wirings connected to pads. Consider an example of a wiring capacitance measurement pattern in which a wiring pattern is formed and the ratio between the dummy wiring pattern and the fixed potential wiring is 3: 1. When the capacitance of this pattern was measured, the wiring width was 1.2 μm, the wiring pitch was 2 to 2.2 μm, the wiring length was about 860 μm, the wiring material was AlSi about 1 μm, and the interlayer film was flat with a structure in which an inorganic coating film was sandwiched between CVD oxide films. In the case where the thickness of the flat portion is about 1 μm, there is almost no difference in the wiring capacitance between the presence and absence of the dummy wiring pattern of the first layer in the second layer, but the wiring capacitance is in the second layer in the third layer. If there is a dummy wiring pattern, it increases by 6 to 8%. The first layer increases by 5 to 10% when the dummy wiring pattern is present in the second layer, and the second layer increases by 14 to 19% when the dummy wiring pattern is present in the third layer. In the future, when multilayer wiring is further provided and dummy wiring patterns are present in both upper and lower layers, the wiring capacitance will further increase. There is a problem that the processing speed of the semiconductor device is reduced due to such an increase in the wiring capacity.

On the other hand, in the structure shown in FIG. 7, the oxide film 55 is grown by the LPD method to fill the recesses between the wiring patterns 53, but since the LPD oxide film is isotropically grown, The oxide film 55 is also grown on the surface of the wiring pattern 53 simply by LPD growth.
Cannot be planarized, and some process is required. For this reason, as a result, a conventional method, for example, a process of applying a resin or the like on an interlayer film which is not flat and etching it back to flatten it is necessary, which complicates the manufacturing process. become. An object of the present invention is to provide a semiconductor device in which a multilayer wiring structure is flattened while preventing an increase in wiring capacitance due to a dummy wiring pattern. Another object of the present invention is to provide a method of manufacturing a semiconductor device in which a multilayer wiring structure is flattened without complicating the number of manufacturing steps.

[0006]

According to a method of manufacturing a semiconductor device of the present invention, a step of forming an aluminum film on a semiconductor substrate and a step of forming a part of the aluminum film on at least the surface side are performed.
A step of forming an alumina layer by oxidizing a part thereof and a step of patterning the aluminum film to form a wiring pattern made of aluminum and a dummy wiring pattern made of alumina. Further, a step of selectively patterning the conductive film on the semiconductor substrate to form a wiring pattern, a step of forming a mask film having an opening between the wiring patterns, and a liquid phase growth method in the opening of the mask film Forming an insulating film and forming the insulating film left after removing the mask film as a dummy wiring pattern.

[0007]

Next, the present invention will be described with reference to the drawings. FIG. 1 is a cross-sectional view showing a reference example of the present invention together with its manufacturing steps. First, as shown in FIG. 1A, an insulating film 2 is formed on a semiconductor substrate 1 on which a semiconductor element is formed, and after opening necessary portions, a metal film such as aluminum or an alloy of aluminum and copper is formed. Form. Furthermore, by forming a resist in a required pattern on the metal film, etching the metal film using the resist as a mask, and removing the resist,
The wiring pattern 3 actually used is formed. here,
The metal film may be gold or copper formed by electrolytic plating or the like. Next, as shown in FIG. 1B, an inorganic coating film such as silica or an organic coating film such as polyimide is spin-coated,
The coating film 4 is formed by applying a heat treatment at about 400 ° C. for about 60 minutes. At this time, the viscosity of the coating film 4 and the number of application rotations are adjusted so that the thickness of the flat portion after the heat treatment becomes substantially the same as that of the wiring pattern 3. Here, instead of the coating film, an inorganic film such as a silicon oxide film or a silicon nitride film may be formed to have substantially the same thickness as the wiring by a vapor phase growth method or the like.

Next, as shown in FIG. 1C, a resist 5 is patterned on the coating film 4. Here, the patterning of the resist is performed by using the wiring pattern 3 shown in FIG.
The other vacant areas are formed in accordance with the wiring pitch, that is, the dummy wiring pattern alone. Next, as shown in FIG. 1D, anisotropic etching of the coating film 4 is performed using the patterned resist 5 as a mask, and the same width and thickness as those of the wiring pattern are formed in the space between the wiring patterns 3. A dummy wiring pattern 6 having a pitch is formed. In this case, a dummy wiring pattern made of a coating film may be formed first, and then a wiring pattern may be formed. Therefore, according to this configuration, since the dummy wiring pattern 6 formed between the wiring patterns 3 is formed of the insulating film, the wiring capacity between the upper and lower wiring layers does not increase, and the operation of the semiconductor device does not increase. This has the effect of improving speed.

FIG. 2 is a view showing a second reference example of the present invention. First, as shown in FIG. 2A, an insulating film 12 is formed on a semiconductor substrate 11 on which a semiconductor element is formed, a necessary portion is opened, and a metal film such as aluminum or an alloy of aluminum and copper is formed. Form. Further, a resist is formed in a required pattern on the metal film, the metal film is etched using the resist as a mask, and the resist is removed to form a wiring pattern 13 actually used. Here, the metal film may be gold, copper, or the like formed by electrolytic plating or the like. Next, as shown in FIG. 2B, a resist 14 is spin-coated, and an opening is formed at a position where a dummy wiring pattern is to be formed at the same width and pitch as the wiring pattern 13. At this time, the viscosity of the resist and the number of coating rotations are adjusted so that the thickness of the flat portion of the resist 14 is thicker than the wiring pattern 13. Next, as shown in FIG. 2C, an inorganic coating material such as silica or an organic coating material such as polyimide is spin-coated on the resist 14 and heat-treated at 100 to 150 ° C. for about 1 minute on a hot plate. The coating film 15 is formed.

Next, as shown in FIG.
The entire surface of the coating film 15 is etched until the thickness of the coating film 15 in the opening of the opening becomes approximately the same as the wiring pattern, and the resist 14 is removed. A dummy wiring pattern 16 having substantially the same width, thickness, and pitch as the wiring is formed in a space between the wirings 13. Also in this reference example , by forming the dummy wiring pattern 16 with an insulating film, an increase in capacitance between the upper and lower wiring layers can be prevented. In addition,
Even in this case, a dummy wiring pattern made of a coating film may be formed first, and then a wiring pattern may be formed. or,
In this embodiment, since the dummy wiring pattern is formed by etching the entire surface, either anisotropic etching or isotropic etching may be used, and the etching conditions can be determined relatively easily.

FIG. 3 is a diagram showing a first embodiment of the present invention. First, as shown in FIG. 3A, a silicon oxide film 22 as an insulating film is formed on a silicon substrate 21, and after opening necessary portions, an aluminum film 23 as a conductive film is formed. Further, as shown in FIG. 3B, a resist pattern 25 patterned using a photolithography technique is used.
Is formed, and the aluminum film 23 is selectively subjected to anodic oxidation using the mask as a mask, so that at least a region to be a dummy wiring pattern is formed as an aluminum oxide (alumina) layer 24 which is an aluminum compound and is also an insulator. . Next, as shown in FIG. 3C, a resist pattern 26 for forming a wiring pattern and a dummy wiring pattern is formed again by using the photolithography technique.
Then, using the resist pattern 26 as a mask, the aluminum film 23 and the alumina layer 24 are simultaneously patterned by anisotropic dry etching, and then the resist is removed. Thus, a wiring pattern 27 formed of aluminum and a dummy wiring pattern 28 formed of alumina are formed. In this embodiment, since the dummy wiring pattern 28 is formed of an insulating film, the increase in capacitance between the upper and lower wiring layers can be prevented. However, this embodiment has an advantage that the wiring pattern and the dummy wiring pattern can be formed in the same etching step.

FIG. 4 is a diagram showing a second embodiment of the present invention. Here, as shown in FIGS. 4A and 4B,
After the aluminum film 23 is formed in the same manner as in the first embodiment, the aluminum film is selectively anodized to form the alumina layer 24. In this case, a part of the thickness from the surface of the aluminum film 23 is reduced. 24. Then, as shown in FIGS. 4C and 4D, a wiring pattern 27 and a dummy wiring pattern 28 are formed in the same steps as in the third embodiment. In this embodiment as well, the increase in capacitance between the upper and lower wiring layers is of course prevented. However, since the depth of the alumina layer 24 may be small, the alumina The spread of the layer 24 in the horizontal direction can be suppressed, and it can be applied to an element having a finer pitch. Although anodization is used as an example in which aluminum is used as alumina, the present invention is not limited to this method.

FIG. 5 shows a third embodiment of the present invention. First, as shown in FIG. 5A, an insulating film 32 is formed on a semiconductor substrate 31 on which a semiconductor element is formed, and after opening necessary portions, a metal film such as aluminum or an alloy of aluminum and copper is formed. Form. Further, a resist is formed in a required pattern on the metal film, the metal film is etched using the resist as a mask, and the resist is removed to form a wiring pattern 33 actually used. The wiring pattern 33 may be formed by a metal electrolytic plating method.
Next, as shown in FIG. 5B, a resist 34 is spin-coated on the wiring pattern 33, and an opening is formed at a position where a dummy wiring pattern is to be formed with the same width and the same pitch as the wiring pattern 33. At this time, the viscosity of the resist 34 and the number of coating rotations are adjusted so that the thickness of the flat portion of the resist 34 is thicker than the wiring pattern 33.

Next, as shown in FIG. 5C, an oxide film 35 grown by the LPD method is selectively grown only in the opening of the resist 44. At this time, the growth conditions are controlled so that the thickness of the LPD oxide film 35 is substantially the same as that of the wiring pattern 33. Thereafter, as shown in FIG. 5D, by removing the resist 34, a dummy wiring pattern 36 having the same width, thickness, and pitch as the wiring pattern 33 is formed in the vacant area between the wiring patterns 33 by LPD oxidation. Membrane 35
Formed by Therefore, also in this configuration, an increase in capacitance between the upper and lower wiring layers can be prevented.

Further, in the third embodiment, the first,
Unlike the second embodiment, since there is no etching step in forming the dummy wiring pattern, the adverse effect of the etching can be prevented. That is, when the dummy wiring pattern is formed by etching, an etching residue may be generated on the side surface of the dummy wiring pattern, and in some cases, on the side surface of the wiring pattern, and this residue causes a defect in a later process. For example, this may cause a “nest” when forming the insulating film immediately above. In this regard, in this embodiment, since there is no etching step, no etching residue is generated on the side surface of each wiring pattern, and defects in later steps are prevented beforehand, and the production yield is improved. In this case, since the dummy wiring pattern is formed by LPD, only the grown film thickness needs to be controlled, and the control of the condition can be performed much more easily than the control of the etching condition. You. Also, by omitting the etching process,
The manufacturing process is also shortened.

[0016]

In is produced by the present invention as has been described above, according to the present invention
In the semiconductor device , the dummy wiring pattern formed between the wiring patterns is formed of an insulating film, so that the wiring capacity between the upper and lower wiring layers is not increased, and the processing speed of the semiconductor device can be improved. There is. According to the manufacturing method of the present invention (claim 1 ), by selectively forming alumina on aluminum, a wiring pattern and a dummy wiring pattern can be simultaneously formed by a single photolithography technique. Further, the production method of the present invention (claim
According to 2 ), since an etching step is not required, an etching residue does not occur on the side surface of the wiring pattern, and it is possible to prevent defects from occurring in a later step, thereby improving the manufacturing yield. And reliability is improved. Further, the control when forming the dummy wiring pattern is facilitated, and the manufacturing can be easily performed.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a reference example of the present invention in the order of manufacturing steps.

FIG. 2 is a cross-sectional view showing a second reference example of the present invention in the order of manufacturing steps.

FIG. 3 is a sectional view showing the first embodiment of the present invention in the order of manufacturing steps.

FIG. 4 is a sectional view showing a second embodiment of the present invention in the order of manufacturing steps.

FIG. 5 is a sectional view showing a third embodiment of the present invention in the order of manufacturing steps.

FIG. 6 is a sectional view showing an example of a conventional structure in the order of manufacturing steps.

FIG. 7 is a cross-sectional view showing another example of the conventional structure in the order of manufacturing steps.

[Explanation of symbols]

 1, 11, 21, 31 Semiconductor substrate 3, 13, 33 Wiring pattern 4, 15 Coating film 6, 16, 36 Dummy wiring pattern 23 Metal film (aluminum film) 24 Alumina layer 27 Wiring pattern 28 Dummy wiring pattern 35 LPD oxide film

 ──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-2-240946 (JP, A) JP-A-4-218918 (JP, A) JP-A-4-287326 (JP, A) JP-A-2- 262338 (JP, A) JP-A-6-5594 (JP, A) JP-A-5-347365 (JP, A)

Claims (2)

(57) [Claims] A method of forming a dummy wiring pattern between wiring patterns and flattening an interlayer film formed on these wiring patterns, the method comprising the steps of: forming an aluminum film on a semiconductor substrate; Forming an alumina layer by oxidizing at least a part of a surface area of at least a part of the plane area of the aluminum film, patterning the aluminum film, and forming a wiring pattern made of aluminum and a dummy made of alumina. A method for manufacturing a semiconductor device, comprising a step of forming a wiring pattern. 2. A dummy wiring pattern is provided between wiring patterns.
To form an interlayer film formed on these wiring patterns.
In a method of manufacturing a semiconductor device in which a semiconductor device is supported, a step of selectively patterning a conductive film on a semiconductor substrate to form a wiring pattern, a step of forming a mask film having an opening between the wiring patterns, Forming an insulating film in the opening of the film by a liquid phase epitaxy method, and forming the insulating film left after removing the mask film as a dummy wiring pattern. Method.