JP2587940B2 - IC test system - Google Patents

Description

The present invention relates to an IC test system having a distributed architecture having a hierarchical structure.

[Prior Art] FIG. 3 is a diagram showing a configuration example of a conventional IC test system. In the IC test system, a program in which a test sequence for testing a device under test is described is stored in a storage device (not shown), and the central processing unit 11 reads out the test program from the storage device and sequentially executes the test program. The central processing unit 11 controls all test operations for testing a semiconductor memory device, for example.

Hardware modules 13A, 13B, 13C to 13N are connected to the central processing unit 11 via control lines 12, and control signals output as the central processing unit 11 decodes and executes the test program are controlled. These hardware modules 13A, 13B, 13C to 13N are supplied through a line 12.

The control signal is, for example, a control signal for supplying a DC signal of 5.25 V to a predetermined input terminal of the device under test, and when the control signal is supplied, for example, the hardware module 13A operates at a 5.25 V Is supplied to a designated input terminal of the device under test.

The control signal output from the central processing unit 11 is, for example, a control signal for instructing measurement of a signal, and the hardware module 13B for measuring a DC voltage, when supplied with this control signal, It is connected to the designated output terminal of the device and measures its signal voltage.

The hardware modules 13A, 13B, 13C to 13N may incorporate the microprocessor 14. Even if a large number of logic elements are required when a test circuit is assembled using only general-purpose logic elements, the circuit board can be made compact by assembling many parts of the logic circuit with the microprocessor 14. In this case, the microprocessor 14 is merely a substitute for a logic element, performs only a predetermined sequence control, and is not generally used in a manner that requires a complicated judgment function.

"Problems to be Solved by the Invention" The central processing unit decodes and executes a program, that is, outputs a control signal for performing a test of the device under test to a hardware module and the like, and a signal output by the device under test. It is necessary to perform all kinds of arithmetic and control required for the operation of the IC test system, such as measurement of the measurement and judgment of the quality of the measurement result.

Therefore, the arithmetic processing time required by the central processing unit becomes longer, and the test speed of the test system cannot be easily increased. In particular, a test such as a DC test for a current signal input-voltage signal output characteristic and a voltage signal input-current signal output characteristic requires a large number of input / output terminals of a device under test, and high-speed test control is desired.

Further, depending on the test content for the device under test, it may be necessary to supply a time-aligned signal from each hardware module as a test signal. Moreover, very accurate simultaneous control or sequential control timing may be required. In such a case, if the central processing unit handles all of the timing relationships, it may take time for the processing, and may not be able to keep up in time.

Also, when an emergency occurs in one hardware module, the other hardware modules must also immediately respond appropriately, and the central processing unit controls each hardware module for a response operation for that. It's time-consuming and too slow.

"Means for Solving the Problem" The IC test system of the present invention includes an instruction for setting a control signal to an input terminal of a device under test and an execution instruction such as a measurement instruction for an output signal from an output terminal of the device under test. A higher-level processing unit that reads a test program recorded in units of lines and sends the read instruction to a plurality of lower-level processing units, and is required to execute the instructions sent from the higher-level processing unit. A plurality of lower processing units that perform various controls and processes on a plurality of hardware modules by reading a program corresponding to the instruction; and a device under test according to the controls and processes from the lower processing units. A plurality of hardware modules for connecting a test signal to the device or measuring an output signal of the device under test, a synchronization bus is provided, and The apparatus includes a synchronization command output circuit that outputs a synchronization command of one predetermined logical value to the synchronization bus, and a synchronization command reception circuit that receives a state of the synchronization bus. , Control is performed in synchronization among the plurality of lower processing units.

According to the configuration of the present invention, the higher-level processing device controls the execution of the test program on a line-by-line basis, and the actual decoding and execution of the program line are distributed by a plurality of dedicated processing devices. Done.

Further, according to the configuration of the present invention, it is possible to perform synchronized control between the lower processing units by a signal via the synchronization bus without passing through the upper processing unit.

Embodiment FIG. 1 is a block diagram showing a configuration example of an IC test system according to the present invention. In particular, the DC test is configured to be able to be executed at high speed, and this IC test system includes a plurality of processing devices having a hierarchical structure. That is, the IC test system of the present invention is connected to a higher-level processing device 21 for controlling the execution of a test program stored in a storage device (not shown) via the control bus 22. A plurality of lower processing units 23A, 23B, 23C to 23N that actually execute the program lines under the control of the higher processing unit 21, and these lower processing units 23A,
Hardware layers 25A, 25B, 25C to 25N controlled through control lines 24 to 23B, 23C to 23N are configured hierarchically.

That is, in the test program for testing the device under test, the test procedure is described in units of rows, and the host processor 21 sequentially reads the test program from the storage unit in units of rows, and determines whether or not to execute the read program line. Control.

The upper processing device 21 includes a plurality of lower processing devices 23A,
23B, 23C to 23N are connected, and the upper processing unit 21 determines whether to execute the read program line while checking the test state of the device under test, and the actual execution of the program line determined to be executed is Each processing device 23A, 23 connected to the lower level
B, 23C to 23N.

Each of the lower processing units 23A, 23B, 23C to 23N is a dedicated processing unit suitable for controlling a test signal for the device under test, and a hardware module connected thereto.
Machine language suitable for controlling 25A, 25B, 25C to 25N is defined as a programming language. Each lower processing unit 23A, 23B, 23C to 23N
When the execution of the program line is commissioned by the upper-level processing device 21, the device decodes the program line and starts executing the program line. In other words, each of the processing devices 23A, 23B, 23C to 23N holds a control program in which a procedure for inputting and outputting a test signal to and from the device under test is stored in a storage device (not shown). The control program is read out according to the result of decoding the program line, and a procedure for input / output control of signals described in the program line is executed.

The lower processing units 23A, 23B, 23C to 23N are respectively connected to hardware modules 25A, 25B, 25C to 25N.
Has a convenient command language system to access any of these, or to change the test status (terminal connection or measuring instrument status). It is configured so that a processing speed several tens of times higher than performing the same processing directly with the instruction word system is obtained.

Further, each of the lower processing units 23A, 23B, 23C to 23N not only executes the program line commissioned to be executed by the upper processing unit 21 as it is, but also decodes the program line and processes the decoding result. Check the functional conditions for which information is given in advance to the device under test, such as the minimum clock width, input conditions, timing relations, or prohibition conditions, etc., and give an incorrect input signal. The program is programmed to output a test signal to the device under test or to control the measurement of the output signal while determining not to fall into a signal state that may cause damage to the device.

For example, when a signal is given to a certain input terminal as an instruction described in a program line in order to set the next input / output state Q2 at a certain input / output state Q1 of the device under test, the device under test is placed. It may fall into the prohibited input / output state Q3 that must not be done. By executing the program line, the processing device 23 checks whether the device under test enters such a prohibited state Q3, determines a control procedure to avoid the prohibited state Q3, and executes the program line. I do. For example,
The processor 23 determines the control procedure such that the input / output state of the device under test reaches the input / output state Q2 described in the program line from the state Q1 through the state Q4, the state Q5,... And executes the program line. .

Further, the processing device 23 takes in the measurement signal via the hardware module 25, but can also perform, for example, a linear correction or a logarithmic curve correction of the measured signal as necessary, and the obtained measurement data is The data is compared with a reference value, a threshold value, or the like, and the quality is determined, and the measured data and the determination result are stored in the data area of the storage device.

The hardware modules 25A, 25B, 25C to 25N are supplied with control signals accompanying the execution of the program lines of the lower processing units 23A, 23B, 23C to 23N, and supply test signals to designated input terminals of the device under test. It can output or measure a signal from a designated output terminal of the device under test.

The hardware modules 25A, 25B, 25C to 25N may include a microprocessor 26. The microprocessor 26 is a general-purpose processor, not for performing complicated judgment processing, but for controlling the input and output of signals to and from the device under test in accordance with instructions from the processing device 23.

Further, in the present invention, each of the lower processing units 23A, 23B, 23C to 2C
The 3N is configured so that the lower processing units 23A, 23B, 23
A synchronization bus 27 is provided between C and 23N. This synchronization bus
27, it is possible to directly exchange synchronization commands among the lower processing units 23A, 23B, 23C to 23N, without waiting for the synchronization control processing by the upper processing unit 21. Synchronous processing between the devices 23A, 23B, 23C to 23N can be performed accurately and quickly.

FIG. 2 is a diagram showing a main part of an embodiment of the present invention. The IC test system according to the present invention is provided with a synchronization bus 27, and each of the processing units 23A, 23B to 23N is provided with a synchronization command input / output terminal 31A, 31B to 31N, respectively. The synchronization bus 27 is connected to 31B to 31N.
And the operation units 32A, 32B to 32N of the respective processing devices 23A, 23B to 23N
Are the synchronization signal input / output terminals 31A, 31B to 31N, the synchronization command output circuits 33A, 33B to 33N, and the synchronization command reception circuits 34A, 34B to 3N.
Connected via 4N.

In this embodiment, each synchronization command output circuit 33A, 33B to 33N
RS flip-flop circuits 35A, 35B to 35N and line driver
36A, 36B to 36N. That is, the synchronization request signals 37A, 37B to 37N of the operation units 32A, 32B to 32N are supplied to the set terminals S of the RS flip-flop circuits 35A, 35B to 35N, respectively. The signal output terminals 38A, 38B to 38N of the RS flip-flop circuits 35A, 35B to 35N are synchronized instruction input / output terminals 31A, 31B to 3N via sign inversion line drivers 36A, 36B to 36N, respectively.
Connected to 1N.

Further, in this embodiment, each of the synchronization command receiving circuits 34A, 34B to 3
4N is constituted by a line receiver, and in this example, the signals given from the synchronization command input / output terminals 31A, 31B to 31N are inverted in sign in this example and supplied to the operation units 32A, 32B to 32N.

In the above configuration, of the lower processing devices 23A, 23B to 23N, for example, when the first processing device 23A decodes a program line given from the upper Control signals and other lower processing units 23B-2
In some cases, it is described that the control signal being processed by the 3N is output at the same timing. In this case,
The arithmetic unit 32A of the lower processing unit 23A sends the synchronization request signal 37A with the RS
The flip-flop circuit 35A is set, and a request for synchronization processing is made to the other lower processing units 23B to 23N.

The output of the RS flip-flop circuit 35A changes to an H-level signal, the H-level signal is inverted by the line driver 36A, and the inverted L-level signal is provided to the synchronization command receiving circuit 34A of the processing device 23A itself. At the same time, it is output from the synchronization command input / output terminal 31A to the synchronization bus 27. This L
The level signal is sent to each lower processing unit through the synchronization bus 27.
The synchronization signal is transmitted to the synchronization signal input / output terminals 31B to 31N of 23B to 23N and received by the respective synchronization command receiving circuits 34B to 34N. The L-level signal is inverted to an H-level signal by the synchronization command receiving circuits 34A, 34B to 34N, and supplied to the respective operation units 32B to 32N and the processing device 32A that has output the synchronization command. Each operation unit 32A, 32B
32N can detect the arrival of the synchronization command by detecting that the signals from the synchronization command receiving circuits 34A, 34B to 34N change to H level signals.

When the synchronization command is detected, the lower processing device 23A that has output the synchronization command and the other lower processing devices 23B to 23N branch to respective routines for a predetermined synchronization process. Upon completion of the synchronization processing imposed on each of the processing devices 23A, 23B to 23N, the processing devices 23A, 23B to 23N send reset signals 39A, 39B to 39N to the respective synchronization command output circuits 33A, 33B to 33N. RS
The flip-flop circuit 35A is reset by applying a reset signal 39A to a signal reset terminal R, and the signal from the output terminal 38A changes to an L level signal. Therefore, the inverted signal, that is, the signal of the L level, disappears on the synchronization bus 27.

That is, according to the configuration of the present invention, when a certain lower processing device needs to synchronize a test signal processed by itself with a test signal processed by another lower processing device, the synchronization is performed. And the processing device that issued the synchronization request itself receives the synchronization signal and enters the synchronization process, so that all the processing devices 23A, 23B to 23N perform the synchronization process under the same conditions. It is possible to perform the order processing at accurate time intervals as well as the processing of the test operation at the same timing.

On the other hand, although the upper processing unit 21 is not shown in the figure, since the status of each of the lower processing units 23A, 23B, 23C to 23N is constantly monitored, the synchronization control between the lower processing units for the device under test is controlled. The user can know that the processing has been completed, and can start processing for controlling the execution of the next program line.

In the above example, the case where one synchronization bus 27 is provided has been described. However, depending on the type of required synchronization processing or the possibility that synchronous processing requests of different types occur almost simultaneously. , A plurality of synchronization buses 27 can be provided.
In this case, the type of the synchronization process is coded and the synchronization bus
27 may be output.

Also, even if an inconvenience occurs in any of the lower-level processing units, an emergency command can be sent to the processing unit in the same hierarchy through the synchronization bus 27, and accordingly, the abnormal situation can be dealt with without delay. Can be done. That is, when an inconvenience occurs in a certain lower processing apparatus, for example, it may be necessary to temporarily stop the processing. Normally, the lower processing devices 23A, 23B, 23C to 23N in which the inconvenience has occurred interrupt the upper processing device 21 to notify the abnormality, and upon detecting the abnormal interruption, the higher processing device 21
For example, it controls to temporarily suspend the lower processing units 23A, 23B, 23C to 23N. However, the lower processing units 23A, 23B, 23C
If an interrupt for notifying an abnormality is issued from .about.23N and the other lower processing device is stopped by the response control of the upper processing device 21, it may be too late in an emergency.
However, according to the present invention, the synchronization bus 27 is provided between the processing devices 23A, 23B, 23C to 23N in the same hierarchy, so that the processing can be performed immediately and as if only one As described above, it is possible to perform unified emergency processing or synchronous processing.

[Effects of the Invention] As described above, according to the present invention, a higher-level processing device is configured to exclusively control execution of a program line, and actual execution of a program line is performed by a plurality of lower-level processing devices. Control in a hierarchical structure that is distributed in In this way, the processing speed is improved by the distributed architecture, and since the optimal instruction word system is used for each layer, the processing up to output of the control signal becomes very fast, and the test for the device under test can be performed. Can be done at high speed.

Further, according to the configuration of the present invention, since the synchronization bus is provided between the lower processing units, the synchronization processing between the lower processing units can be performed easily and independently of the processing of the upper processing unit. Can be easily taken. Therefore, a plurality of test signals can be supplied to the device under test with a very accurate timing relationship. In addition, even in an emergency, the test system can be immediately suspended or quickly entered a predetermined evacuation state.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing an embodiment of the present invention, FIG. 2 is a circuit configuration diagram showing a main part of the present invention, and FIG. 3 is a diagram showing a configuration example of a conventional IC test system. 11: Central processing unit, 12: Control line, 13: Hardware module, 14: Microprocessor, 21: Host processing unit, 2
2: Control bus, 23: Lower processing unit, 24: Control line, 25: Hardware module, 26: Microprocessor, 27: Synchronization bus, 31: Synchronization command input / output terminal, 32: Operation unit, 33: Synchronization Command output circuit, 34: synchronization command receiving circuit (line receiver), 35: flip-flop circuit, 36: line driver,
37: synchronization request signal, 38: output terminal, 39: reset signal.

Claims (1)

(57) [Claims] 1. A test program in which an instruction for setting a control signal to an input terminal of a device under test and an execution command such as a measurement command for an output signal from an output terminal of the device under test are recorded in units of lines, and read out in units of lines. A high-level processing device that sends the read instruction to a plurality of low-level processing devices; and a control or process required to execute the instruction sent from the high-level processing device. A plurality of lower-level processing units that read and execute the plurality of hardware modules; a test signal is connected to the device under test according to control or processing from the lower-level processing device; A plurality of hardware modules for measuring signals, a synchronization bus is provided, and each of the plurality of lower-level processing devices is a predetermined one of the synchronization buses. A synchronization command output circuit that outputs a synchronization command of a logical value, and a synchronization command reception circuit that receives a state of the synchronization bus. The synchronization command receiving circuit receives a state of the synchronization bus. IC test system characterized by synchronized control.