JPH0546908B2 - - Google Patents

Description

[Detailed Description of the Invention] (Industrial Application Field) The present invention relates to an analog LSI test device, and in particular,
Concerning improvement of pattern generation part.

(Prior art) Conventionally, a pattern signal is given to an IC such as an analog LSI (hereinafter referred to as a device under test), the response output signal is compared with an expected value, and a discrepancy is detected to determine whether the device under test is good or not. Analog to detect
There is an LSI test equipment.

FIG. 3 is a block diagram showing an example of a pattern generator part in such a test apparatus. In the figure, reference numeral 10 denotes an address generator, which is configured to be able to generate addresses using a counter, microprogram, or the like. This address generator 10
When a pattern signal is generated from the pattern memory 20 by specifying an address, the pattern signal is converted into a predetermined output format by the formatter 30, and then output by a driver and a comparator.
It is applied to the device under test 50 via the comparator circuit 40. The resulting response output of the device under test 50 is input to the comparator of the driver/comparator circuit 40. If the response output is within a predetermined range, it is assumed to be normal data and is led to the formatter 30, where the data format is converted and then compared with an expected value, and the comparison result is stored in the fail memory 60.

The expected values are stored in the pattern memory 20, and each expected value related to the previously output pattern data is output to the formatter 30.

The fail memory 60 stores a flag indicating a failure each time a mismatched comparison result in which the measured data does not match the expected value is detected, and also stores the pattern data generated at that time and the address storing the pattern data. They are beginning to memorize them at the same time. Therefore, this fail memory 6
By reading the contents of 0, it is possible to know the defective address and the pattern data output at that time.

Further, in order to perform the test under conditions according to the comparison results, the address generator 10 generates addresses by referring to the comparison results of the fail memory 60, that is, pass/fail.

(Problem to be solved by the invention) Some recent devices under test are equipped with more advanced intelligent functions within the same device, and at the same time have a configuration in which digital circuits and analog circuits coexist. It has become necessary to send and receive signals to and from a device under test while monitoring its internal state.

However, the conventional device as described above has the following problems.

Describing patterns and expected values is complicated. Even state control patterns that are not directly related to the generation of test patterns must be described.

The number of data channels input and output via the driver/comparator circuit increases.

Depending on the device, the fail memory flag must mean stopping, and the desired effect may not be obtained.

The number of device states required for testing is increasing year by year, and the above conditions are becoming more severe.

In view of these points, it is an object of the present invention to eliminate the need to increase the number of channels even if the number of states of the device under test increases, and to detect and judge the state of the device under test separately from determining the fail memory flag. By doing this, it is possible to select the pattern data that should be generated, and a flag that can determine the device status is prepared separately from the fail memory flag, making it possible to write pattern generation algorithms as easily as in a normal computer. The purpose of the present invention is to provide a pattern generator for IC testing.

In order to achieve such an objective, the present invention, in addition to the configuration of a conventional IC test pattern generator, provides a path that is separate from the path that takes in the response output, and generates a pattern according to the internal state of the device under test. A clutch means for detecting a status signal output from the test device itself, and an address control circuit for controlling the address of the pattern memory when generating pattern data based on the flag from the fail memory and the status signal from the latch means. It is characterized by the following:

(Example) The present invention will be explained in detail below using the drawings. FIG. 1 is a diagram showing the configuration of essential parts of an embodiment of an IC test pattern generator according to the present invention. In the figure, parts equivalent to those in FIG. 3 are designated by the same reference numerals, and their explanation will be omitted. 80 is a register that latches the device state of the device under test 50. In addition,
The device under test 50 here has two states (operation modes), and the device under test itself outputs state signals of low level (level 0) and high level (level 1) representing the state. This is an example of something that would happen.

A status signal of the device 50 is applied from the device under test 50 to the register 80 via a buffer (or a comparator in some cases) 70. The timing of the latch depends on the applied clock CLK. The output of this register 80 can be used by assigning a simple conditional branch instruction and an instruction that does not update the address of the pattern memory 20 until the conditions are met.

90 is an address control circuit, which is a fail memory 6
The address given to the address generator 10 is controlled according to the flag outputted by 0 and the output of the register 80.

The operation in such a configuration will be explained next. As shown in FIG. 2, pattern data is output from the pattern memory 20 in accordance with the address generated by the address generator 10 every clock.

Note that when the status signal of the device under test 50 is level 0, the pattern data P ₁ , P ₂ , . . .
, at level 1, pattern data E ₁ , E ₂ ,
... is given to the device under test 50.

On the other hand, the address control circuit 90 refers to the status signal via the register 80 during a pattern generation cycle and outputs an address corresponding to pattern data to be generated in the next pattern generation cycle. This address is input to address generator 10, but address generator 10 does not update the address until the next clock arrives.

Now, the output pattern data is transmitted to the formatter 30 and the driver/comparator circuit 40.
The signal is input to the device under test 50 via. Thereafter, a similar conventional test based on the flag in the fail memory 60 and a test branching according to the status signal, which is a feature of the present application, are performed as appropriate.

For example, as shown in FIG. 2, pattern data P ₁ is sent from the pattern memory 20 by clock T ₁ input.
is output, the response output from the device under test 50 that has received the pattern data is normal, a flag indicating normality is stored in the fail memory 60, and the status signal of the device is at a level as shown in FIG. Suppose it is 0.

If the register 80 latches the input signal at the falling edge of the clock, the status signal is latched at the falling edge of the clock _T1 . The latched state signal (level 0 signal) is applied to address control circuit 90. The status signal is now level 0.
In this case, the next pattern data (P ₂ ) is generated according to only the flag from the fail memory 60 as in the conventional case.
If the address control circuit 90 is to output
From there, an address corresponding to pattern data _P2 is given to address generator 10. Address generator 10 updates the address with the next clock (T ₂ ) input. As a result, pattern data _P2 is generated from the pattern memory 20.

Next, the pattern data P ₂ is transferred to the device under test 5.
When the state of the device changes and the status signal becomes level 1, level 1 is latched to level 80 at the falling edge of clock _T2 .
The latch output is input to address control circuit 90. The address control circuit 90 outputs branch destination addresses corresponding to the pattern data E ₁ , E ₂ , . . . when the status signal is at level 1. The address generator 10 updates its output (address) with the next clock (T ₃ ) input, thereby generating the pattern data from the pattern memory 20 as shown in FIG.
E ₁ is output.

While the pattern data E ₁ is being applied to the device under test 50, if the status signal remains at level 1 as shown in FIG. 2C, the address control circuit 90 generates the next pattern data E ₂ by the same operation. Outputs the address to be used. As a result, pattern data _E2 is applied to the device under test 50 during the next clock _T4 period.

As described above, predetermined pattern data can be automatically given to the device under test based on the status signal of the device under test 50.

(Effects of the Invention) According to the present invention configured as described above, the following effects are exhibited.

There is no longer a need to arrange patterns in memory and write the status of the device under test. That is,
Since the address control circuit determines the state of the device and generates a predetermined address, it is no longer necessary to write patterns that are not directly related to pattern generation.

The device status signal is taken out directly from another outlet of the device under test, so there is no need to increase the number of channels taken in by the driver/comparator circuit.

In addition to the fail memory flag, a signal representing the state of the device under test is referenced, which simplifies pattern programming because pattern generation and error detection can be considered separately.

[Brief explanation of drawings]

Fig. 1 is a main part configuration diagram showing an embodiment of an IC test pattern generator according to the present invention, Fig. 2 is a time chart for explaining the operation, and Fig. 3 is an example of a conventional IC test device. FIG. DESCRIPTION OF SYMBOLS 10...Address generator, 20...Pattern memory, 30...Formatter, 40...Driver/comparator circuit, 50...Device under test, 60...Fail memory, 70...Buffer, 80...Register, 90... ...Address control circuit.

Claims (1)

[Claims] 1. Applying pattern data generated from a pattern memory to a device under test via a formatter and a driver/comparator circuit, and checking whether the resulting response output from the device under test is within a predetermined range. The response output determined by the driver/comparator circuit and within a predetermined range is further compared with the expected value in the formatter, the comparison result is stored in the fail memory in the form of a flag indicating pass/fail, and then the output is determined based on the flag in the fail memory. Next, in an IC test pattern generator configured to determine an address corresponding to pattern data generated from a pattern memory, a path is provided separately from the path for receiving the response output, and a path is provided that is connected to the internal state of the device under test. a latch means for detecting a status signal output from the device under test itself in response to the failure; and controlling an address of the pattern memory when generating pattern data based on the flag from the fail memory and the status signal from the latch means. 1. A pattern generation device for IC testing, comprising an address control circuit that generates predetermined pattern data according to the state of a device under test.