JP2586011B2 - Voltage generation circuit - Google Patents
Voltage generation circuitInfo
- Publication number
- JP2586011B2 JP2586011B2 JP61202507A JP20250786A JP2586011B2 JP 2586011 B2 JP2586011 B2 JP 2586011B2 JP 61202507 A JP61202507 A JP 61202507A JP 20250786 A JP20250786 A JP 20250786A JP 2586011 B2 JP2586011 B2 JP 2586011B2
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- differential input
- reference voltage
- temperature coefficient
- input transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Amplifiers (AREA)
- Control Of Electrical Variables (AREA)
- Continuous-Control Power Sources That Use Transistors (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、電圧発生回路に関し、特にLCD駆動用電圧
等、任意の温度係数を必要とする電圧発生回路に関する
ものである。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a voltage generating circuit, and more particularly to a voltage generating circuit that requires an arbitrary temperature coefficient, such as an LCD driving voltage.
電圧発生回路に於いて、従来は第３図に示すように、
内部基準電圧（Vriと表わす）を、増巾器を用いて、ｎ
倍し、外部基準電圧（Vroと表わす）を発生する回路が
知られている。Conventionally, in a voltage generating circuit, as shown in FIG.
The internal reference voltage (denoted as Vri) is calculated by using an amplifier.
A circuit that generates an external reference voltage (referred to as Vro) by multiplying the external reference voltage is known.
しかしながら、従来技術では、外部基準電圧の温度係
数は、内部基準電圧の温度係数と同一であり、内部基準
電圧は、一般にバンドギヤツプ方式等、物理定数を用
い、安定な出力電圧を得る方式が主流であり、物理定数
のため、その温度計数も製造プロセスにより一義的に定
まる。任意の温度係数を得るためには、第４図に示すよ
うに、負の温度係数をもつバンドギヤツプ電圧VBEと、
正の温度係数をもつ拡散抵抗RDによる電圧降下VRDとを
組合せて内部基準電圧Vriを発生していた。ところで、
低消費電流から、半導体チツプ上の専有面積を小さくし
ようとすると、拡散抵抗は、低濃度不純物拡散により作
る必要があり、その抵抗値の製造バラツキは大きくなら
ざるを得ない。そのため、内部基準電圧値及び、その温
度係数もバラツキが大きくなつてしまうという問題点を
有する。However, in the prior art, the temperature coefficient of the external reference voltage is the same as the temperature coefficient of the internal reference voltage, and the internal reference voltage generally uses a physical constant such as a bandgap method to obtain a stable output voltage. Because of the physical constant, its temperature coefficient is also uniquely determined by the manufacturing process. To obtain an arbitrary temperature coefficient, as shown in FIG. 4, a bandgap voltage V BE having a negative temperature coefficient,
The internal reference voltage Vri was generated by combining the voltage drop V RD by diffusion resistance RD with a positive temperature coefficient. by the way,
In order to reduce the occupied area on the semiconductor chip due to low current consumption, the diffused resistor must be formed by low-concentration impurity diffusion, and the variation in the resistance value must be increased. Therefore, there is a problem that the internal reference voltage value and its temperature coefficient also vary greatly.
本発明はこのような問題点を解決するもので、その目
的とするところは、バラツキの少ない、任意の温度係数
を有し、低消費電流かつ広い動作電流電圧範囲を有し、
半導体チツプ上の専有面積の小さい、基準電圧発生回路
を提供することである。The present invention solves such a problem, and the object is to have an arbitrary temperature coefficient with little variation, a low current consumption and a wide operating current voltage range,
An object of the present invention is to provide a reference voltage generating circuit having a small occupied area on a semiconductor chip.
本発明の電圧発生回路は、基準電圧を発生する基準電
圧発生回路と、第１の差動入力トランジスタ、第２の差
動入力トランジスタを有し、前記第１及び第２の差動入
力トランジスタのゲート端子に入力された電圧に基づい
て出力電圧を発生する演算増幅回路とを備え、前記第１
の差動トランジスタのゲート端子には前記基準電圧が入
力され、前記第２の差動入力トランジスタのゲート端子
には前記出力電圧が帰還入力される電圧発生回路におい
て、前記基準電圧発生回路は温度係数を有し、前記第１
の差動入力トランジスタのしきい値電圧と前記第２の差
動入力トランジスタのしきい値電圧とは、所望の前記出
力電圧の温度係数に応じて異なっていることを特徴とす
る。A voltage generation circuit according to the present invention includes a reference voltage generation circuit that generates a reference voltage, a first differential input transistor, and a second differential input transistor. An operational amplifier circuit for generating an output voltage based on a voltage input to a gate terminal;
The reference voltage is input to a gate terminal of the differential transistor of the second differential input transistor, and the output voltage is fed back to the gate terminal of the second differential input transistor. And the first
The threshold voltage of the differential input transistor and the threshold voltage of the second differential input transistor are different according to a desired temperature coefficient of the output voltage.
本発明は、以上の構成を有することにより、実施例に
詳細を示すとおり、従来比例関係にあつた内部基準電圧
値と外部基準電圧値の間に、加減算の項を挿入出来、任
意の温度特性を有する基準電圧を発生出来る。As described in detail in the embodiments, the present invention allows the addition of a term of addition and subtraction between the internal reference voltage value and the external reference voltage value, which have been conventionally in a proportional relationship, as described in detail in the embodiment. Can be generated.
以下本発明の電圧発生回路の一実施例を第２図に示
す。M1は、デプレシヨンＰ型MOSFETで電流源動作を行な
う。この電流値をカレント・ミラー回路により分配する
ことにより、広い電流電圧範囲にわたり、回路が定電流
動作をし、安定かつ定消費電流を実現している。内部基
準電圧Vriは、トランジスタQ1,Q2のVBEにより発生し、
定電流動作のため、広い電源電圧範囲にわたり、高レベ
ル電源電圧VDDとVriとの電位差は一定に保たれる。この
内部基準電圧発生器１の出力Vriを演算増巾器２の差動
入力トランジスタM2に入力し、もう片側の差動入力トラ
ンジスタM3に帰還電圧VFBを入力する。差動出力を、出
力バツフアトランジスタM4に与え、M4の出力（Vro）
を、帰還抵抗R1,R2により分割し、帰還電圧VFBとし、差
動入力部に帰している。ここで差動入力部にオフセツト
電圧を設定すると、以下に示すように任意の温度係数を
もつた基準電圧Vroを発生することが出来る。FIG. 2 shows an embodiment of the voltage generating circuit according to the present invention. M1 performs a current source operation with a depletion P-type MOSFET. By distributing this current value by the current mirror circuit, the circuit performs a constant current operation over a wide current voltage range, thereby realizing stable and constant current consumption. The internal reference voltage Vri is generated by V BE of the transistors Q 1 and Q 2 ,
Due to the constant current operation, the potential difference between the high-level power supply voltages VDD and Vri is kept constant over a wide power supply voltage range. The output Vri of the internal reference voltage generator 1 is input to the differential input transistor M2 of the operational amplifier 2, and the feedback voltage VFB is input to the other differential input transistor M3. The differential output is given to the output buffer transistor M4, and the output of M4 (Vro)
Is divided by the feedback resistors R 1 and R 2 to obtain a feedback voltage VFB , which is returned to the differential input unit. When an offset voltage is set in the differential input section, a reference voltage Vro having an arbitrary temperature coefficient can be generated as shown below.
Vri（Ｔ）＋VOF＝VFB（Ｔ）＝ｎ・Vro（Ｔ）……（１） ここでVOF≒オフセツト電圧 Vri（０）：基準温度におけるVri Vro（０）：基準温度におけるVro （１）式を温度Ｔで偏微分すると となる。Vri (T) + V OF = V FB (T) = n · Vro (T) (1) where V OF ≒ offset voltage Vri (0): Vri at the reference temperature Vro (0): Vro at the reference temperature Becomes
すなわち、Vroの温度係数 は、Vriの温度係数 に、１対１に比例せず、オフセツト電圧VOFにより任意
に設定可能となる。本実施例では、演算増巾器の差動入
力部にMOSFETを用いているため、オフセツト電圧はチヤ
ネル・ドープ工程等により片側のMOSFETのスレツシヨル
ド電圧Vthを変えることにより、差動入力部MOFFETのVth
差として、容易にかつ、任意の値に設定することが出来
る。That is, the temperature coefficient of Vro Is the Vri temperature coefficient To not proportional to the one-to-one, and can be arbitrarily set by the offset voltage V OF. In this embodiment, since the MOSFET is used for the differential input section of the operational amplifier, the offset voltage is changed by changing the threshold voltage Vth of the MOSFET on one side by a channel doping process or the like, thereby obtaining the Vth of the differential input section MOFFET.
The difference can be set easily and to any value.
以上のように、本発明の電圧発生回路は、所望の温度
係数を有する電圧を発生できるという顕著な効果を有す
る。As described above, the voltage generation circuit of the present invention has a remarkable effect that a voltage having a desired temperature coefficient can be generated.
第１図は本発明の構成を明示する図、第２図は本発明の
一実施例の回路図、第３図は従来の構成図、第４図は従
来の内部基準電圧発生回路の図。 １……内部基準電圧発生器 ２……演算増巾器（入力オフセツト電圧付） ３……演算増巾器FIG. 1 is a diagram clearly showing the configuration of the present invention, FIG. 2 is a circuit diagram of one embodiment of the present invention, FIG. 3 is a conventional configuration diagram, and FIG. 4 is a diagram of a conventional internal reference voltage generating circuit. 1 Internal reference voltage generator 2 Operational amplifier (with input offset voltage) 3 Operational amplifier
Claims (1)
スタを有し、前記第１及び第２の差動入力トランジスタ
のゲート端子に入力された電圧に基づいて出力電圧を発
生する演算増幅回路とを備え、 前記第１の差動入力トランジスタのゲート端子には前記
基準電圧が入力され、前記第２の差動入力トランジスタ
のゲート端子には前記出力電圧が帰還入力される電圧発
生回路において、 前記基準電圧発生回路は温度係数を有し、 前記第１の差動入力トランジスタのしきい値電圧と前記
第２の差動入力トランジスタのしきい値電圧とは、所望
の前記出力電圧の温度係数に応じて異なっていることを
特徴とする電圧発生回路。A reference voltage generating circuit for generating a reference voltage; a first differential input transistor and a second differential input transistor; and a gate terminal of the first and second differential input transistors. An operational amplifier circuit for generating an output voltage based on the input voltage, wherein the reference voltage is input to a gate terminal of the first differential input transistor, and a gate terminal of the second differential input transistor Wherein the reference voltage generation circuit has a temperature coefficient, and a threshold voltage of the first differential input transistor and a threshold voltage of the second differential input transistor. A voltage generating circuit, which differs from a threshold voltage according to a desired temperature coefficient of the output voltage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61202507A JP2586011B2 (en) | 1986-08-28 | 1986-08-28 | Voltage generation circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61202507A JP2586011B2 (en) | 1986-08-28 | 1986-08-28 | Voltage generation circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6356713A JPS6356713A (en) | 1988-03-11 |
| JP2586011B2 true JP2586011B2 (en) | 1997-02-26 |
Family
ID=16458627
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61202507A Expired - Lifetime JP2586011B2 (en) | 1986-08-28 | 1986-08-28 | Voltage generation circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2586011B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4830325B2 (en) * | 2005-03-23 | 2011-12-07 | ミツミ電機株式会社 | Semiconductor device |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5822425A (en) * | 1981-08-04 | 1983-02-09 | Toshiba Corp | Reference voltage generating circuit |
| JPH0618012B2 (en) * | 1983-01-25 | 1994-03-09 | セイコーエプソン株式会社 | Constant voltage circuit |
| JPS61138318A (en) * | 1984-12-10 | 1986-06-25 | Nec Corp | Reference voltage generating circuit |
-
1986
- 1986-08-28 JP JP61202507A patent/JP2586011B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6356713A (en) | 1988-03-11 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |