JP2023531485A - Three-dimensional memory and its control method - Google Patents

Abstract

The present disclosure relates to a three-dimensional memory and its control method. The three-dimensional memory comprises a first deck and a second deck stacked vertically on a substrate, the first deck and the second deck each comprising a plurality of memory strings, each memory string comprising a plurality of memory cells, the plurality of memory cells comprising a first portion and a second portion, the diameter of the channel structure corresponding to the first portion of the memory cells being smaller than the diameter of the channel structure corresponding to the second portion of the memory cells. The method is to read the selection memory cells in the first and / / or the second deck, and to apply a pass voltage to a non -selected memory cell other than the selection memory cells in the first and second decks, and the first pass voltage is lower than the second pass voltage. Included to the first non -selected memory cell in the first portion, and the second pass voltage is added and applied to the second non -selected memory cell.

Description

FIELD OF THE DISCLOSURE The present disclosure relates to the field of integrated circuit manufacturing, and more particularly to three-dimensional memories and their control methods.

In order to overcome the limitations of the two-dimensional memory device, the industry has developed and produced a large-scale memory device having a three-dimensional (3D) structure in which memory cells are three-dimensionally arranged on a substrate to increase the integration density. 3D NAND flash is a three-dimensional storage element. As the number of stacked layers increases, the channel hole gradually becomes deeper. Since the upper opening of the channel hole is larger than its lower opening, the deeper the channel hole, the greater the difference between the upper opening and the lower opening of the channel hole. When a read operation is performed on a three-dimensional storage element, and the same pass voltage is applied to each memory cell on a memory string formed by the same channel hole, if the opening of the channel hole in which the memory cell is located is relatively small, the pass voltage will lead to a higher electric field strength in the memory cell, resulting in read disturb to the memory cell after many times of reading.

A technical problem to be solved by the present disclosure is to provide a three-dimensional memory and its control method that reduce read disturb.

To solve the above technical problem, the technical solution adopted by the present disclosure is a control method for a three-dimensional storage element, in which a three-dimensional memory comprises a first deck and a second deck stacked vertically on a substrate, each of the first deck and the second deck comprising a plurality of memory strings, each memory string comprising a plurality of memory cells, the plurality of memory cells comprising a first portion and a second portion corresponding to the first portion of the memory cell. the diameter of the channel structure corresponding to the second portion of the memory cell is smaller than the diameter of the channel structure corresponding to the second portion of the memory cell, the method is performing a read operation on the selected memory cells in the first deck and/or the second deck; and applying a pass voltage to unselected memory cells other than the selected memory cells in the first deck and the second deck, wherein the pass voltage includes a first pass voltage and a second pass voltage, the first pass voltage being lower than the second pass voltage, and the first pass voltage being the first pass voltage. applying the second pass voltage to the first unselected memory cells of the portion and applying the second pass voltage to the second unselected memory cells of the second portion.

In an embodiment of the present disclosure, the method further comprises performing a program verify operation on the selected memory cell and applying a pass voltage to unselected memory cells other than the selected memory cell in the first deck and the second deck, wherein a second pass voltage is applied to the second unselected memory cell, the applied pass voltage is determined according to the state of the first unselected memory cell, and if the first unselected memory cell is in a programmed state, the first pass voltage is applied to the first unselected memory cell; applying a second pass voltage to the first unselected memory cell if the unselected memory cell is in an erased state.

In certain embodiments of the present disclosure, memory cells in a memory string are coupled to corresponding word lines through which pass voltages are applied to the memory cells.

In certain embodiments of the present disclosure, when a read operation is performed on a selected memory cell, a read voltage is applied to the word line of the selected memory cell.

In certain embodiments of the present disclosure, when a program verify operation is performed on a selected memory cell, a program verify voltage is applied to the word line of the selected memory cell.

In certain embodiments of the present disclosure, each memory cell is at a corresponding cell depth in a memory string, and programming operations are performed on a page of memory cells at the same cell depth through word lines layer by layer in the direction of expansion of the channel structure of the memory string.

To solve the above technical problem, the present disclosure further proposes a three-dimensional memory, which comprises a memory cell array comprising a first deck and a second deck stacked vertically on a substrate, the first deck and the second deck each comprising a plurality of memory strings, each memory string extending vertically over the substrate and comprising a plurality of memory cells vertically arranged in series connection, a first portion and a second portion. a plurality of memory cells, wherein a diameter of a channel structure in a first portion of the memory cell is smaller than a diameter of a channel structure in a second portion of the memory cell; and a controller configured to send a control signal to the voltage controller when a read operation is performed on the selected memory cell, the controller applying a pass voltage including a first pass voltage and a second pass voltage to the unselected memory cells in response to the control signal, wherein the first pass voltage is lower than the second pass voltage and the first non-selected portion of the first portion. a controller, wherein a first pass voltage is applied to selected memory cells and a second pass voltage is applied to second unselected memory cells of the second portion.

In certain embodiments of the present disclosure, the controller is further configured to send a control signal to the voltage controller when a program verify operation is performed on the selected memory cell, wherein the voltage controller is responsive to the control signal to apply a second pass voltage to the second unselected memory cell, apply the first pass voltage to the first unselected memory cell if the first unselected memory cell is in a programmed state, and apply a second pass voltage to the first unselected memory cell if the first unselected memory cell is in an erased state.

In certain embodiments of the present disclosure, the three-dimensional memory further comprises a plurality of word lines, each of which is at the same cell depth and coupled to a page of memory cells, each memory cell being located at a corresponding cell depth in the memory string.

In certain embodiments of the present disclosure, the diameter of the channel structure of the memory string gradually increases from the bottom surface to the top surface of the memory string.

In one embodiment of the present disclosure, the first portion of the memory cells underlies the second portion of the memory cells.

In an embodiment of the present disclosure, the memory string comprises a first memory string and a second memory string stacked in the spreading direction of the channel structure, the diameter of the channel structure of the first memory string gradually increasing from the bottom surface to the top surface of the first memory cell, and the diameter of the channel structure of the second memory string gradually increasing from the bottom surface to the top surface of the second memory string.

In one embodiment of the present disclosure, the diameter of the channel structure at the top surface of the first memory string is larger than the diameter of the channel structure at the bottom surface of the second memory cell.

In one embodiment of the present disclosure, the three-dimensional memory is 3D NAND flash.

According to the three-dimensional memory and its control method of the present disclosure, a first pass voltage lower than the normal pass voltage can be applied to memory cells with relatively small diameter channel structures, thereby reducing read disturb in this portion of the memory cells. Also, during the program verify phase, a relatively low first pass voltage is applied to the memory cell, which is a relatively small opening channel structure, thereby further reducing read disturb in this portion of the memory cell and enhancing the reliability of the three-dimensional memory.

In order to make the previously stated objects, features and advantages of the present disclosure more apparent and comprehensible, specific implementations of the present disclosure will be described in detail below in connection with the drawings.

FIG. 2 is a structural diagram of a portion of a three-dimensional memory with multiple decks; FIG. 4 is a distribution diagram of threshold voltages of memory cells in a three-dimensional memory; FIG. 4 is a distribution diagram of threshold voltages of memory cells in a three-dimensional memory; FIG. 4 is a schematic diagram of the effect of read disturb on E0 margin; 4 is an exemplary flow chart of a method for controlling a three-dimensional memory, according to an embodiment of the present disclosure; FIG. 4 is an implementation schematic diagram of a control method for a three-dimensional memory, according to an embodiment of the present disclosure; FIG. 4 is an implementation schematic diagram of a control method for a three-dimensional memory, according to an embodiment of the present disclosure; FIG. 4 is an implementation schematic diagram of a control method for a three-dimensional memory, according to an embodiment of the present disclosure; FIG. 4 is an implementation schematic diagram of a control method for a three-dimensional memory, according to an embodiment of the present disclosure; FIG. 4 is an effect schematic diagram of a control method of a three-dimensional memory according to an embodiment of the present disclosure; FIG. 4 is an implementation schematic diagram of a control method for a three-dimensional memory, according to an embodiment of the present disclosure; FIG. 4 is an implementation schematic diagram of a control method for a three-dimensional memory, according to an embodiment of the present disclosure; FIG. 4 is an implementation schematic diagram of a control method for a three-dimensional memory, according to an embodiment of the present disclosure; FIG. 4 is an implementation schematic diagram of a control method for a three-dimensional memory, according to an embodiment of the present disclosure; FIG. 3B is a module diagram of a three-dimensional memory, according to an embodiment of the present disclosure; FIG. 3 is a circuit schematic diagram of a memory block that can be used in certain embodiments of the present disclosure;

In order to make the previously stated objects, features and advantages of the present disclosure more apparent and comprehensible, specific implementations of the present disclosure will be described in detail below in connection with the drawings.

The following detailed description sets forth more specific details for a thorough understanding of the present disclosure. However, the disclosure may also be implemented in manners other than those described herein. Accordingly, the present disclosure is not limited to the specific embodiments disclosed below.

As indicated in the present application and claims, terms such as "a," "an," and/or "the" are not specifically intended for singular connotations, but are intended to include plural connotations, with grammatically obvious exceptions. Broadly speaking, the terms "comprise" and "conclude" indicate only that a method or apparatus includes the specifically identified steps and elements, not an exclusive list, and a method or apparatus may include other steps or elements.

When describing embodiments of the present disclosure in detail, cross-sectional views representing device structures are partially enlarged rather than to scale for convenience of illustration, and schematic views are merely exemplary and do not limit the scope of protection of the present disclosure herein. Furthermore, the three-dimensional spatial dimensions of length, width, and depth should be included in the actual fabrication.

Spatial-related terms such as “under,” “below,” “lower,” “beneath,” “above,” “on,” and the like are sometimes used herein for descriptive convenience to describe the relationship of one element or feature to another element or feature as shown in the figures. It will be appreciated that these spatially related terms are terms intended to encompass orientations of the device in use or operation other than as depicted in the figures. For example, when the device in the figures is flipped, the orientation of elements described as being “below,” “under,” or “beneath” other elements or features changes orientation “above” other elements. Thus, the representative terms "below" and "beneath" can include upward and downward directions. The orientation of the device may be in other orientations (rotated 90 degrees or otherwise), and thus spatially related terms as used herein should be interpreted accordingly. It is also understood that when a layer is said to be "between" two layers, it can be the only layer between the two layers, or there can be one or more layers intervening therebetween.

In the context of this application, a structure in which a first feature is said to be "over" a second feature may include embodiments in which the first feature and the second feature are in direct contact, and may also include embodiments in which another feature is formed between the first and second features, such as the first and second features not in direct contact.

Also, it should be noted that the terms "first", "second", etc. used to define the components are merely for convenience of distinguishing the corresponding components. Unless otherwise stated, the terms mentioned above do not have a specific meaning and are therefore not considered to limit the scope of protection of the present application.

As used herein, the term "three-dimensional (3D) memory device" refers to a semiconductor device in which memory cell transistor strings (herein referred to as "memory strings", such as NAND strings) are vertically oriented on a lateral substrate such that the memory strings extend vertically with respect to the substrate. As used herein, the term "perpendicular/perpendicularly" means nominally perpendicular to the sides of the substrate.

As used herein, the term "substrate" refers to a material to which layers of material are subsequently applied. The substrate itself may be patterned. The material applied to the top surface of the substrate may be patterned or left unpatterned. Furthermore, substrates may include a wide variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate may be made of non-conductive material such as glass, plastic, or a sapphire wafer.

As used herein, the term "layer" refers to a portion of material that includes a thickened region. A layer may span the entire underlying or overlying structure, or its extent may be less than the underlying or overlying structure. Further, a layer can be a uniform uninterrupted structure whose thickness is less than the thickness of the uninterrupted structure or a region of non-uniform uninterrupted structure. For example, there may be layers between any pair of horizontal planes between the top and bottom surfaces of the unbroken structure, or between the top and bottom surfaces of the unbroken structure. Layers may extend horizontally, vertically, and/or along tapered surfaces. A substrate can be a layer, can have one or more layers on it, and/or can have one or more layers thereon, above it, and/or below it. A layer can include multiple layers. For example, interconnect layers can include one or more conductor and contact layers (where contacts, interconnect lines, and/or via holes are formed) and one or more insulating layers.

This application uses flow diagrams to illustrate the work performed by the system according to embodiments of the present application. It should be understood that the actions previously mentioned or the actions below do not necessarily have to be performed in sequential order. Alternatively, each step may be processed in reverse order or simultaneously. On the other hand, alternatively, additional work is added to these processes, and alternatively, some one or more steps of the operations are removed from these processes.

FIG. 1 is a structural diagram of part of a three-dimensional memory with multiple decks. Looking at FIG. 1, the three-dimensional memory comprises two decks, a first deck 110 and a second deck 120, respectively. In each deck, a stack structure 111,121 is formed by alternating layers of gate layers and insulating layers, and a channel hole structure 112,121 is formed in the stack structure 111,121. As shown in FIG. 1, in the first deck 110, the opening at the top surface 114 of the channel hole structure 112 is larger than the opening at the bottom surface 113 thereof. In the second deck 120 , the openings at the top surface 124 of the channel hole structure 122 are larger than the openings at the bottom surface 123 . At the interface between the first deck 110 and the second deck 120 , the opening of the channel holes on the bottom surface 113 of the first deck 110 is smaller than the opening of the channel holes on the top surface 124 of the second deck 120 .

In an actual three-dimensional memory structure, the opening of the channel hole gradually becomes smaller from the top surface to the bottom surface of the channel hole in the spreading direction of the channel hole structure. As the number of stacked layers in the stack structure 111, 121 increases, the channel hole structure 112, 122 gradually becomes deeper, and its depth-to-width ratio gradually increases, gradually widening the difference between the opening at the top and the bottom of the channel hole 112, 122.

2A and 2B are distribution diagrams of threshold voltages of memory cells in a three-dimensional memory, with the horizontal axis representing the threshold voltage Vt and the vertical axis representing the number of memory cells. 2A and 2B take Multi-Level Cell (MLC) technology as an example, according to which each memory cell stores 2-bit information, namely 00, 01, 10 and 11. FIG. The threshold voltage of the memory cell may be in four states, E state, P1 state, P2 state, and P3 state, as shown in FIGS. 2A and 2B. Among them, the E state is the erase state corresponding to the erase operation whose corresponding data format is 11, and the P1, P2, and P3 states are the program states corresponding to the program operations whose corresponding data format is 00, 01, and 10, respectively.

FIG. 2A is a distribution diagram of threshold voltages under normal conditions. Looking at FIG. 2A, there are multiple margins between each state, e.g., a margin distance divided into E0 and E1 margins between the E and P1 states, where the E0 margin is close to the E state and the E1 margin is close to the P1 state. Similarly, the margin distances between the P1, P2 and P3 states are divided into E2 margin, E3 margin, E4 margin and E5 margin.

When a read operation is performed on a memory cell, a read voltage (Vread) is applied to the gates of the read memory cells, said memory cells being turned on, and a pass voltage ( _Vpass ) is applied to the other memory cells on the same memory sling as the read memory cell. The pass voltage is also called the transmission voltage or turn-on voltage. A memory string may be viewed as a memory cell string distributed along a channel hole structure as shown in FIG. In the small opening memory cell at the bottom of the channel hole structure, the pass voltage will bring high electric field intensity and strong tunneling effect, which will bring certain programming effect to the memory cell. Memory cells in the erased state are particularly susceptible to the program effect of the pass voltage due to their low threshold voltages, thereby broadening the erased state E state distribution, eg, as shown in FIG. 2B.

FIG. 2B is a distribution diagram of threshold voltages when the voltage distribution in the erased state is wide. Looking at FIG. 2B, the voltage distribution in the E0 state spreads out toward the P1 state, resulting in a reduced E0 margin. Due to the shrinking E0 margin, erroneous reads of memory cells in the E state can occur, resulting in read disturb and reduced data storage reliability.

FIG. 3 is a schematic diagram of the effect of read disturb on the E0 margin. As shown in FIG. 3, the horizontal axis represents the word line (WL) number 0 to 127 of the three-dimensional memory, indicating that the three-dimensional memory is a 128-layer 3D NAND flash. Also, the three-dimensional memory has two decks, as shown in FIG. The vertical axis of FIG. 3 represents the E0 margin width value, which is the median of several test results. Looking at FIG. 3, the left half 310 of the horizontal axis shows the original state of the memory cell without programming (fresh), and the right half 320 shows the state of the memory cell after 300 cycles (300 cyc) of programming.

Looking at FIG. 3, the left half 310 and the right half 320 each have four curves corresponding to different reading times. Among them, the reading time corresponding to curves 311 and 321 is 0, the reading time corresponding to curves 312 and 322 is 1000, the reading time corresponding to curves 313 and 323 is 3000, and the reading time corresponding to curves 314 and 324 is 30000. Clearly, the E0 margin gradually shrinks as the read time increases. FIG. 3 corresponds to a three-dimensional memory with two decks shown in FIG. 1, where the word line numbers 0-63 belong to the first deck, the numbers gradually increase upward from the bottom surface of the channel hole structure, and the word line numbers 64-127 belong to the second deck.

Taking left half 310 as an example in conjunction with FIGS. 1 and 3, word line number 0 corresponds to the memory cell at the bottom of the channel hole structure. After several read operations, the size of the E0 margin of memory cells in the first deck increases as the number of word lines (0-63) increases, and the size of the E0 margin of memory cells in the second deck also increases as the number of word lines (64-127) increases. Therefore, the E0 margin for the memory cells at the bottom of the deck is the smallest, e.g., the first range 315, the second range 316, enclosed by the dashed circle in FIG. 3, corresponding to the memory cells at the bottom of the first deck and the memory cells at the bottom of the second deck, respectively.

In the right half 320, the E0 margin of the memory cell after 300 cycles of programming is somewhat less than the E0 margin of the memory cell in its original state without undergoing programming. In addition, like the left half 310, the E0 margins of the memory cells at the bottom of the first deck and at the bottom of the second deck are relatively small, e.g.

FIG. 4 is an exemplary flow diagram of a method for controlling a three-dimensional memory, according to an embodiment of the present disclosure; A three-dimensional memory comprises a plurality of memory strings, each memory string comprising a plurality of memory cells comprising a first portion and a second portion, wherein the diameter of the channel structure corresponding to the first portion of the memory cells is smaller than the diameter of the channel structure corresponding to the second portion of the memory cells. Looking at FIG. 4, the control method of this embodiment is:
Step S410: Applying a pass voltage to the unselected memory cells when performing a read operation on the selected memory cell, wherein a first pass voltage is applied to the first unselected memory cells of the first portion and a second pass voltage is applied to the second unselected memory cells of the second portion, the first pass voltage being lower than the second pass voltage.

In some implementations, memory cells in a memory string of a three-dimensional memory are coupled to corresponding word lines to which pass voltages are applied, thereby effecting the application of bus voltages to the memory cells.

In some embodiments, when a read operation is performed on a selected memory cell, a read voltage is applied to the word line of the selected memory cell.

5A-5D are schematic diagrams of implementations of methods for controlling three-dimensional memory cells, according to certain embodiments of the present disclosure. The control method shown in FIG. 4 is described below in conjunction with FIGS. 5A-5D.

Looking at FIG. 5A, a structural diagram of a 128-layer three-dimensional memory with two decks is shown. The three-dimensional memory comprises a first deck 510 located at the bottom and a second deck 520 located at the top. The first deck 510 comprises 64 gate layers WL0-WL63 and the second deck 520 also comprises 64 gate layers WL64-WL127. The three-dimensional memory also has several virtual gate layers 530 between the first deck 510 and the second deck 520, the virtual gate layers 530 do not provide an actual gate effect. It can be seen that in the structure of a three-dimensional memory, a word line is connected to a gate layer, and a voltage can be applied through the word line to the gate layer connected to the word line. In Figures 5A-5D, WL (word line) is used to represent the name of the gate layer connected to different word lines.

In this embodiment, the diameter of the channel structure corresponding to the memory cell is the opening of the channel hole structure, as shown in FIG.

In connection with FIGS. 1-5A, the channel structure opening corresponding to the memory cells associated with the bottom several gate layers in the first deck 510 is relatively small, assuming that the number of gate layers is about 15-20, i.e., the gate layers in which the first portion of the memory cells are located are WL0-WL14 to WL0-WL19.

This disclosure does not limit the number of memory cells in the first and second portions, nor the number of corresponding gate layers. In actual implementation of the control method, the extent of the gate layer in which the first and second portions of the memory cell are located can be set as desired.

The present disclosure will be described by taking 16 layers as an example. Looking at FIG. 5A, the memory cells corresponding to WL0-WL15 and WL65-WL79 belong to the first part in step S410, and the memory cells in the rest of the gate layer belong to the second part.

To explain step S410, it will be explained according to the number of gate layers in which the selected memory cell is located, respectively.

In FIG. 5A, the selected memory cells 540 are at WL0-WL23, and the memory cells located in the other gate layers, including WL24-WL127, are unselected memory cells. When the read voltage Vread is applied to the selected memory cell 540, the pass voltage Vpass is applied to other unselected memory cells. Among these unselected memory cells, the memory cells located at WL64 to WL78 belong to the first portion, and the unselected memory cells in this portion are called first unselected memory cells 550. FIG. Other unselected memory cells, including memory cells located at WL24-WL63 and WL79-WL127, belong to the second portion, and these unselected memory cells are referred to as second unselected memory cells 560. FIG. According to step S410, a first pass voltage Vpass1 is applied to the first unselected memory cells 550 belonging to the first portion and a second pass voltage Vpass2 is applied to the second unselected cell memories 560 belonging to the second portion, where Vpass1<Vpass2.

It should be noted that the selected memory cell 540 of WL0-WL23 means that the selected memory cell 540 is located in any one or more layers of WL0-WL23. Selected memory cells 540 may be located in different memory strings, but the diameters of channel structures corresponding to memory cells 540 in the same gate layer but in different memory strings are approximately the same. If the selected memory cell 540 is in layer WL15, the pass voltage is applied to the memory cells on the gate layers WL0-W23 except for WL15, similarly according to the principle of step S410, that is, according to the principle that the first pass voltage Vpass1 is applied to WL0-WL14 belonging to the first portion, and the second pass voltage Vpass2 is applied to WL16-WL23 belonging to the second portion.

In FIG. 5B, the selected memory cells 540 are on WL24 to WL55, and the memory cells located on the other gate layers are unselected memory cells. When the read voltage Vread is applied to the selected memory cell 540, the pass voltage Vpass is applied to other unselected memory cells. Among these unselected memory cells, a first unselected memory cell 550 comprises memory cells located on gate layers WL0-WL15 and WL64-WL79, and a second unselected memory cell 560 comprises memory cells located on gate layers WL16-WL23, WL56-WL63, and WL80-WL127. According to step S410, a first pass voltage Vpass1 is applied to the first unselected memory cell 560, where Vpass1<Vpass2.

In FIG. 5C, the selected memory cells are WL56 to WL87, and the other memory cells located in the gate layer are unselected memory cells. When the read voltage Vread is applied to the selected memory cell 540, the pass voltage Vpass is applied to other unselected memory cells. Among these unselected memory cells, a first unselected memory cell 550 comprises memory cells located on gate layers WL0-WL15, and a second unselected memory cell 560 comprises memory cells located on gate layers WL16-WL55 and WL88-WL127. According to step S410, a first pass voltage Vpass1 is applied to the first unselected memory cell 550 and a second pass voltage Vpass2 is applied to the second unselected memory cell 560, where Vpass1<Vpass2.

In FIG. 5D, the selected memory cells 540 are WL88 to WL127, and the other memory cells located in the gate layer are unselected memory cells. When the read voltage Vread is applied to the selected memory cell 540, the pass voltage Vpass is applied to other unselected memory cells. Among these unselected memory cells, a first unselected memory cell 550 comprises memory cells located on gate layers WL0-WL15 and WL64-WL79, and a second unselected memory cell 560 comprises memory cells located on gate layers WL16-WL63 and WL80-WL87. According to step S410, a first pass voltage Vpass1 is applied to the first unselected memory cell 550 and a second pass voltage Vpass2 is applied to the second unselected memory cell 560, where Vpass1<Vpass2.

In the above embodiment, the second pass voltage may be a commonly used standard voltage, eg, Vpass2=6.5-7V. The first pass voltage is lower than the standard pass voltage, eg, Vpass=6-6.5V. The first pass voltage Vpass1 is about 0.5V lower than the second pass voltage Vpass2.

FIG. 6 is an effect schematic diagram of a control method for three-dimensional memory according to an embodiment of the present disclosure. Looking at FIG. 6, its horizontal axis represents the number of word lines in the three-dimensional memory from 0 to 127, and its vertical axis represents the width of the E0 margin. FIG. 6 is an example of the average E0 margin obtained after 30000 read duty cycles. Curve 610 shows that the second pass voltage Vpass2 is applied to all of the unselected cells, and curve 620 shows that the first pass voltage Vpass1 is applied to the first unselected memory cells and the second pass voltage Vpass2 is applied to the second unselected memory cells.

In the embodiment as seen in FIG. 6, Vpass1=6.2V and Vpass2=6.6V. As can be seen in FIG. 6, for memory cells near WL0-WL16 at the bottom of the channel structure, the Y-axis value of curve 620 is greater than the Y-axis value of curve 610, i.e., the method of the present disclosure increases the E0 margin for memory cells near WL0-WL16.

According to the control method of the three-dimensional memory described above, a first pass voltage that is lower than the standard pass voltage is applied to the memory cells whose channel structure has a relatively small diameter, so that the read disturb of this part of the memory cells can be mitigated.

Turning to FIG. 4, in some embodiments, the method of controlling a three-dimensional memory of the present disclosure further comprises:
Step 420: Applying a second pass voltage to a second unselected memory cell when a program verify operation is performed on the selected memory cell; applying the first pass voltage to the first unselected memory cell if the first unselected memory cell is in a programmed state; and applying a second pass voltage to the first unselected memory cell if the first unselected memory cell is in an erased state. Step 420 is described below in conjunction with FIGS. 7A-7D.

In some embodiments, when a program verify operation is performed on a selected memory cell, a program verify voltage is applied to the word line of the selected memory cell.

7A-7D are schematic diagrams of implementations of a control method for a three-dimensional memory, according to certain embodiments of the present disclosure. Figures 7A-7D are examples of four situations, each with a different number of gate layers in which the selected memory cell is located.

Looking at FIG. 7A, a schematic diagram of a 128-layer three-dimensional memory with two decks is shown similar to FIG. The three-dimensional memory comprises a first deck 710 located at the bottom and a second deck 720 located at the top. The first deck 710 comprises 64 gate layers WL0-WL63 and the second deck 720 also comprises 64 gate layers WL64-WL127. The first deck 710 further comprises a number of virtual gate layers 730 between the first deck 710 and the second deck 720 that do not provide a real gate layer effect. The memory cells on the gate layers WL0 to WL15 and WL64 to WL79 correspond to the first portion of the small opening channel structure, and the memory cells on the other gate layers correspond to the second portion of the large opening channel structure.

In FIG. 7A, the selected memory cells 740 are at WL0-WL23, and the memory cells located in the other gate layers, including WL24-WL127, are unselected memories. When the program verify voltage Vverify is applied to the selected memory cell 740, the pass voltage Vpass is applied to other unselected memory cells.

In some embodiments, each memory cell is located at a corresponding cell depth in the memory string, and programming operations are performed on a page of memory cells located at the same cell depth through word lines layer by layer in the direction in which the channel structure of the memory string extends. Looking at FIG. 7A, in this embodiment, the number of word lines increases layer by layer in a first direction D1, which also corresponds to the spreading direction of the channel structure of the memory string. WL0 corresponds to the bottom surface of the channel structure and WL127 corresponds to the top surface of the channel structure. Also, WL0 corresponds to the bottom surface of the channel structure on the first deck 710, WL63 corresponds to the top surface of the channel structure on the first deck 710, WL64 corresponds to the bottom surface of the channel structure on the second deck 720, and WL127 corresponds to the top surface of the channel structure on the second deck 720.

Memory cells at the same gate layer have the same cell depth, and memory cells at the same cell depth form a three-dimensional memory page. In embodiments such as those shown in Figures 7A-7D, programming begins at the bottom layer WL0 and proceeds layer by layer upwards.

During a program operation (which may also be referred to as write data), memory cells are programmed according to word line program order or other programming rules. For example, a programming operation may begin with a word line on the source side of a memory block and continue on a word line on the drain side of the memory block. One program rule is to proceed to program the next word line (ie, program within a page) as each word line completes programming. During a program operation, in a three-dimensional memory, one or more layers are selected as a selection layer, a programming voltage is applied to the selection layer, and no bit line voltage is applied to the bit line corresponding to the selection string, i.e. the bit line corresponding to the selection string is regarded as the selection string to be programmed, while the suppression operation is performed for the other memory strings.

Looking at FIG. 7A, a selected memory cell 740 is located in gate layers WL0-WL23, which may be one or more layers therein. In this case, the other gate layers WL24 to WL127 have not been programmed and are in an erased state. Therefore, the pass voltage Vpass applied to the unselected memory cells on WL24 to WL127 is the second pass voltage Vpass2.

In FIG. 7B, the selected memory cells 741 are WL24 to WL55, and the other memory cells located in the gate layer are unselected memory cells. When the program verify voltage Vverify is applied to the selected memory cell 741, the pass voltage Vpass is applied to other unselected memory cells. The second pass voltage Vpass2 is applied to the second unselected memory cell 761 among these unselected memory cells. As can be seen in FIG. 7A, the first unselected memory cells 750 in the gate layers WL0-WL15 have undergone the programming operation and are in the programmed state, so the first pass voltage Vpass1 is applied to the first unselected memory cells 750. The unselected memory cells 762 located in the gate layers WL56-WL127 are in an erased state and are therefore subject to the second pass voltage Vpass2, where Vpass1<Vpass2. The unselected memory cells 762 include first unselected memory cells WL64-WL79 belonging to the first portion and second unselected memory cells WL80-WL127 belonging to the second portion.

In FIG. 7C, the selected memory cells 742 are WL56 to WL87, and the memory cells located in the other gate layers are unselected memory cells. When the program verify voltage Vverify is applied to the selected memory cell 742, the pass voltage Vpass is applied to other unselected memory cells. Among these unselected memory cells, second pass voltage Vpass2 is applied to second unselected memory cells 763 comprising memory cells located in gate layers WL16-WL55 and WL88-WL127. The unselected memory cells further comprise a first unselected memory cell 750 located in the gate layers WL0-WL15, and as can be seen in FIG. 7A, this first unselected memory cell 750 has undergone a programming operation and is in a programmed state, so a first pass voltage Vpass1 is applied to this first unselected memory cell 750.

In FIG. 7D, the selected memory cells 743 are WL88 to WL127, and the memory cells located in the other gate layer are unselected memory cells. When the program verify voltage Vverify is applied to the selected memory cell 743, the pass voltage Vpass is applied to other unselected memory cells. Among these unselected memory cells, second pass voltage Vpass2 is applied to second unselected memory cells 764 comprising memory cells located in gate layers WL16-WL63 and WL80-WL87. The unselected memory cells further comprise a first unselected memory cell 750 on the gate layers WL0-WL15 and a first unselected memory cell 751 on the gate layers WL64-WL79, as can be seen in FIG. 7A, these unselected memory cells have undergone a programming operation and are in a programmed state, so the first unselected memory cells 750, 751 are applied with a first pass voltage Vpass1.

Application of the program verify voltage Vverify to a memory cell is equivalent to a read operation, which also results in read disturb for memory cells with relatively small openings. According to the control method of the above embodiment, the read disturb of the program verification voltage can be reduced during that period.

7A-7D are examples of embodiments in which the programming operation begins at gate layer WL0 and progresses layer-by-layer to WL127. In other embodiments, programming operations may be performed layer-by-layer from gate layer WL127 down to WL0, and the method of operation described above also applies to these embodiments.

FIG. 8 is a module diagram of a three-dimensional memory according to certain embodiments of the present disclosure; The three-dimensional memory control methods of the present disclosure so far described can be used to control the three-dimensional memory of the present embodiments, and therefore all of the drawings and detailed descriptions so far described can be used to depict the three-dimensional memory of the present disclosure.

Looking at FIG. 8, the three-dimensional memory comprises memory cell array 810 and controller 820 . Memory cell array 810 comprises a plurality of memory strings, each extending vertically over a substrate and comprising a plurality of memory cells arranged vertically in a series connection. The plurality of memory cells has a first portion and a second portion, wherein the diameter of the channel structure in the first portion of the memory cells is smaller than the diameter of the channel structure in the second portion of the memory cells. The controller 820 is configured to apply a pass voltage Vpass to the unselected memory cells when a read operation is performed on the selected memory cell, wherein a first pass voltage Vpass1 is applied to the first unselected memory cells in the first portion and a second pass voltage Vpass2 is applied to the second unselected memory cells in the second portion, the first pass voltage Vpass1 being lower than the second pass voltage Vpass2.

Depending on the embodiment, the controller 820 will further apply a second non -selected memory cell to the second non -selected memory cell, and if the first non -selected memory cell is in a program state, the first pass voltage VPASS1 is the first selection memory cell. It is configured so that if the first non -selected memory cell is in the erasure state, the first non -selected memory cell is applied to the second pass voltage VPass2.

The controller 820 can use the three-dimensional memory control method of the present disclosure to perform the functions described above, and therefore the drawings and detailed descriptions described above can be used to depict the specific functions of the three-dimensional memory controller 820 of the present disclosure. If the content is the same, it will not be described any further.

In this embodiment, each memory cell included in the memory cell array 810 may be a single-level cell (SLC) that stores 1-bit data, a multi-level cell (MLC) (such as MLC, TLC, and QLC) that can store more than two bits of data, or any combination of single-level cells and multi-level cells.

In this embodiment, memory cells in memory cell array 810 can be connected to word lines WL and bit lines BL. On the other hand, the memory cell array 810 can also be connected to other select lines, such as string select lines SSL and ground select lines GSL. Specifically, the memory cell array 810 can be connected to a word line decoder 850 through word lines WL or select lines (SSL and/or GSL) and further to a voltage generator 860 . The memory cell array 810 may be connected to a bitline decoder 830 through bitlines BL and further to input/output (I/O) circuitry 840 . Controller 820 is connected to bit line decoder 830, I/O circuit 840, word line decoder 850, and voltage generator 860, respectively.

When one or more memory cells need to be erased, programmed, read-written, or verified, controller 820 can send the address of one or more memory cells for addressing by bit line decoder 830 through bit line BL and by word line decoder 850 through word line WL.

In some embodiments, the functions of bitline decoder 830 and wordline decoder 850 may be performed by a unified address decoder. The address decoder may further comprise components such as address buffers.

The I/O circuitry 840 can, on one hand, receive data from the controller 820 and/or outside and store the received data in the memory cell array 810 for write operations, and on the other hand can read data from the memory cell array 810 and output the read data to the controller 820 and/or outside for read operations.

The voltage generator 860 can receive control signals from the controller 820 and generate various voltages for performing erase operations, program operations, read-write operations, and verify operations on the memory cell array 810 . In particular, voltage generator 860 can generate word line voltages, such as program voltages (ie, write voltages), program inhibit voltages, read voltages, and verify voltages. A voltage generator 860 can generate a bit line voltage, such as a bit line apply voltage or a blocking voltage. In this embodiment of the present disclosure, the voltage generator 860 can generate the pass voltage Vpass (including the first pass voltage Vpass1 and the second pass voltage Vpass2), the read voltage Vread, and the program verify voltage Vverify, etc., as described above.

Controller 820 may output control signals to bit line decoder 830 , I/O circuitry 840 , word line decoder 850 , and voltage generator 860 . For example, controller 820 may output voltage control signals to voltage generator 860, output word line addresses to word line decoder 850, output bit line addresses to bit line decoder 830, output write data to I/O circuitry 840, and receive data read from I/O circuitry 840.

In some embodiments, controller 820 controls bit line decoder 830 to select some bit lines BL, word line decoder 850 to select some word lines WL, and applies a constant voltage to these bit lines BL and word lines WL through voltage generator 860. For example, during a read operation, a read voltage may be applied to the selected word line WL, and in memory cells where reading is blocked, a read blocking voltage may be applied to the unselected bit lines BL. During a program operation, a program voltage and a verify voltage may be applied to the selected word line WL, and a program blocking voltage is applied to the unselected bit lines BL.

The controller 820 of this embodiment of the disclosure may further comprise components such as processors, I/O interfaces, and the like. The control logic of controller 820 for bit line decoder 830, I/O circuit 840, word line decoder 850, and voltage generator 860 is not limited to that described above. Controller 820 may perform other logical control functions for non-volatile memory as will be appreciated by those skilled in the art.

In some embodiments, controller 820 can indicate, based on software, the memory operations that memory cell array 810 needs to perform.

In this embodiment of the present disclosure, the memory strings extend vertically over the substrate. The substrate may be a silicon substrate (Si), a germanium substrate (Ge), a silicon germanium substrate (SiGe), a Silicon On Insulator (SOI), a Germanium On Insulator (GOI), or the like. In some embodiments, the substrate may also be a substrate comprising other elemental or compound semiconductors such as GaAs, InP, or SiC. The substrate may also be a stacked structure such as Si/SiGe. The substrate may also comprise other epitaxial structures such as SiGe On Insulator (SGOI). In some embodiments, the substrate may be made from a non-conductive material such as glass, plastic, or a sapphire wafer. The substrate has undergone some necessary processing, eg, a common active area has been formed, necessary cleaning has been performed, and so on.

A stack structure may be disposed over the substrate, the stack structure being a stack formed by alternating layers of a first material layer and a second material layer. The first material layer and the second material layer may be selected from the following materials, which may include at least one insulator, such as silicon nitride, silicon oxide, amorphous carbon, diamond-like amorphous carbon, germanium oxide, aluminum oxide, etc., and combinations thereof. The first material layer and the second material layer have different etch selectivities. For example, they may be a combination of silicon nitride and silicon oxide, a combination of silicon oxide and undoped polysilicon or amorphous carbon, a combination of silicon oxide or silicon nitride and amorphous carbon, and the like. Methods of depositing the first material layer and the second material layer of the stacked structure include Chemical Vapor Deposition (CVD, PECVD, LPCVD, and HDPCVD), Atomic Layer Deposition (ALD), or Molecular Beam Epitaxy (MBE), thermal oxidation, and evaporation. , sputtering, and various other methods. In this embodiment of the present disclosure, the first layer of material may be a gate layer and the second layer of material may be an insulating layer. A gate layer may be formed after removal of the dummy gate layer. The material of the gate sacrificial layer may be, for example, a silicon nitride layer. The material of the gate layer may be a conductive material such as metallic tungsten, cobalt, copper, nickel, or may be polysilicon, doped silicon, or any combination thereof. The material of the insulating layer may be, for example, silicon oxide, aluminum oxide, hafnium oxide, tantalum oxide, or the like.

In this embodiment of the present disclosure, the material of the substrate may be silicon, for example. The first material layer and the second material layer are, for example, a combination of silicon nitride and silicon oxide. Taking the combination of silicon nitride and silicon oxide as an example, a stacked structure can be formed by alternately depositing silicon nitride and silicon oxide on a substrate by chemical vapor deposition (CVD), atomic layer deposition (ALD) or other suitable deposition methods.

Although the specification describes representative compositions of initial semiconductor structures, it is understood that one or more features may be removed from, substituted for, or added to such semiconductor structures. For example, various well regions may be formed in the substrate as desired. Also, the materials given as examples for each layer are merely exemplary, for example the substrate may be SOI (silicon-on-insulator), SiGe, Si:C or other silicon-containing substrates. The gate layer may also be other conductive layers, such as metallic tungsten, cobalt, nickel, and the like. The second material may also be other insulating materials such as aluminum oxide, hafnium oxide, tantalum oxide, and the like.

A channel structure corresponding to the memory cell may be formed in a channel hole vertically penetrating the stack structure. Therefore, the channel structure may be cylindrical. The channel structure may comprise a channel layer or a memory layer. Overall, the memory layer and the channel layer are arranged seamlessly from the outside to the inside in the radial direction of the channel structure. The memory layer may comprise a blocking layer, a charge trapping layer, and a tunneling layer, which are deposited in a radial direction of the channel structure from the outside to the inside of the channel structure without interruption. A fill layer may also be disposed in the channel layer. The packing layer can act as a support. The material of the filling layer may be silicon oxide. The fill layer may be solid or hollow provided that it does not affect device reliability. Formation of the channel structure may be performed by one or more film deposition processes such as ALD, CVD, PVD, etc., or any combination thereof.

In some embodiments, the three-dimensional memory of the present disclosure further comprises a plurality of word lines, each of the plurality of word lines connecting with a page of memory cells of the same cell depth, each memory cell located at a corresponding cell depth in the mesring.

FIG. 9 is a circuit schematic diagram of a memory block that can be used in this embodiment of the present disclosure. A memory cell array 810 as seen in FIG. 8 may comprise a plurality of memory blocks. Looking at FIG. 9, MC (memory cell) represents a memory cell, and the cell depth of each memory cell corresponds. For example, memory cell MC in FIG. 9 is located in a gate layer connected to word line WL8. A memory string STR connects a plurality of memory cells seamlessly in a direction in which the number of word line layers WL1 to WL8 gradually increases. Memory cells with the same cell depth are located on the same page. Controller 820 controls voltage generator 860 to generate the voltage applied to each word line according to the settings, thereby controlling the voltage applied to each memory cell.

Each string STR may further comprise a string select transistor SST and a ground select transistor GST respectively connected across the seamlessly connected memory cells MC. GSL stands for common source line. The number of memory strings STR, word lines WL, and bit lines BL may vary depending on the embodiment.

FIG. 9 is merely illustrative and does not limit the actual structure, number of wordline layers, etc. of the three-dimensional memory of the present disclosure.

In some embodiments, the diameter of the channel structure of the memory string of the present disclosure gradually increases from the bottom surface to the top surface of the memory string.

In some embodiments, the first portion of the memory cells underlies the second portion of the memory cells.

In some embodiments, the memory string comprises a first memory string and a second memory string stacked in the direction in which the channel structure extends, the diameter of the channel structure of the first memory string gradually increasing from the bottom surface to the top surface of the first memory string, and the diameter of the channel structure of the second memory string gradually increasing from the bottom surface to the top surface of the second memory string. The diameter of the channel structure at the top surface of the first memory string may be larger than the diameter of the channel structure at the bottom surface of the second memory string. For the structure of the three-dimensional memory of these embodiments, reference can be made to FIG. 1, which comprises more than two decks each comprising a channel structure with a smaller diameter at the bottom and a larger diameter at the top.

In some embodiments, the three-dimensional memory cells of the present disclosure are 3D NAND flash.

In the three-dimensional memory of the present disclosure, a relatively low first pass voltage is applied to the memory cells that are small opening channel structures during a read operation, thereby effectively reducing the read disturb of this portion of the memory cells, and in the program verify phase, by also applying a relatively low first pass voltage to the memory cells that are small opening channel structures, further reducing the read disturb of this portion of the memory cells and enhancing the reliability of the three-dimensional memory.

Although the present disclosure has been described with reference to specific embodiments at the present time, it should be appreciated by those skilled in the art that the foregoing embodiments were only used to describe the disclosure and that various equivalent modifications and substitutions may be made without departing from the spirit of the disclosure. Therefore, variations and variations of the above-described embodiments, so long as they come within the substantial spirit of this disclosure, are covered by the claims of this application.

110 first deck 111 stack structure 112 channel hole structure 113 bottom surface 114 top surface 120 second deck 121 stack structure 122 channel hole structure 123 bottom surface 124 top surface 310 left half 311 curve 313 curve 314 curve 315 first range 316 second range 320 right half 510 second Deck 1 520 Second deck 540 Selected memory cell 550 First unselected memory cell 560 Second unselected memory cell 610 Curve 620 Curve 710 First deck 720 Second deck 740 Selected memory cell 741 Selected memory cell 742 Selected memory cell 743 Selected memory cell 750 First unselected memory cell 751 First unselected memory cell 761 second unselected memory cell 762 unselected memory cell 763 second unselected memory cell 764 second unselected memory cell 810 memory cell array 820 controller 830 bit line decoder 840 input/output (I/O) circuit 850 word line decoder 860 voltage generator

Claims (14)

A method for controlling a three-dimensional memory, wherein the three-dimensional memory comprises a first deck and a second deck stacked vertically on a substrate, the first deck and the second deck each comprising a plurality of memory strings, each memory string comprising a plurality of memory cells, the plurality of memory cells comprising a first portion and a second portion, wherein a diameter of a channel structure corresponding to a first portion of the memory cells corresponds to a second portion of the memory cells. diameter, the method comprising:
performing a read operation on selected memory cells in the first deck and/or the second deck;
applying a pass voltage to unselected memory cells other than the selected memory cell in the first deck and the second deck, wherein the pass voltage comprises a first pass voltage and a second pass voltage, wherein the first pass voltage is lower than the second pass voltage, the first pass voltage is applied to the first unselected memory cells of the first portion, and the second pass voltage is applied to the second unselected memory cells of the second portion; control methods, including; performing a program verify operation on the selected memory cell;
a step of applying the pass voltage to unselected memory cells other than the selected memory cells in the first deck and the second deck, wherein the second pass voltage is applied to the second unselected memory cells, the applied pass voltage is determined according to the state of the first unselected memory cells, and if the first unselected memory cells are in a programmed state, the first pass voltage is applied to the first unselected memory cells; 2. The control method of claim 1, further comprising: applying a pass voltage to the first unselected memory cell. 2. The control method of claim 1, wherein the memory cells in the memory string are connected to corresponding word lines, and the pass voltage is applied to the memory cells through the corresponding word lines. 4. The control method of claim 3, wherein when the read operation is performed on the selected memory cell, a read voltage is applied to the word line of the selected memory cell. 4. The control method of claim 3, wherein a program verify voltage is applied to the word line of the selected memory cell when a program verify operation is performed on the selected memory cell. 4. The control method of claim 3, wherein each memory cell is at a corresponding cell depth in said memory string, and a programming operation is performed to a page of said memory cells at the same cell depth through said word lines layer by layer in the direction of extension of the channel structure of said memory string. A three-dimensional memory,
a memory cell array comprising a first deck and a second deck stacked vertically on a substrate, the first deck and the second deck each comprising a plurality of memory strings, each memory string extending vertically over the substrate and comprising a plurality of memory cells vertically arranged in series connection;
said plurality of memory cells comprising a first portion and a second portion, wherein a diameter of a channel structure in a first portion of said memory cell is smaller than a diameter of said channel structure in a second portion of said memory cell;
A controller configured to send a control signal to a voltage controller when a read operation is performed on a selected memory cell, in response to the control signal, applying a pass voltage comprising a first pass voltage and a second pass voltage to unselected memory cells, wherein the first pass voltage is lower than the second pass voltage, the first pass voltage is applied to the first unselected memory cells of the first portion, and the second pass voltage is applied to the second unselected memory cells of the second portion. A three-dimensional memory, comprising: a controller. The controller is further configured to send a control signal to the voltage controller when a program verify operation is performed on a selected memory cell, the voltage controller applying the second pass voltage to the second unselected memory cell in response to the control signal, applying the first pass voltage to the first unselected memory cell if the first unselected memory cell is in a programmed state, and applying the second pass voltage to the first unselected memory cell if the first unselected memory cell is in an erased state. 8. The three-dimensional memory according to claim 7, wherein the voltage is applied. 8. The three-dimensional memory of claim 7, further comprising a plurality of word lines, each word line being at the same cell depth and coupled to a page of memory cells, each memory cell being located at a corresponding cell depth in the memory string. 8. The three-dimensional memory of claim 7, wherein the diameter of the channel structure of the memory string gradually increases from the bottom surface to the top surface of the memory string. 8. The three-dimensional memory of claim 7, wherein the first portion of the memory cells underlies the second portion of the memory cells. 8. The three-dimensional memory according to claim 7, wherein the memory string comprises a first memory string and a second memory string stacked in the direction in which the channel structure spreads, the diameter of the channel structure of the first memory string gradually increasing from the bottom surface to the top surface of the first memory string, and the diameter of the channel structure of the second memory string gradually increasing from the bottom surface to the top surface of the second memory string. 13. The three-dimensional memory of claim 12, wherein the diameter of the channel structure at the top surface of the first memory string is larger than the diameter of the channel structure at the bottom surface of the second memory string. 8. The three-dimensional memory of claim 7, wherein the three-dimensional memory is 3D NAND flash.

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