JP7575496B2 - Three-dimensional memory and control method thereof - Google Patents

Description

This disclosure relates to the field of integrated circuit manufacturing, and more specifically to three-dimensional memories and control methods thereof.

To overcome the limitations of two-dimensional memory elements, the industry has developed and produced large-scale memory elements with three-dimensional (3D) structures in which memory cells are arranged three-dimensionally on a substrate, increasing integration density. 3D NAND flash is a three-dimensional memory element. As the number of stack layers increases, the channel hole gradually becomes deeper. Since the upper opening of the channel hole is larger than its lower opening, the difference between the upper and lower openings of the channel hole increases as the channel hole becomes deeper. When a read operation is performed on a three-dimensional memory element and the same pass voltage is applied to each memory cell on a memory string formed by the same channel hole, if the opening of the channel hole where the memory cell is located is relatively small, the pass voltage will bring a higher electric field strength to the memory cell, and after multiple reads, will cause read disturbance to the memory cell.

The technical problem to be solved by this disclosure is to provide a three-dimensional memory that reduces read disturbance and a method for controlling the same.

In order to solve the above technical problems, the technical solution adopted by the present disclosure is a control method for a three-dimensional memory element, in which a three-dimensional memory includes a first deck and a second deck stacked in the vertical direction of a substrate, the first deck and the second deck each including a plurality of memory strings, each memory string including a plurality of memory cells, the plurality of memory cells including a first portion and a second portion, and a diameter of a channel structure corresponding to the first portion of the memory cells being smaller than a diameter of a channel structure corresponding to the second portion of the memory cells, the method including: performing a read operation on a selected memory cell in the first deck and/or the second deck; and applying a pass voltage to unselected memory cells other than the selected memory cell in the first deck and the second deck, the pass voltage including a first pass voltage and a second pass voltage, the first pass voltage being lower than the second pass voltage, the first pass voltage being applied to the first unselected memory cell in the first portion, and the second pass voltage being applied to the second unselected memory cell in the second portion.

In an embodiment of the present disclosure, the method further includes performing a program verify operation on the selected memory cell and applying a pass voltage to unselected memory cells other than the selected memory cell in the first deck and the second deck, where a second pass voltage is applied to the second unselected memory cell, the applied pass voltage being determined according to a state of the first unselected memory cell, and if the first unselected memory cell is in a programmed state, the first pass voltage is applied to the first unselected memory cell, and if the first unselected memory cell is in an erased state, the second pass voltage is applied to the first unselected memory cell.

In one embodiment of the present disclosure, memory cells in a memory string are coupled to a corresponding word line through which a pass voltage is applied to the memory cells.

In one embodiment of the present disclosure, when a read operation is performed on a selected memory cell, a read voltage is applied to the word line of the selected memory cell.

In one embodiment of the present disclosure, when a program verify operation is performed on a selected memory cell, a program verify voltage is applied to the word line of the selected memory cell.

In one embodiment of the present disclosure, each memory cell is at a corresponding cell depth in a memory string, and programming is performed on a page of memory cells at the same cell depth through word lines in a layer-by-layer manner in the direction of the extent of the channel structure of the memory string.

To solve the above technical problems, the present disclosure further proposes a three-dimensional memory, which includes a memory cell array having a first deck and a second deck stacked vertically on a substrate, each of the first deck and the second deck having a plurality of memory strings, each of the memory strings extending vertically above the substrate and having a plurality of memory cells arranged vertically in series connection; a plurality of memory cells having a first portion and a second portion, the diameter of the channel structure of the first portion of the memory cell being smaller than the diameter of the channel structure of the second portion of the memory cell; and a controller configured to send a control signal to the voltage controller when a read operation is performed on a selected memory cell, the controller being configured to apply a pass voltage including a first pass voltage and a second pass voltage to the unselected memory cells in response to the control signal, the first pass voltage being lower than the second pass voltage, the first pass voltage being applied to the first unselected memory cell of the first portion, and the second pass voltage being applied to the second unselected memory cell of the second portion.

In some embodiments of the present disclosure, the controller is further configured to send a control signal to the voltage controller when a program verify operation is performed on the selected memory cell, and the voltage controller, in response to the control signal, applies a second pass voltage to a second unselected memory cell, applies the first pass voltage to a first unselected memory cell if the first unselected memory cell is in a programmed state, and applies the second pass voltage to the first unselected memory cell if the first unselected memory cell is in an erased state.

In some embodiments of the present disclosure, the three-dimensional memory further comprises a plurality of word lines, each of which is coupled to a page of memory cells at the same cell depth, with each memory cell located at a corresponding cell depth in a memory string.

In one embodiment of the present disclosure, the diameter of the channel structure of the memory string gradually increases from the bottom surface to the top surface of the memory string.

In some embodiments of the present disclosure, a first portion of the memory cell is located below a second portion of the memory cell.

In one embodiment of the present disclosure, a memory string includes a first memory string and a second memory string stacked in the direction of extension of the channel structure, with the diameter of the channel structure of the first memory string gradually increasing from the bottom surface to the top surface of the first memory cell, and the diameter of the channel structure of the second memory string gradually increasing from the bottom surface to the top surface of the second memory string.

In one embodiment of the present disclosure, the diameter of the channel structure at the top surface of the first memory string is greater than the diameter of the channel structure at the bottom surface of the second memory cell.

In one embodiment of the present disclosure, the three-dimensional memory is 3D NAND flash.

According to the disclosed three-dimensional memory and control method thereof, a first pass voltage lower than the normal pass voltage is applied to memory cells having a relatively small diameter channel structure, thereby reducing read disturbance in this portion of the memory cell. In addition, in the program verification phase, a relatively low first pass voltage is applied to memory cells having a relatively small open channel structure, thereby further reducing read disturbance in this portion of the memory cell and increasing the reliability of the three-dimensional memory.

In order to make the above-mentioned objectives, features, and advantages of the present disclosure clearer and easier to understand, specific implementation forms of the present disclosure will be described in detail below in conjunction with the drawings.

FIG. 1 is a structural diagram of a portion of a three-dimensional memory having multiple decks. FIG. 1 is a distribution diagram of threshold voltages of memory cells in a three-dimensional memory. FIG. 1 is a distribution diagram of threshold voltages of memory cells in a three-dimensional memory. FIG. 1 is a schematic diagram of the effect of read disturb on E0 margin. 1 is an exemplary flow diagram of a method for controlling a three-dimensional memory according to an embodiment of the present disclosure. 1 is a schematic diagram of an implementation of a control method for a three-dimensional memory according to an embodiment of the present disclosure. 1 is a schematic diagram of an implementation of a control method for a three-dimensional memory according to an embodiment of the present disclosure. 1 is a schematic diagram of an implementation of a control method for a three-dimensional memory according to an embodiment of the present disclosure. 1 is a schematic diagram of an implementation of a control method for a three-dimensional memory according to an embodiment of the present disclosure. 1 is a schematic diagram illustrating the effect of a control method for a three-dimensional memory according to an embodiment of the present disclosure. 1 is a schematic diagram of an implementation of a control method for a three-dimensional memory according to an embodiment of the present disclosure. 1 is a schematic diagram of an implementation of a control method for a three-dimensional memory according to an embodiment of the present disclosure. 1 is a schematic diagram of an implementation of a control method for a three-dimensional memory according to an embodiment of the present disclosure. 1 is a schematic diagram of an implementation of a control method for a three-dimensional memory according to an embodiment of the present disclosure. FIG. 2 is a modular diagram of a three-dimensional memory according to an embodiment of the present disclosure. FIG. 2 is a circuit schematic diagram of a memory block that can be used in certain embodiments of the present disclosure.

In order to make the above-mentioned objectives, features, and advantages of the present disclosure clearer and easier to understand, specific implementation forms of the present disclosure will be described in detail below in conjunction with the drawings.

The following detailed description provides more specific details for a thorough understanding of the present disclosure. However, the present disclosure may be implemented in ways other than those described herein. Thus, the present disclosure is not limited to the specific embodiments disclosed below.

As used herein and in the claims, terms such as "a," "an," and/or "the" are not intended to refer to the singular, but rather to include the plural, unless otherwise clearly indicated in the text. In general, the terms "comprise" and "conclude" indicate only that the method or apparatus includes the specifically identified steps and elements, not an exclusive enumeration, and that the method or apparatus may include other steps or elements.

When describing the embodiments of the present disclosure in detail, for convenience of illustration, cross-sectional views showing device structures are partially enlarged and not to scale, and schematic diagrams are merely illustrative and do not limit the scope of protection of the present disclosure herein. Furthermore, the three-dimensional spatial dimensions of length, width, and depth should be included in the actual fabrication.

Spatial relationship terms such as "under," "below," "lower," "beneath," "above," and "on" may be used herein for convenience of description to describe the relationship of an element or feature to another element or feature as shown in the figures. It is understood that these spatial relationship terms are intended to include orientations of the device other than as shown in the figures in use or operation. For example, if a device in a figure is flipped, the orientation of an element described as being "below," or "under," or "beneath" another element or feature will change to being "above" the other element. Thus, the representative terms "below" and "beneath" can include an upward and downward orientation. The device may be otherwise oriented (rotated 90 degrees or otherwise) and therefore the spatial relationship terms as used herein should be interpreted accordingly. Also, when a layer is said to be "between" two layers, it is understood that it may be the only layer between the two layers, or there may be one or more layers intervening between them.

In the context of this application, a structure in which a first feature is "over" a second feature can include embodiments in which the first feature and the second feature are in direct contact, and can also include embodiments in which another feature is formed between the first feature and the second feature, such that the first feature and the second feature are not in direct contact.

It should also be noted that the terms "first", "second", etc., used to define components are merely for the convenience of distinguishing corresponding components. Unless otherwise specified, the terms described above do not have any specific meaning and therefore are not considered to limit the scope of protection of this application.

As used herein, the term "three-dimensional (3D) memory element" refers to a semiconductor element in which memory cell transistor strings (referred to herein as "memory strings", such as NAND strings) are oriented perpendicular to a horizontal substrate such that the memory strings extend perpendicular to the substrate. As used herein, the term "vertical" means nominally perpendicular to the sides of the substrate.

As used herein, the term "substrate" refers to a material onto which a layer of material is subsequently added. The substrate itself may be patterned. The material added to the top surface of the substrate may be patterned or may remain unpatterned. Additionally, substrates may include a wide range of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, substrates may be made of non-conductive materials such as glass, plastic, or sapphire wafers.

As used herein, the term "layer" refers to a portion of material that includes a region of thickness. A layer may span the entirety of an underlying or overlying structure, or may extend less than the extent of the underlying or overlying structure. Additionally, a layer may be a uniform continuous structure whose thickness is less than the thickness of the continuous structure, or a region of a non-uniform continuous structure. For example, a layer may be between any pair of horizontal surfaces between the top and bottom surfaces of a continuous structure, or on the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and/or along tapered surfaces. A substrate may be a layer and may include one or more layers therein and/or have one or more layers on, above, and/or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductor and contact layers (with contacts, interconnect lines, and/or via holes formed therein) and one or more insulating layers.

Flow diagrams are used in this application to illustrate operations performed by the system according to embodiments of the application. It should be understood that the operations described above or below do not necessarily have to be performed in order. Conversely, the steps may be processed in reverse order or simultaneously. Alternatively, other operations may be added to these processes, or alternatively, any one or more steps of the operations may be removed from these processes.

Figure 1 is a structural diagram of a part of a three-dimensional memory with multiple decks. Looking at Figure 1, the three-dimensional memory has two decks, a first deck 110 and a second deck 120. In each deck, a stack structure 111, 121 is formed by alternating layers of gate layers and insulating layers, and a channel hole structure 112, 121 is formed in the stack structure 111, 121. As shown in Figure 1, in the first deck 110, the opening on the top surface 114 of the channel hole structure 112 is larger than the opening on the bottom surface 113. In the second deck 120, the opening on the top surface 124 of the channel hole structure 122 is larger than the opening on the bottom surface 123. At the interface between the first deck 110 and the second deck 120, the opening of the channel hole on the bottom surface 113 of the first deck 110 is smaller than the opening of the channel hole on the top surface 124 of the second deck 120.

In an actual three-dimensional memory structure, the opening of the channel hole becomes gradually smaller from the top to the bottom of the channel hole in the direction of expansion of the channel hole structure. As the number of stack layers in the stack structures 111, 121 increases, the channel hole structures 112, 122 become gradually deeper and their depth-to-width ratios gradually increase, gradually widening the difference between the openings at the top and bottom of the channel holes 112, 122.

2A and 2B are distribution diagrams of threshold voltages of memory cells in a three-dimensional memory, where the horizontal axis represents the threshold voltage Vt and the vertical axis represents the number of memory cells. In FIGS. 2A and 2B, a multi-level cell (MLC) technology is taken as an example, according to which each memory cell stores two bits of information, namely, 00, 01, 10, and 11. The threshold voltages of memory cells may have four states, namely, E state, P1 state, P2 state, and P3 state, as shown in FIGS. 2A and 2B. Among them, E state is an erase state corresponding to an erase action whose corresponding data format is 11, and P1 state, P2 state, and P3 state are program states corresponding to program actions whose corresponding data formats are 00, 01, and 10, respectively.

Figure 2A is a distribution diagram of threshold voltages under normal conditions. Looking at Figure 2A, there are multiple margins between each state, for example, the margin distance between the E state and the P1 state, which is divided into E0 margin and E1 margin, where the E0 margin is closer to the E state and the E1 margin is closer to the P1 state. Similarly, the margin distance between the P1 state, the P2 state, and the P3 state is divided into E2 margin, E3 margin, E4 margin, and E5 margin.

When a read operation is performed on memory cells, a read voltage (Vread) is applied to the gate of the read memory cell, which means that these memory cells are in a turned-on state, and a pass voltage ( _Vpass ) is applied to the other memory cells on the same memory string as the read memory cell. The pass voltage is also called a transmission voltage or a turn-on voltage. A memory string may be regarded as a memory cell string distributed along a channel hole structure, as shown in FIG. 1. For the small opening memory cells at the bottom of the channel hole structure, the pass voltage will bring about a high electric field strength and a strong tunnel effect, which will bring about a certain program effect on the memory cells. Especially, the erased memory cells are susceptible to the program effect of the pass voltage due to their low threshold voltage, which will make the erased state E-state distribution wider, for example, as shown in FIG. 2B.

Figure 2B is a distribution diagram of threshold voltages when the voltage distribution of the erased state is expanding. Looking at Figure 2B, the voltage distribution of the E0 state expands toward the P1 state, resulting in a reduction in the E0 margin. Due to the reduction in the E0 margin, there is a possibility that a memory cell in the E state may be read erroneously, which may result in a read disturb and a reduction in the reliability of data storage.

Figure 3 is a schematic diagram of the effect of read disturb on E0 margin. As shown in Figure 3, the horizontal axis represents the number of word lines (WL) of the 3D memory from 0 to 127, indicating that the 3D memory is a 128-layer 3D NAND flash. The 3D memory also has two decks as shown in Figure 1. The vertical axis of Figure 3 represents the width value of the E0 margin, which is the median value of several test results. Looking at Figure 3, the left half 310 of the horizontal axis represents the original state (fresh) of the memory cell that has not been programmed, and the right half 320 represents the state of the memory cell after 300 cycles (300 cyc) of programming.

Looking at FIG. 3, the left half 310 and the right half 320 each have four curves corresponding to various read times. Among them, the read time corresponding to curves 311 and 321 is 0, the read time corresponding to curves 312 and 322 is 1000, the read time corresponding to curves 313 and 323 is 3000, and the read time corresponding to curves 314 and 324 is 30000. Obviously, as the read time increases, the E0 margin gradually shrinks. FIG. 3 corresponds to the three-dimensional memory with two decks shown in FIG. 1, where the word line number 0 to 63 belongs to the first deck, the number gradually increases from the bottom surface of the channel hole structure upward, and the word line number 64 to 127 belongs to the second deck.

In the context of Figures 1 and 3, taking the left half 310 as an example, the word line number 0 corresponds to the memory cells at the bottom of the channel hole structure. After several read operations, the size of the E0 margin of the memory cells in the first deck increases with increasing word line number (0-63), and the size of the E0 margin of the memory cells in the second deck also increases with increasing word line number (64-127). Thus, the E0 margin of the memory cells at the bottom of the deck is smallest, e.g., the first range 315 and the second range 316 surrounded by dotted circles in Figure 3, which correspond to the memory cells at the bottom of the first deck and the memory cells at the bottom of the second deck, respectively.

In the right half 320, the E0 margin of the memory cells after 300 cycles of programming is somewhat smaller than the E0 margin of the memory cells in their original state without programming. In addition, similar to the left half 310, the E0 margin of the memory cells at the bottom of the first deck and at the bottom of the second deck is relatively small, for example, the third range 317 and the fourth range 318 enclosed by the dotted circle in FIG. 3.

4 is an exemplary flow chart of a control method for a three-dimensional memory according to an embodiment of the present disclosure. The three-dimensional memory includes a plurality of memory strings, each memory string includes a plurality of memory cells having a first portion and a second portion, and a diameter of a channel structure corresponding to the first portion of the memory cell is smaller than a diameter of a channel structure corresponding to the second portion of the memory cell. Looking at FIG. 4, the control method of this embodiment includes:
Step S410: applying pass voltages to unselected memory cells when performing a read operation on a selected memory cell, including applying a first pass voltage to a first unselected memory cell of a first portion and applying a second pass voltage to a second unselected memory cell of a second portion, the first pass voltage being lower than the second pass voltage.

In some implementations, memory cells in a memory string of a three-dimensional memory are coupled to corresponding word lines to which a pass voltage is applied, thereby providing the effect of applying a bus voltage to the memory cells.

In some embodiments, when a read operation is performed on a selected memory cell, a read voltage is applied to the word line of the selected memory cell.

Figures 5A-5D are schematic implementation diagrams of a control method for a three-dimensional memory cell according to an embodiment of the present disclosure. The control method shown in Figure 4 is described below in conjunction with Figures 5A-5D.

Looking at Figure 5A, a structural diagram of a 128-layer 3D memory with two decks is shown. The 3D memory includes a first deck 510 located at the bottom and a second deck 520 located at the top. The first deck 510 includes 64 gate layers WL0-WL63, and the second deck 520 also includes 64 gate layers WL64-WL127. The 3D memory further includes some virtual gate layers 530 between the first deck 510 and the second deck 520, which do not provide any real gate effect. It can be seen that in the structure of the 3D memory, word lines are connected to gate layers, and a voltage can be applied through the word lines to the gate layers connected to the word lines. In Figures 5A-5D, WL (word lines) is used to represent the names of gate layers connected to different word lines.

In this embodiment, as shown in FIG. 1, the diameter of the channel structure corresponding to the memory cell is the opening of the channel hole structure.

In relation to Figures 1-5A, the openings of the channel structures corresponding to the memory cells associated with the bottom several gate layers in the first deck 510 are relatively small, assuming that the number of gate layers is about 15-20, i.e., assuming that the gate layers in which the first portion of the memory cells are located are WL0-WL14 to WL0-WL19.

This disclosure does not limit the number of memory cells in the first and second parts, nor the number of corresponding gate layers. In the actual implementation of the control method, the range of gate layers in which the first and second parts of the memory cells are located can be set as needed.

This disclosure will be explained using 16 layers as an example. Looking at FIG. 5A, the memory cells corresponding to WL0-WL15 and WL65-WL79 belong to the first part in step S410, and the memory cells outside the gate layer belong to the second part.

To explain step S410, we will explain it according to the number of gate layers in which the selected memory cell is located.

In FIG. 5A, the selected memory cell 540 is located at WL0-WL23, and the memory cells located in the other gate layers, including WL24-WL127, are unselected memory cells. When a read voltage Vread is applied to the selected memory cell 540, a pass voltage Vpass is applied to the other unselected memory cells. Of these unselected memory cells, the memory cells located at WL64-WL78 belong to a first portion, and the unselected memory cells in this portion are referred to as first unselected memory cells 550. The other unselected memory cells, including the memory cells located at WL24-WL63 and WL79-WL127, belong to a second portion, and these unselected memory cells are referred to as second unselected memory cells 560. According to step S410, a first pass voltage Vpass1 is applied to a first unselected memory cell 550 belonging to the first portion, and a second pass voltage Vpass2 is applied to a second unselected cell memory 560 belonging to the second portion, where Vpass1<Vpass2.

It should be noted that the selected memory cell 540 in WL0-WL23 means that the selected memory cell 540 is located in any one or more layers of WL0-WL23. The selected memory cell 540 may be located in different memory strings, but the diameter of the channel structure corresponding to the memory cell 540 in the same gate layer but in different memory strings is approximately the same. If the selected memory cell 540 is in layer WL15, then pass voltages are applied to the memory cells on the gate layers WL0-WL23 except WL15 according to the principle of step S410 as well, that is, according to the principle that the first pass voltage Vpass1 is applied to WL0-WL14 belonging to the first part, and the second pass voltage Vpass2 is applied to WL16-WL23 belonging to the second part.

In FIG. 5B, the selected memory cell 540 is located at WL24-WL55, and the memory cells located at the other gate layers are unselected memory cells. When a read voltage Vread is applied to the selected memory cell 540, a pass voltage Vpass is applied to the other unselected memory cells. Among these unselected memory cells, a first unselected memory cell 550 includes memory cells located at gate layers WL0-WL15 and WL64-WL79, and a second unselected memory cell 560 includes memory cells located at gate layers WL16-WL23, WL56-WL63, and WL80-WL127. According to step S410, a first pass voltage Vpass1 is applied to the first unselected memory cell 560, where Vpass1<Vpass2.

In FIG. 5C, the selected memory cells are WL56-WL87, and the memory cells located in the other gate layers are unselected memory cells. When a read voltage Vread is applied to the selected memory cell 540, a pass voltage Vpass is applied to the other unselected memory cells. Among these unselected memory cells, a first unselected memory cell 550 includes memory cells located in gate layers WL0-WL15, and a second unselected memory cell 560 includes memory cells located in gate layers WL16-WL55 and WL88-WL127. According to step S410, a first pass voltage Vpass1 is applied to the first unselected memory cell 550, and a second pass voltage Vpass2 is applied to the second unselected memory cell 560, where Vpass1<Vpass2.

In FIG. 5D, the selected memory cell 540 is WL88-WL127, and the memory cells located in the other gate layers are unselected memory cells. When the read voltage Vread is applied to the selected memory cell 540, the pass voltage Vpass is applied to the other unselected memory cells. Among these unselected memory cells, the first unselected memory cell 550 includes memory cells located in the gate layers WL0-WL15 and WL64-WL79, and the second unselected memory cell 560 includes memory cells located in the gate layers WL16-WL63 and WL80-WL87. According to step S410, the first pass voltage Vpass1 is applied to the first unselected memory cell 550, and the second pass voltage Vpass2 is applied to the second unselected memory cell 560, where Vpass1<Vpass2.

In the above embodiment, the second pass voltage may be a standard voltage that is normally used, for example, Vpass2 = 6.5 to 7 V. The first pass voltage is lower than the standard pass voltage, for example, Vpass = 6 to 6.5 V. The first pass voltage Vpass1 is about 0.5 V lower than the second pass voltage Vpass2.

Figure 6 is a schematic diagram of the effect of a control method for a three-dimensional memory according to an embodiment of the present disclosure. Looking at Figure 6, its horizontal axis represents the number of word lines of the three-dimensional memory from 0 to 127, and its vertical axis represents the width of the E0 margin. Figure 6 is an example of the average value of the E0 margin obtained after 30,000 read operation cycles. Curve 610 shows the state where the second pass voltage Vpass2 is applied to all of the unselected cells, and curve 620 shows the state where the first pass voltage Vpass1 is applied to the first unselected memory cell and the second pass voltage Vpass2 is applied to the second unselected memory cell.

In an embodiment as seen in FIG. 6, Vpass1=6.2V and Vpass2=6.6V. As can be seen in FIG. 6, for memory cells near WL0-WL16 at the bottom of the channel structure, the Y-axis value of curve 620 is greater than the Y-axis value of curve 610, i.e., the method of the present disclosure provides a greater E0 margin for memory cells near WL0-WL16.

According to the above-described three-dimensional memory control method, a first pass voltage that is lower than the standard pass voltage is applied to a memory cell having a relatively small diameter channel structure, thereby mitigating read disturb in this portion of the memory cell.

Referring to FIG. 4, in some embodiments, the control method for a three-dimensional memory of the present disclosure further includes:
STEP 420: applying a second pass voltage to second unselected memory cells when a program verify operation is performed on the selected memory cells, and applying the first pass voltage to the first unselected memory cells if the first unselected memory cells are in a programmed state and applying the second pass voltage to the first unselected memory cells if the first unselected memory cells are in an erased state. STEP 420 is described below in conjunction with Figures 7A-7D.

In some embodiments, when a program verify operation is performed on a selected memory cell, a program verify voltage is applied to the word line of the selected memory cell.

Figures 7A-7D are schematic diagrams illustrating an implementation of a method for controlling a three-dimensional memory according to an embodiment of the present disclosure. Figures 7A-7D are examples of four situations, each with a different number of gate layers in which a selected memory cell is located.

...

In FIG. 7A, the selected memory cell 740 is located at WL0-WL23, and the memory cells located in the other gate layers, including WL24-WL127, are unselected memory cells. When the program verify voltage Vverify is applied to the selected memory cell 740, the pass voltage Vpass is applied to the other unselected memory cells.

In some embodiments, each memory cell is located at a corresponding cell depth in the memory string, and a page of memory cells located at the same cell depth is programmed through word lines layer by layer in the direction of the memory string channel structure. Referring to FIG. 7A, in this embodiment, the number of word lines increases layer by layer in a first direction D1 that also corresponds to the direction of the memory string channel structure. WL0 corresponds to the bottom surface of the channel structure, and WL127 corresponds to the top surface of the channel structure. WL0 corresponds to the bottom surface of the channel structure of the first deck 710, WL63 corresponds to the top surface of the channel structure of the first deck 710, WL64 corresponds to the bottom surface of the channel structure of the second deck 720, and WL127 corresponds to the top surface of the channel structure of the second deck 720.

Memory cells in the same gate layer have the same cell depth, and memory cells at the same cell depth form a page of a three-dimensional memory. In an embodiment such as that shown in Figures 7A-7D, programming begins at the bottom layer WL0 and proceeds upwards, layer by layer.

During a program operation (which may also be considered as writing data), the memory cells are programmed according to a word line program order or other program rules. For example, the program operation may start with the word lines on the source side of the memory block and continue with the word lines on the drain side of the memory block. In one program rule, as each word line is programmed, the next word line is programmed (i.e., programmed within the page). During a program operation, in the 3D memory, one or more layers are selected as selected layers, a program voltage is applied to the selected layers, and no bit line voltage is applied to the bit lines corresponding to the selected strings, i.e., the bit lines corresponding to the selected strings are considered as the selected strings to be programmed, while the rest of the memory strings are inhibited.

Referring to FIG. 7A, the selected memory cell 740 is located in gate layers WL0-WL23, which may be one or more layers among them. In this case, the other gate layers WL24-WL127 have not been programmed and are in an erased state. Therefore, the pass voltage Vpass applied to the unselected memory cells in WL24-WL127 is the second pass voltage Vpass2.

In FIG. 7B, the selected memory cell 741 is WL24-WL55, and the memory cells located in the other gate layers are unselected memory cells. When the program verify voltage Vverify is applied to the selected memory cell 741, the other unselected memory cells are applied with the pass voltage Vpass. Among these unselected memory cells, the second unselected memory cell 761 is applied with the second pass voltage Vpass2. As can be seen in FIG. 7A, the first unselected memory cell 750 in the gate layers WL0-WL15 has been through a program operation and is in a programmed state, and therefore the first pass voltage Vpass1 is applied to the first unselected memory cell 750. The unselected memory cells 762 located in the gate layers WL56-WL127 are in an erased state, and therefore the second pass voltage Vpass2 is applied to these unselected memory cells 762, where Vpass1<Vpass2. The unselected memory cells 762 include first unselected memory cells WL64-WL79 belonging to the first portion and second unselected memory cells WL80-WL127 belonging to the second portion.

In FIG. 7C, the selected memory cell 742 is WL56-WL87, and the memory cells located in the other gate layers are unselected memory cells. When the program verify voltage Vverify is applied to the selected memory cell 742, the pass voltage Vpass is applied to the other unselected memory cells. Among these unselected memory cells, a second pass voltage Vpass2 is applied to a second unselected memory cell 763 comprising memory cells located in gate layers WL16-WL55 and WL88-WL127. The unselected memory cells further comprise a first unselected memory cell 750 located in gate layers WL0-WL15, and as can be seen in FIG. 7A, this first unselected memory cell 750 has undergone a program operation and is in a programmed state, and therefore a first pass voltage Vpass1 is applied to this first unselected memory cell 750.

In FIG. 7D, the selected memory cell 743 is WL88-WL127, and the memory cells located in the other gate layers are unselected memory cells. When the program verify voltage Vverify is applied to the selected memory cell 743, the pass voltage Vpass is applied to the other unselected memory cells. Among these unselected memory cells, a second pass voltage Vpass2 is applied to a second unselected memory cell 764 comprising memory cells located in gate layers WL16-WL63 and WL80-WL87. The unselected memory cells further comprise a first unselected memory cell 750 located in gate layers WL0-WL15 and a first unselected memory cell 751 located in gate layers WL64-WL79, and as can be seen in FIG. 7A, these unselected memory cells have undergone a program operation and are in a program state, and therefore a first pass voltage Vpass1 is applied to the first unselected memory cells 750, 751.

The application of the program verify voltage Vverify to the memory cell is equivalent to a read operation, which also results in read disturb for memory cells with relatively small apertures. By following the control method of the above embodiment, the read disturb of the program verify voltage can be reduced during that time.

FIGS. 7A-7D are example embodiments in which the programming operation begins with gate layer WL0 and proceeds layer-by-layer to WL127. In other embodiments, the programming operation may proceed layer-by-layer from gate layer WL127 downward to WL0, and the above method of operation also applies to these embodiments.

Figure 8 is a module diagram of a three-dimensional memory according to an embodiment of the present disclosure. The three-dimensional memory of this embodiment can be controlled using the control method of the three-dimensional memory described above in this disclosure, and therefore the three-dimensional memory of this disclosure can be depicted using all of the drawings and embodiments for implementing the invention described above.

Looking at FIG. 8, the three-dimensional memory includes a memory cell array 810 and a controller 820. The memory cell array 810 includes a plurality of memory strings, each of which includes a plurality of memory cells that extend vertically on a substrate and are vertically arranged in series connection. The plurality of memory cells include a first portion and a second portion, and the diameter of the channel structure of the first portion of the memory cell is smaller than the diameter of the channel structure of the second portion of the memory cell. The controller 820 is configured to apply a pass voltage Vpass to the unselected memory cells when a read operation is performed on the selected memory cell, where a first pass voltage Vpass1 is applied to the first unselected memory cell in the first portion, and a second pass voltage Vpass2 is applied to the second unselected memory cell in the second portion, and the first pass voltage Vpass1 is lower than the second pass voltage Vpass2.

In some embodiments, the controller 820 is further configured to apply a second pass voltage Vpass2 to the second unselected memory cell when a program verify operation is performed on the selected memory cell, apply a first pass voltage Vpass1 to the first selected memory cell if the first unselected memory cell is in a programmed state, and apply a second pass voltage Vpass2 to the first unselected memory cell if the first unselected memory cell is in an erased state.

The controller 820 can implement the functions described above using the control method for the three-dimensional memory of the present disclosure, and therefore the specific functions of the controller 820 of the three-dimensional memory of the present disclosure can be described using the drawings and the description for implementing the invention described above. If the contents are the same, they will not be described further.

In this embodiment, each memory cell included in the memory cell array 810 may be a single-level cell (SLC: Single-Level Cell) that stores one bit of data, a multi-level cell (MLC: Multi-Level Cell) (such as MLC, TLC, and QLC) that can store two or more bits of data, or any combination of single-level cells and multi-level cells.

In this embodiment, the memory cells in the memory cell array 810 can be connected to the word lines WL and the bit lines BL. Meanwhile, the memory cell array 810 can also be connected to other selection lines, such as the string selection line SSL and the ground selection line GSL. Specifically, the memory cell array 810 can be connected to the word line decoder 850 through the word lines WL or the selection lines (SSL and/or GSL) and further connected to the voltage generator 860. The memory cell array 810 can be connected to the bit line decoder 830 through the bit lines BL and further connected to the input/output (I/O) circuit 840. The controller 820 is connected to the bit line decoder 830, the I/O circuit 840, the word line decoder 850, and the voltage generator 860, respectively.

When an erase, program, read-write, or verify operation needs to be performed on one or more memory cells, the controller 820 can send the addresses of the one or more memory cells via the bit lines BL for addressing by the bit line decoder 830 and via the word lines WL for addressing by the word line decoder 850.

In some embodiments, the functions of bit line decoder 830 and word line decoder 850 may be performed by a unified address decoder. The address decoder may further include components such as an address buffer.

On the one hand, the I/O circuit 840 can receive data from the controller 820 and/or the outside and store the received data in the memory cell array 810 for a write operation, and on the other hand, it can read data from the memory cell array 810 and output the read data to the controller 820 and/or the outside for a read operation.

The voltage generator 860 can generate various voltages to perform erase, program, read-write, and verify operations on the memory cell array 810 upon receiving control signals from the controller 820. In particular, the voltage generator 860 can generate word line voltages, such as program voltages (i.e., write voltages), program inhibit voltages, read voltages, and verify voltages. The voltage generator 860 can generate bit line voltages, such as bit line applied voltages or blocking voltages. In this embodiment of the present disclosure, the voltage generator 860 can generate the pass voltages Vpass (including the first pass voltage Vpass1 and the second pass voltage Vpass2), read voltages Vread, and program verify voltages Vverify, as described above.

The controller 820 can output control signals to the bit line decoder 830, the I/O circuit 840, the word line decoder 850, and the voltage generator 860. For example, the controller 820 can output voltage control signals to the voltage generator 860, output word line addresses to the word line decoder 850, output bit line addresses to the bit line decoder 830, output write data to the I/O circuit 840, and receive read data from the I/O circuit 840.

In some embodiments, the controller 820 controls the bit line decoder 830 to select some bit lines BL and the word line decoder 850 to select some word lines WL, and applies a constant voltage to these bit lines BL and word lines WL through the voltage generator 860. For example, during a read operation, a read voltage may be applied to the selected word lines WL, and for memory cells that are blocked from being read, a read blocking voltage may be applied to the unselected bit lines BL. During a program operation, a program voltage and a verify voltage may be applied to the selected word lines WL, and a program blocking voltage is applied to the unselected bit lines BL.

The controller 820 of this embodiment of the disclosure may further include components such as a processor, an I/O interface, etc. The control logic of the controller 820 for the bit line decoder 830, the I/O circuitry 840, the word line decoder 850, and the voltage generator 860 is not limited to that described above. The controller 820 may perform other logical control functions for the non-volatile memory as would be understood by one of ordinary skill in the art.

In some embodiments, the controller 820 can indicate, based on software, the memory operations that the memory cell array 810 needs to perform.

In this embodiment of the disclosure, the memory strings extend vertically on a substrate. The substrate may be a silicon substrate (Si), a germanium substrate (Ge), a silicon germanium substrate (SiGe), a silicon on insulator (SOI), a germanium on insulator (GOI), etc. In some embodiments, the substrate may also be a substrate including other elemental or compound semiconductors such as GaAs, InP, or SiC. The substrate may also be a stack structure such as Si/SiGe. The substrate may further comprise other epitaxial structures such as SiGe on insulator (SGOI). In some embodiments, the substrate may be made of a non-conductive material such as glass, plastic, or a sapphire wafer. The substrate may undergo some necessary processing, such as forming a common active area, performing necessary cleaning, etc.

The stack structure may be disposed on the substrate, and the stack structure may be a stack formed by alternating lamination of a first material layer and a second material layer. The first material layer and the second material layer may be selected from the following materials, which may include at least one insulator, such as silicon nitride, silicon oxide, amorphous carbon, diamond-like amorphous carbon, germanium oxide, aluminum oxide, and the like, and combinations thereof. The first material layer and the second material layer have different etching selectivities. For example, they may be a combination of silicon nitride and silicon oxide, a combination of silicon oxide and undoped polysilicon or amorphous carbon, a combination of silicon oxide or silicon nitride and amorphous carbon, and the like. The deposition methods of the first and second material layers of the stack structure can include chemical vapor deposition (CVD, PECVD, LPCVD, and HDPCVD), atomic layer deposition (ALD), or physical vapor deposition methods such as molecular beam epitaxy (MBE), thermal oxidation, evaporation, sputtering, and various other methods. In this embodiment of the present disclosure, the first material layer can be a gate layer and the second material layer can be an insulating layer. The gate layer can be formed after removal of the dummy gate layer. The material of the gate sacrificial layer can be, for example, a silicon nitride layer. The material of the gate layer can be a conductive material such as metallic tungsten, cobalt, copper, nickel, and can be polysilicon, doped silicon, or any combination thereof. The material of the insulating layer may be, for example, silicon oxide, aluminum oxide, hafnium oxide, tantalum oxide, etc.

In this embodiment of the present disclosure, the material of the substrate may be, for example, silicon. The first material layer and the second material layer may be, for example, a combination of silicon nitride and silicon oxide. Taking the combination of silicon nitride and silicon oxide as an example, the silicon nitride and silicon oxide can be alternately deposited on the substrate in a continuous manner by chemical vapor deposition (CVD), atomic layer deposition (ALD), or other suitable deposition methods to form a stack structure.

Although representative compositions of the initial semiconductor structure are described herein, it is understood that one or more features may be removed, replaced, or added to such semiconductor structure. For example, various well regions may be formed in the substrate as desired. Also, the exemplary materials for each layer are merely exemplary, and for example, the substrate may be other silicon-containing substrates such as SOI (silicon on insulator), SiGe, Si:C, etc. The gate layer may also be other conductive layers, such as metallic tungsten, cobalt, nickel, etc. The second material may also be other insulating materials, such as aluminum oxide, hafnium oxide, tantalum oxide, etc.

A channel structure corresponding to a memory cell may be formed in a channel hole that penetrates the stack structure vertically. The channel structure may therefore be cylindrical. The channel structure may comprise a channel layer or a memory layer. In general, the memory layer and the channel layer are arranged in the radial direction of the channel structure from the outside to the inside without interruption. The memory layer may comprise a blocking layer, a charge trapping layer, and a tunnel layer that are deposited in the radial direction of the channel structure from the outside to the inside without interruption. A filling layer may also be arranged in the channel layer. The filling layer may act as a support. The material of the filling layer may be silicon oxide. The filling layer may be solid or hollow, provided that it does not have any effect on the device reliability. The formation of the channel structure may be performed by one or more film deposition processes, such as ALD, CVD, PVD, etc., or any combination thereof.

In some embodiments, the three-dimensional memory of the present disclosure further comprises a plurality of word lines, each of which is coupled to a page of memory cells of the same cell depth, each memory cell being located at a corresponding cell depth in the message string.

Figure 9 is a circuit schematic diagram of a memory block that can be used in this embodiment of the disclosure. A memory cell array 810 as seen in Figure 8 may comprise multiple memory blocks. Looking at Figure 9, MC (memory cell) represents a memory cell, and the cell depth of each memory cell corresponds. For example, the memory cell MC in Figure 9 is located in a gate layer connected to the word line WL8. The memory string STR seamlessly connects multiple memory cells in a direction in which the number of word line layers WL1-WL8 increases gradually. Memory cells with the same cell depth are located in the same page. The controller 820 controls the voltage generator 860 to generate voltages applied to each word line according to the settings, thereby controlling the voltages applied to each memory cell.

Each string STR may further include a string select transistor SST and a ground select transistor GST, each connected across the continuously connected memory cells MC. GSL stands for common source line. The number of memory strings STR, word lines WL, and bit lines BL may vary depending on the embodiment.

Figure 9 is merely an example and does not limit the actual structure or number of word line layers of the three-dimensional memory of the present disclosure.

In some embodiments, the diameter of the channel structure of the memory string of the present disclosure gradually increases from the bottom surface to the top surface of the memory string.

In some embodiments, the first portion of the memory cell is located below the second portion of the memory cell.

In some embodiments, the memory string comprises a first memory string and a second memory string stacked in the direction of the spread of the channel structure, the diameter of the channel structure of the first memory string gradually increasing from the bottom surface to the top surface of the first memory string, and the diameter of the channel structure of the second memory string gradually increasing from the bottom surface to the top surface of the second memory string. The diameter of the channel structure at the top surface of the first memory string may be larger than the diameter of the channel structure at the bottom surface of the second memory string. For the structure of the three-dimensional memory of these embodiments, reference can be made to FIG. 1, where the three-dimensional memory comprises more than two decks, each of which comprises a channel structure having a smaller diameter at the bottom surface and a larger diameter at the top surface.

In some embodiments, the three-dimensional memory cell of the present disclosure is a 3D NAND flash.

In the three-dimensional memory disclosed herein, during a read operation, a relatively low first pass voltage is applied to the memory cell having a small open channel structure, thereby effectively reducing read disturbance of this portion of the memory cell, and during the program verify phase, a relatively low first pass voltage is also applied to the memory cell having a small open channel structure, thereby further reducing read disturbance of this portion of the memory cell and increasing the reliability of the three-dimensional memory.

Although the present disclosure has been described with reference to specific embodiments at present, those skilled in the art should understand that the above embodiments are merely used to illustrate the present disclosure, and that various equivalent modifications and substitutions may be made without departing from the spirit of the present disclosure. Therefore, variations and variants of the above-described embodiments are within the scope of the claims of this application, so long as they fall within the substantial spirit of the present disclosure.

110 First deck 111 Stack structure 112 Channel hole structure 113 Bottom surface 114 Top surface 120 Second deck 121 Stack structure 122 Channel hole structure 123 Bottom surface 124 Top surface 310 Left half 311 Curve 313 Curve 314 Curve 315 First area 316 Second area 320 Right half 510 First deck 520 Second deck 540 Selected memory cell 550 First unselected memory cell 560 Second unselected memory cell 610 Curve 620 Curve 710 First deck 720 Second deck 740 Selected memory cell 741 Selected memory cell 742 Selected memory cell 743 Selected memory cell 750 First unselected memory cell 751 First unselected memory cell 761 Second unselected memory cell 762 Unselected memory cell 763 Second unselected memory cell 764 Second unselected memory cell 810 Memory cell array 820 Controller 830 Bit line decoder 840 Input/output (I/O) circuit 850 Word line decoder 860 Voltage generator

Claims (12)

A method of controlling a three-dimensional memory, the three-dimensional memory comprising a first deck and a second deck stacked in a vertical direction of a substrate, the first deck and the second deck each comprising a plurality of memory strings, each memory string comprising a plurality of memory cells, the plurality of memory cells comprising a first portion and a second portion, a diameter of a channel structure corresponding to the first portion of the memory cells being smaller than a diameter of a channel structure corresponding to the second portion of the memory cells, the method comprising:
performing a read operation on selected memory cells in at least one of the first deck or the second deck;
applying pass voltages to unselected memory cells other than the selected memory cell in the first deck and the second deck, the pass voltages comprising a first pass voltage and a second pass voltage, the first pass voltage being lower than the second pass voltage, the first pass voltage being applied to a first unselected memory cell in the first portion, and the second pass voltage being applied to a second unselected memory cell in the second portion;
performing a program verify operation on the selected memory cell;
A control method comprising: applying the pass voltage to unselected memory cells other than the selected memory cell in the first deck and the second deck, wherein the second pass voltage is applied to the second unselected memory cells, the pass voltage applied being determined according to a state of the first unselected memory cells, and if the first unselected memory cells are in a programmed state, the first pass voltage is applied to the first unselected memory cells, and if the first unselected memory cells are in an erased state, the second pass voltage is applied to the first unselected memory cells . The control method of claim 1, wherein the memory cells in the memory string are coupled to corresponding word lines, and the pass voltage is applied to the memory cells through the corresponding word lines. The control method of claim 2 , wherein a read voltage is applied to a word line of the selected memory cell when the read operation is performed on the selected memory cell. 3. The method of claim 2 , wherein a program verify voltage is applied to the word line of the selected memory cell when a program verify operation is performed on the selected memory cell. 3. The control method of claim 2, wherein each memory cell is at a corresponding cell depth in the memory string, and a program operation is performed on a page of memory cells at the same cell depth through the word line in a layer-by-layer manner in the direction of extension of a channel structure of the memory string . A three-dimensional memory,
a memory cell array comprising a first deck and a second deck stacked vertically on a substrate, each of the first deck and the second deck comprising a plurality of memory strings, each memory string extending vertically above the substrate and comprising a plurality of memory cells arranged vertically in series connection;
the plurality of memory cells having a first portion and a second portion, the diameter of a channel structure of the first portion of the memory cell being smaller than a diameter of the channel structure of the second portion of the memory cell;
a controller configured to send a control signal to a voltage controller when a read operation is performed on a selected memory cell, the controller being responsive to the control signal to apply a pass voltage to unselected memory cells, the pass voltage comprising a first pass voltage and a second pass voltage, the first pass voltage being lower than the second pass voltage, the first pass voltage being applied to a first unselected memory cell of the first portion, and the second pass voltage being applied to a second unselected memory cell of the second portion ;
The three dimensional memory, wherein the controller is further configured to send a control signal to the voltage controller when a program verify operation is performed on a selected memory cell, and the voltage controller, in response to the control signal, applies the second pass voltage to the second unselected memory cell, applies the first pass voltage to the first unselected memory cell if the first unselected memory cell is in a programmed state, and applies the second pass voltage to the first unselected memory cell if the first unselected memory cell is in an erased state . 7. The three dimensional memory of claim 6 , further comprising a plurality of word lines, each of the word lines coupled to a page of memory cells at a same cell depth, each memory cell located at a corresponding cell depth in the memory string. The three dimensional memory of claim 6 , wherein the diameter of the channel structure of the memory string gradually increases from a bottom surface to a top surface of the memory string. The three dimensional memory of claim 6 , wherein a first portion of the memory cell is located below a second portion of the memory cell. 7. The three-dimensional memory of claim 6, wherein the memory strings include a first memory string and a second memory string stacked in a direction of extension of the channel structure, the diameter of the channel structure of the first memory string gradually increasing from a bottom surface to a top surface of the first memory string, and the diameter of the channel structure of the second memory string gradually increasing from a bottom surface to a top surface of the second memory string. 11. The three dimensional memory of claim 10 , wherein the diameter of the channel structure at the top surface of the first memory string is greater than the diameter of the channel structure at the bottom surface of the second memory string. The three dimensional memory of claim 6 , wherein the three dimensional memory is a 3D NAND flash.

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