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JP2021129042A - Semiconductor devices and their manufacturing methods - Google Patents

Semiconductor devices and their manufacturing methods Download PDF

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JP2021129042A
JP2021129042A JP2020023497A JP2020023497A JP2021129042A JP 2021129042 A JP2021129042 A JP 2021129042A JP 2020023497 A JP2020023497 A JP 2020023497A JP 2020023497 A JP2020023497 A JP 2020023497A JP 2021129042 A JP2021129042 A JP 2021129042A
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film
insulating film
layer
insulating
semiconductor device
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将希 野口
Masaki Noguchi
将希 野口
章 高島
Akira Takashima
章 高島
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Kioxia Corp
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Kioxia Corp
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Priority to TW109123196A priority patent/TWI794618B/en
Priority to CN202010758272.3A priority patent/CN113270420B/en
Priority to US17/019,662 priority patent/US11735673B2/en
Publication of JP2021129042A publication Critical patent/JP2021129042A/en
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B43/00EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/67Thin-film transistors [TFT]
    • H10D30/674Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • H10D30/6756Amorphous oxide semiconductors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B43/00EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B43/00EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/01Manufacture or treatment
    • H10D30/021Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0413Manufacture or treatment of FETs having insulated gates [IGFET] of FETs having charge-trapping gate insulators, e.g. MNOS transistors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/69IGFETs having charge trapping gate insulators, e.g. MNOS transistors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/40Crystalline structures
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/60Electrodes characterised by their materials
    • H10D64/66Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/691Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator comprising metallic compounds, e.g. metal oxides or metal silicates 

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  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
  • Formation Of Insulating Films (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)

Abstract

To provide a semiconductor device capable of improving performance of a block insulation film, and a method for manufacturing the same.SOLUTION: According to one embodiment, a semiconductor device comprises a laminated film alternately including a plurality of electrode layers and a plurality of insulation layers. The semiconductor device also comprises a first insulation film, a charge storage layer, a second insulation film, and a semiconductor layer provided in this order in the laminated film. The device further comprises a third insulation film provided between the electrode layers and the insulation layers and between the electrode layers and the first insulation film, and including an aluminum oxide film of an α crystal phase in the laminated film.SELECTED DRAWING: Figure 5

Description

本発明の実施形態は、半導体装置およびその製造方法に関する。 An embodiment of the present invention relates to a semiconductor device and a method for manufacturing the same.

3次元メモリのブロック絶縁膜は例えば、シリコン酸化膜に加えて、アルミニウム酸化膜などの金属絶縁膜を含むように形成される。ブロック絶縁膜の性能を向上させるためには、好適な金属絶縁膜を含むブロック絶縁膜を形成することが望まれる。 The block insulating film of the three-dimensional memory is formed so as to include, for example, a metal insulating film such as an aluminum oxide film in addition to the silicon oxide film. In order to improve the performance of the block insulating film, it is desired to form a block insulating film containing a suitable metal insulating film.

特開2009−132961号公報Japanese Unexamined Patent Publication No. 2009-132961 特開2009−55030号公報JP-A-2009-55030

Karl Wefers and Chanakya Misra, Alcoa Technical Paper, No.19, Revised(1987) Alcoa LaboratoriesKarl Wefers and Chanakya Misra, Alcoa Technical Paper, No.19, Revised (1987) Alcoa Laboratories

ブロック絶縁膜の性能を向上させることが可能な半導体装置およびその製造方法を提供する。 Provided are a semiconductor device capable of improving the performance of a block insulating film and a method for manufacturing the same.

一の実施形態によれば、半導体装置は、複数の電極層と複数の絶縁層とを交互に含む積層膜を備える。前記装置はさらに、前記積層膜内に順に設けられた第1絶縁膜、電荷蓄積層、第2絶縁膜、および半導体層を備える。前記装置はさらに、前記積層膜内において、前記電極層と前記絶縁層との間と、前記電極層と前記第1絶縁膜との間とに設けられ、α結晶相のアルミニウム酸化膜を含む第3絶縁膜を備える。 According to one embodiment, the semiconductor device includes a laminated film including a plurality of electrode layers and a plurality of insulating layers alternately. The device further includes a first insulating film, a charge storage layer, a second insulating film, and a semiconductor layer, which are sequentially provided in the laminated film. The device is further provided between the electrode layer and the insulating layer and between the electrode layer and the first insulating film in the laminated film, and includes an aluminum oxide film having an α crystal phase. 3 Insulating film is provided.

第1実施形態の半導体装置の構造を示す斜視図である。It is a perspective view which shows the structure of the semiconductor device of 1st Embodiment. 第1実施形態の半導体装置の製造方法を示す断面図(1/4)である。It is sectional drawing (1/4) which shows the manufacturing method of the semiconductor device of 1st Embodiment. 第1実施形態の半導体装置の製造方法を示す断面図(2/4)である。It is sectional drawing (2/4) which shows the manufacturing method of the semiconductor device of 1st Embodiment. 第1実施形態の半導体装置の製造方法を示す断面図(3/4)である。It is sectional drawing (3/4) which shows the manufacturing method of the semiconductor device of 1st Embodiment. 第1実施形態の半導体装置の製造方法を示す断面図(4/4)である。It is sectional drawing (4/4) which shows the manufacturing method of the semiconductor device of 1st Embodiment. 第1実施形態の半導体装置の製造方法の詳細を示す断面図である。It is sectional drawing which shows the detail of the manufacturing method of the semiconductor device of 1st Embodiment. 第1実施形態の半導体装置の特性を説明するためのグラフである。It is a graph for demonstrating the characteristic of the semiconductor device of 1st Embodiment. 第1実施形態の絶縁膜5b、5cの特性を説明するためのグラフである。It is a graph for demonstrating the characteristic of the insulating film 5b, 5c of 1st Embodiment.

以下、本発明の実施形態を、図面を参照して説明する。図1から図8において、同一の構成には同一の符号を付し、重複する説明は省略する。 Hereinafter, embodiments of the present invention will be described with reference to the drawings. In FIGS. 1 to 8, the same configurations are designated by the same reference numerals, and redundant description will be omitted.

(第1実施形態)
図1は、第1実施形態の半導体装置の構造を示す斜視図である。図1の半導体装置は、例えば3次元型のNANDメモリである。
(First Embodiment)
FIG. 1 is a perspective view showing the structure of the semiconductor device of the first embodiment. The semiconductor device of FIG. 1 is, for example, a three-dimensional NAND memory.

図1の半導体装置は、コア絶縁膜1と、チャネル半導体層2と、トンネル絶縁膜3と、電荷蓄積層4と、ブロック絶縁膜5と、電極層6とを備えている。ブロック絶縁膜5は、絶縁膜5aと、絶縁膜5bとを含んでいる。電極層6は、バリアメタル層6aと、電極材層6bとを含んでいる。ブロック絶縁膜5内の絶縁膜5aは第1絶縁膜の例であり、トンネル絶縁膜3は第2絶縁膜の例であり、ブロック絶縁膜5内の絶縁膜5bは第3絶縁膜の例である。 The semiconductor device of FIG. 1 includes a core insulating film 1, a channel semiconductor layer 2, a tunnel insulating film 3, a charge storage layer 4, a block insulating film 5, and an electrode layer 6. The block insulating film 5 includes an insulating film 5a and an insulating film 5b. The electrode layer 6 includes a barrier metal layer 6a and an electrode material layer 6b. The insulating film 5a in the block insulating film 5 is an example of the first insulating film, the tunnel insulating film 3 is an example of the second insulating film, and the insulating film 5b in the block insulating film 5 is an example of the third insulating film. be.

図1では、基板上に複数の電極層と複数の絶縁層とが交互に積層されており、これらの電極層および絶縁層内にメモリホールH1が設けられている。図1は、これらの電極層のうちの1つの電極層6を示している。これらの電極層は例えば、NANDメモリのワード線として機能する。図1は、基板の表面に平行で互いに垂直なX方向およびY方向と、基板の表面に垂直なZ方向とを示している。本明細書においては、+Z方向を上方向として取り扱い、−Z方向を下方向として取り扱う。−Z方向は、重力方向と一致していてもよいし、重力方向とは一致していなくてもよい。 In FIG. 1, a plurality of electrode layers and a plurality of insulating layers are alternately laminated on a substrate, and a memory hole H1 is provided in these electrode layers and the insulating layer. FIG. 1 shows one of these electrode layers, the electrode layer 6. These electrode layers function, for example, as word lines of NAND memory. FIG. 1 shows the X and Y directions parallel to the surface of the substrate and perpendicular to each other, and the Z direction perpendicular to the surface of the substrate. In the present specification, the + Z direction is treated as an upward direction, and the −Z direction is treated as a downward direction. The −Z direction may or may not coincide with the direction of gravity.

コア絶縁膜1、チャネル半導体層2、トンネル絶縁膜3、電荷蓄積層4、および絶縁膜5aは、メモリホールH1内に形成されており、NANDメモリのメモリセルを構成している。絶縁膜5aは、メモリホールH1内の電極層および絶縁層の表面に形成され、電荷蓄積層4は、絶縁膜5aの表面に形成されている。電荷蓄積層4は、外側の側面と内側の側面との間に電荷を蓄積することが可能である。トンネル絶縁膜3は、電荷蓄積層4の表面に形成され、チャネル半導体層2は、トンネル絶縁膜3の表面に形成されている。チャネル半導体層2は、メモリセルのチャネルとして機能する。コア絶縁膜1は、チャネル半導体層2内に形成されている。 The core insulating film 1, the channel semiconductor layer 2, the tunnel insulating film 3, the charge storage layer 4, and the insulating film 5a are formed in the memory hole H1 and form a memory cell of the NAND memory. The insulating film 5a is formed on the surfaces of the electrode layer and the insulating layer in the memory hole H1, and the charge storage layer 4 is formed on the surface of the insulating film 5a. The charge storage layer 4 is capable of accumulating charges between the outer side surface and the inner side surface. The tunnel insulating film 3 is formed on the surface of the charge storage layer 4, and the channel semiconductor layer 2 is formed on the surface of the tunnel insulating film 3. The channel semiconductor layer 2 functions as a channel of a memory cell. The core insulating film 1 is formed in the channel semiconductor layer 2.

絶縁膜5aは、例えばSiO膜(シリコン酸化膜)である。電荷蓄積層4は、例えばSiN膜(シリコン窒化膜)である。トンネル絶縁膜3は例えば、SiON膜(シリコン酸窒化膜)とSiO膜とを含む積層膜である。チャネル半導体層2は、例えばポリシリコン層である。コア絶縁膜1は、例えばSiO膜である。 The insulating film 5a is, for example, a SiO 2 film (silicon oxide film). The charge storage layer 4 is, for example, a SiN film (silicon nitride film). The tunnel insulating film 3 is, for example, a laminated film including a SiON film (silicon oxynitride film) and a SiO 2 film. The channel semiconductor layer 2 is, for example, a polysilicon layer. The core insulating film 1 is, for example, a SiO 2 film.

絶縁膜5b、バリアメタル層6a、および電極材層6bは、互いに隣接する絶縁層間に形成されており、上側の絶縁層の下面と、下側の絶縁層の上面と、絶縁膜5aの側面とに順に形成されている。絶縁膜5bは例えば、Al膜(アルミニウム酸化膜)などの金属絶縁膜である。バリアメタル層6aは、例えばTiN膜(チタン窒化膜)である。電極材層6bは、例えばW(タングステン)層である。 The insulating film 5b, the barrier metal layer 6a, and the electrode material layer 6b are formed between insulating layers adjacent to each other, and include a lower surface of the upper insulating layer, an upper surface of the lower insulating layer, and a side surface of the insulating film 5a. It is formed in order. The insulating film 5b is, for example, a metal insulating film such as an Al 2 O 3 film (aluminum oxide film). The barrier metal layer 6a is, for example, a TiN film (titanium nitride film). The electrode material layer 6b is, for example, a W (tungsten) layer.

以下、本実施形態の絶縁膜5bのさらなる詳細を説明する。 Further details of the insulating film 5b of the present embodiment will be described below.

絶縁膜5bは例えば、α結晶相のAl膜である。α結晶相のAl膜は、一般的なAl膜であるγ結晶相のAl膜と同等の誘電率を有している。一方、α結晶相のAl膜のSi(シリコン)層に対するバリアハイトは、γ結晶相のAl膜のSi層に対するバリアハイトよりも0.7eV高くなっている。0.7eVというバリアハイト差は、NANDメモリの消去動作時において、ワード線からのバックトンネリング電流の低減に効果的である。よって、本実施形態によれば、絶縁膜5bとしてα結晶相のAl膜を形成することで、NANDメモリのリーク電流を低減することが可能となる。 The insulating film 5b is, for example, an Al 2 O 3 film having an α crystal phase. the Al 2 O 3 film of α crystal phase has a typical Al 2 O 3 the Al 2 O 3 film of film in a γ crystal phase equivalent dielectric constant. On the other hand, the barrier height for Si (silicon) layer of the Al 2 O 3 film of α crystalline phase, 0.7 eV is higher than the barrier height to Si layer of the Al 2 O 3 film of γ crystalline phase. The barrier height difference of 0.7 eV is effective in reducing the back tunneling current from the word line during the erasing operation of the NAND memory. Therefore, according to the present embodiment, it is possible to reduce the leakage current of the NAND memory by forming the Al 2 O 3 film of the α crystal phase as the insulating film 5b.

なお、γ結晶相のAl膜は、欠陥スピネル構造と呼ばれる準安定構造を有しているのに対して、α結晶相のAl膜は、コランダム構造と呼ばれる最安定構造を有している。γ結晶相のAl膜では、O2−イオンは面心立方格子を構成しており、Al3+イオンは6配位または4配位となっている。一方、α結晶相のAl膜では、O2−イオンは六方最密充填を構成しており、Al3+イオンは6配位サイトの2/3を規則的に占有している。γ結晶相のAl膜とα結晶相のAl膜との間にはこのような違いがあるため、Al膜がγ結晶相にあるかα結晶相にあるかは、X線回折により特定することが可能である。 The Al 2 O 3 film of the γ crystal phase has a semi-stable structure called a defective spinel structure, whereas the Al 2 O 3 film of the α crystal phase has the most stable structure called a corundum structure. Have. In the Al 2 O 3 film of the γ crystal phase, the O 2- ions form a face-centered cubic lattice, and the Al 3+ ions are 6- or 4-coordinated. On the other hand, in the Al 2 O 3 film of the α crystal phase, the O 2- ions form a hexagonal close-packed structure, and the Al 3+ ions regularly occupy 2/3 of the 6-coordination sites. Because of these differences between the Al 2 O 3 film of γ crystal phase of the Al 2 O 3 film and the α-crystal phase, or the Al 2 O 3 film is in a or α crystal phase in γ crystalline phase Can be identified by X-ray diffraction.

図2から図5は、第1実施形態の半導体装置の製造方法を示す断面図である。 2 to 5 are cross-sectional views showing a method of manufacturing the semiconductor device of the first embodiment.

まず、基板11上に下地層12を形成し、下地層12上に複数の犠牲層13と複数の絶縁層14とを交互に形成する(図2)。その結果、下地層12上に、複数の犠牲層13と複数の絶縁層14とを交互に含む積層膜15が形成される。次に、積層膜15と下地層12とを貫通するメモリホールH1を形成する(図2)。その結果、基板11の上面が、メモリホールH1内に露出する。 First, the base layer 12 is formed on the substrate 11, and a plurality of sacrificial layers 13 and a plurality of insulating layers 14 are alternately formed on the base layer 12 (FIG. 2). As a result, a laminated film 15 including a plurality of sacrificial layers 13 and a plurality of insulating layers 14 alternately is formed on the base layer 12. Next, the memory hole H1 penetrating the laminated film 15 and the base layer 12 is formed (FIG. 2). As a result, the upper surface of the substrate 11 is exposed in the memory hole H1.

基板11は例えば、Si基板などの半導体基板である。下地層12は例えば、基板11上に順に設けられた下部絶縁膜12a、半導体層12b、および上部絶縁膜12cを含む積層膜である。下部絶縁膜12aは例えば、SiO膜、または、SiO膜とその他の絶縁膜とを含む積層膜である。半導体層12bは、例えばポリシリコン層である。上部絶縁膜12cは例えば、SiO膜、または、SiO膜とその他の絶縁膜とを含む積層膜である。犠牲層13は例えばSiN膜であり、絶縁層14は例えばSiO膜である。犠牲層13は、第1膜の例である。なお、メモリホールH1は、基板11に到達するように形成する代わりに、基板11の上方の半導体層に到達するように形成してもよい。 The substrate 11 is, for example, a semiconductor substrate such as a Si substrate. The base layer 12 is, for example, a laminated film including a lower insulating film 12a, a semiconductor layer 12b, and an upper insulating film 12c which are sequentially provided on the substrate 11. The lower insulating film 12a is, for example, a SiO 2 film or a laminated film including a SiO 2 film and another insulating film. The semiconductor layer 12b is, for example, a polysilicon layer. The upper insulating film 12c is, for example, a SiO 2 film or a laminated film including a SiO 2 film and another insulating film. The sacrificial layer 13 is, for example, a SiN film, and the insulating layer 14 is, for example, a SiO 2 film. The sacrificial layer 13 is an example of the first membrane. The memory hole H1 may be formed so as to reach the semiconductor layer above the substrate 11 instead of being formed so as to reach the substrate 11.

次に、メモリホールH1内の基板11、下地層12、および積層膜15の表面に、絶縁膜5a、電荷蓄積層4、およびトンネル絶縁膜3を順に形成する(図3)。次に、メモリホールH1の底部から、絶縁膜5a、電荷蓄積層4、およびトンネル絶縁膜3をエッチングにより除去する(図3)。その結果、基板11の上面が、メモリホールH1内に再び露出する。次に、メモリホールH1内の基板11およびトンネル絶縁膜3の表面に、チャネル半導体層2とコア絶縁膜1とを順に形成する(図3)。その結果、メモリホールH1内の下地層12および積層膜15の側面に、絶縁膜5a、電荷蓄積層4、トンネル絶縁膜3、チャネル半導体層2、およびコア絶縁膜1が順に形成される。 Next, the insulating film 5a, the charge storage layer 4, and the tunnel insulating film 3 are formed in this order on the surfaces of the substrate 11, the base layer 12, and the laminated film 15 in the memory hole H1 (FIG. 3). Next, the insulating film 5a, the charge storage layer 4, and the tunnel insulating film 3 are removed from the bottom of the memory hole H1 by etching (FIG. 3). As a result, the upper surface of the substrate 11 is exposed again in the memory hole H1. Next, the channel semiconductor layer 2 and the core insulating film 1 are sequentially formed on the surfaces of the substrate 11 and the tunnel insulating film 3 in the memory hole H1 (FIG. 3). As a result, the insulating film 5a, the charge storage layer 4, the tunnel insulating film 3, the channel semiconductor layer 2, and the core insulating film 1 are sequentially formed on the side surfaces of the base layer 12 and the laminated film 15 in the memory hole H1.

次に、積層膜15内に不図示のスリットを形成し、このスリットを利用してリン酸などの薬液により犠牲層13を除去する。その結果、絶縁層14間に複数の空洞H2が形成される(図4)。これらの空洞H2は、凹部の例である。 Next, a slit (not shown) is formed in the laminated film 15, and the sacrificial layer 13 is removed with a chemical solution such as phosphoric acid using this slit. As a result, a plurality of cavities H2 are formed between the insulating layers 14 (FIG. 4). These cavities H2 are examples of recesses.

次に、これらの空洞H2内の絶縁層14および絶縁膜5aの表面に、絶縁膜5b、バリアメタル層6a、および電極材層6bを順に形成する(図5)。その結果、絶縁膜5aと絶縁膜5bとを含むブロック絶縁膜5が形成される。さらには、各空洞H2内に、バリアメタル層6aと電極材層6bとを含む電極層6が形成され、下地層12上に、複数の電極層6と複数の絶縁層14とを交互に含む積層膜16が形成される。 Next, the insulating film 5b, the barrier metal layer 6a, and the electrode material layer 6b are formed in this order on the surfaces of the insulating layer 14 and the insulating film 5a in the cavity H2 (FIG. 5). As a result, the block insulating film 5 including the insulating film 5a and the insulating film 5b is formed. Further, an electrode layer 6 including a barrier metal layer 6a and an electrode material layer 6b is formed in each cavity H2, and a plurality of electrode layers 6 and a plurality of insulating layers 14 are alternately included on the base layer 12. The laminated film 16 is formed.

各空洞H2内では、絶縁膜5b、バリアメタル層6a、および電極材層6bが、上側の絶縁層14と下側の絶縁層14との間に形成される。よって、各空洞H2内の絶縁膜5bは、上側の絶縁層14の下面、下側の絶縁層14の上面、および絶縁膜5aの側面に形成され、上側の絶縁層14、下側の絶縁層14、および絶縁膜5aと、バリアメタル層6aとの間に挟まれる。上述のように、本実施形態の絶縁膜5bは例えば、α結晶相のAl膜である。この絶縁膜5bの形成方法の詳細については、後述する。 In each cavity H2, an insulating film 5b, a barrier metal layer 6a, and an electrode material layer 6b are formed between the upper insulating layer 14 and the lower insulating layer 14. Therefore, the insulating film 5b in each cavity H2 is formed on the lower surface of the upper insulating layer 14, the upper surface of the lower insulating layer 14, and the side surface of the insulating film 5a, and the upper insulating layer 14 and the lower insulating layer are formed. It is sandwiched between the 14 and the insulating film 5a and the barrier metal layer 6a. As described above, the insulating film 5b of the present embodiment is, for example, an Al 2 O 3 film having an α crystal phase. Details of the method for forming the insulating film 5b will be described later.

このようにして、本実施形態の半導体装置が製造される(図5)。図1は、図5に示す半導体装置の一部を示している。 In this way, the semiconductor device of the present embodiment is manufactured (FIG. 5). FIG. 1 shows a part of the semiconductor device shown in FIG.

図6は、第1実施形態の半導体装置の製造方法の詳細を示す断面図である。図6(a)から図6(c)は、図5にて絶縁膜5bを形成する工程の詳細を示している。 FIG. 6 is a cross-sectional view showing details of the method for manufacturing the semiconductor device of the first embodiment. 6 (a) to 6 (c) show the details of the step of forming the insulating film 5b in FIG.

まず、空洞H2内の絶縁層14および絶縁膜5aの表面に、絶縁膜5cを形成する(図6(a))。絶縁膜5cは例えば、Al膜と異なるアルミニウム化合物膜である。このような絶縁膜5cの例は、アモルファス相のアルミニウム化合物膜であるAlN膜(アルミニウム窒化膜)である。絶縁膜5cは、第2膜の例である。なお、図6(a)は、トンネル絶縁膜3に含まれる絶縁膜3a(例えばSiO膜)と絶縁膜3b(例えばSiON膜)とを示している。 First, the insulating film 5c is formed on the surfaces of the insulating layer 14 and the insulating film 5a in the cavity H2 (FIG. 6A). The insulating film 5c is, for example, an aluminum compound film different from the Al 2 O 3 film. An example of such an insulating film 5c is an AlN film (aluminum nitride film) which is an amorphous phase aluminum compound film. The insulating film 5c is an example of the second film. Note that FIG. 6A shows an insulating film 3a (for example, a SiO 2 film) and an insulating film 3b (for example, a SiON film) included in the tunnel insulating film 3.

本実施形態の絶縁膜5c(AlN膜)は、縦型減圧バッチ炉内でALD(Atomic Layer Deposition)により形成される。具体的には、絶縁膜5cは、原料ガスとしてTMA(トリメチルアルミニウム、Al(CH)を使用し、窒化剤としてアンモニア(NH)を使用して、300〜400℃の温度で形成される。絶縁膜5cの膜厚は、ALDサイクル数を調整することで制御される。本実施形態では、後述するように、アモルファス相のAlN膜をα結晶相のAl膜に熱酸化により変化させることで、絶縁膜5cを絶縁膜5bに変化させる。この熱酸化によれば、絶縁膜5cの酸化と結晶化が同時に進み、絶縁膜5cが絶縁膜5bに変化する。 The insulating film 5c (AlN film) of the present embodiment is formed by ALD (Atomic Layer Deposition) in a vertical decompression batch furnace. Specifically, the insulating film 5c is formed at a temperature of 300 to 400 ° C. using TMA (trimethylaluminum, Al (CH 3 ) 3 ) as a raw material gas and ammonia (NH 3 ) as a nitriding agent. Will be done. The film thickness of the insulating film 5c is controlled by adjusting the number of ALD cycles. In the present embodiment, as described later, the AlN film of the amorphous phase in the Al 2 O 3 film of α-crystal phase by changing the thermal oxidation, changing the insulating film 5c on the insulating film 5b. According to this thermal oxidation, the insulating film 5c is oxidized and crystallized at the same time, and the insulating film 5c is changed to the insulating film 5b.

なお、絶縁膜5cは、その他のアルミニウム化合物膜でもよい。このような絶縁膜5cの例は、アルミニウム(Al)元素と窒素(N)元素とを含むアモルファス相のアルミニウム化合物膜であり、例えば、AlON膜(アルミニウム酸窒化膜)、AlCN膜(アルミニウム炭窒化膜)、AlCON膜(アルミニウム炭酸窒化膜)などを含む。絶縁膜5cは、結晶相以外のアルミニウム化合物膜として形成され、熱酸化により酸化と結晶化とが同時に進む絶縁膜であれば、その他の絶縁膜でもよい。また、絶縁膜5cは、本実施形態では液化ガスであるTMAを用いて形成されるが、AlCl(塩化アルミニウム)などの固体材料を昇華させることで形成されてもよい。 The insulating film 5c may be another aluminum compound film. An example of such an insulating film 5c is an aluminum compound film having an amorphous phase containing an aluminum (Al) element and a nitrogen (N) element. For example, an AlON film (aluminum oxynitride film) and an AlCN film (aluminum carbonitriding). Membrane), AlCON film (aluminum carbonated film) and the like. The insulating film 5c may be any other insulating film as long as it is formed as an aluminum compound film other than the crystalline phase and oxidation and crystallization proceed at the same time by thermal oxidation. Further, although the insulating film 5c is formed by using TMA which is a liquefied gas in the present embodiment, it may be formed by sublimating a solid material such as AlCl 3 (aluminum chloride).

次に、絶縁膜5cの熱酸化を行う(図6(b))。その結果、絶縁膜5cの酸化と結晶化が同時に進み、絶縁膜5c(アモルファス相のAlN膜)が絶縁膜5b(α結晶相のAl膜)に変化する(図6(c))。 Next, the insulating film 5c is thermally oxidized (FIG. 6 (b)). As a result, oxidation and crystallization of the insulating film 5c proceed at the same time, and the insulating film 5c (amorphous phase AlN film) changes to the insulating film 5b (α crystal phase Al 2 O 3 film) (FIG. 6 (c)). ..

本実施形態では、ラジカル酸化により熱印加と酸化を同時に行い、絶縁膜5cを絶縁膜5bに変化させる。例えば、膜厚2.3〜2.5nmの絶縁膜5cに対し、930〜1050℃の温度および10.5torrの圧力で10〜30秒のラジカル酸化を行う。この際、H(水素)ガスの分圧比が2〜20%となるように、HガスとO(酸素)ガスとを同時に供給することで、OラジカルおよびOHラジカルを生成させ、Oラジカルにより絶縁膜5cを酸化させる(図6(b)を参照)。これにより、絶縁膜5cが膨張して、約3nmの膜厚を有する絶縁膜5bを得ることができる。なお、本実施形態では熱によりOラジカルを生成させているが、代わりにプラズマを用いてOラジカルを生成させてもよい。 In the present embodiment, heat application and oxidation are simultaneously performed by radical oxidation to change the insulating film 5c into an insulating film 5b. For example, an insulating film 5c having a film thickness of 2.3 to 2.5 nm is subjected to radical oxidation for 10 to 30 seconds at a temperature of 930 to 1050 ° C. and a pressure of 10.5 torr. At this time, O radicals and OH radicals are generated by simultaneously supplying H 2 gas and O 2 (oxygen) gas so that the partial pressure ratio of H 2 (hydrogen) gas is 2 to 20%, and O Radicals oxidize the insulating film 5c (see FIG. 6B). As a result, the insulating film 5c expands, and an insulating film 5b having a film thickness of about 3 nm can be obtained. In this embodiment, O radicals are generated by heat, but plasma may be used instead to generate O radicals.

絶縁膜5cをラジカル酸化により絶縁膜5bに変化させる場合、ラジカルの影響で、絶縁膜5a(SiO膜)と電荷蓄積層4(SiN膜)との間に、シリコン(Si)元素、酸素(O)元素、および窒素(N)元素を含む層Lが形成される(図6(b)を参照)。層Lは、窒素元素を含む酸化膜の層であり、複数の空洞H2および複数の絶縁層14の側方(図6(b)ではX方向)に、Z方向に延びるように形成される。層Lは例えば、0.8〜1.0nmの厚さを有し、最終的に完成する半導体装置内にも残存する。層Lは、第1層の例である。後述するように、本実施形態の層L内の窒素濃度は、電荷蓄積層4内の窒素濃度よりも高くなる。 When the insulating film 5c is changed to the insulating film 5b by radical oxidation, the silicon (Si) element and oxygen (Si) element and oxygen (Si) element and oxygen (Si) between the insulating film 5a (SiO 2 film) and the charge storage layer 4 (SiN film) due to the influence of the radical. A layer L containing an element O) and an element nitrogen (N) is formed (see FIG. 6 (b)). The layer L is a layer of an oxide film containing a nitrogen element, and is formed so as to extend in the Z direction sideways (X direction in FIG. 6B) of the plurality of cavities H2 and the plurality of insulating layers 14. The layer L has a thickness of, for example, 0.8 to 1.0 nm, and remains in the finally completed semiconductor device. Layer L is an example of the first layer. As will be described later, the nitrogen concentration in the layer L of the present embodiment is higher than the nitrogen concentration in the charge storage layer 4.

なお、絶縁膜5cの熱酸化は、ラジカル酸化の代わりに水酸化により行ってもよい。例えば、膜厚2.3〜2.5nmの絶縁膜5cに対し、縦型減圧バッチ炉内で850〜950℃の温度および384torrのHO(水)分圧で10〜60分の水酸化を行う。この際、水酸化用の水として、水分発生器を用いて精製した水蒸気が炉内に導入される。これにより、絶縁膜5cが膨張して、約3nmの膜厚を有する絶縁膜5bを得ることができる。絶縁膜5cの水酸化のプロセスは、ここでは水蒸気をN(窒素)ガスで希釈した大気圧プロセスとするが、代わりに減圧プロセスとしてもよい。 The thermal oxidation of the insulating film 5c may be carried out by hydroxylation instead of radical oxidation. For example, an insulating film 5c having a film thickness of 2.3 to 2.5 nm is hydroxylated for 10 to 60 minutes at a temperature of 850 to 950 ° C. and a partial pressure of H 2 O (water) of 384 torr in a vertical decompression batch furnace. I do. At this time, steam purified using a water generator is introduced into the furnace as water for hydroxylation. As a result, the insulating film 5c expands, and an insulating film 5b having a film thickness of about 3 nm can be obtained. The process of hydroxylating the insulating film 5c is an atmospheric pressure process in which water vapor is diluted with N 2 (nitrogen) gas, but a decompression process may be used instead.

図6(a)から図6(c)の工程の実行後には、空洞H2内に、絶縁膜5bを介して、バリアメタル層6aと電極材層6bとを順に形成する(図5を参照)。このようにして、本実施形態の半導体装置が製造される。 After executing the steps of FIGS. 6 (a) to 6 (c), the barrier metal layer 6a and the electrode material layer 6b are sequentially formed in the cavity H2 via the insulating film 5b (see FIG. 5). .. In this way, the semiconductor device of the present embodiment is manufactured.

図7は、第1実施形態の半導体装置の特性を説明するためのグラフである。 FIG. 7 is a graph for explaining the characteristics of the semiconductor device of the first embodiment.

曲線C1は、図6(b)のラジカル酸化を実行する前の電荷蓄積層4、絶縁膜5a、および絶縁膜5bに対するXRR(X線反射率)測定の結果を表す。曲線C2は、図6(b)のラジカル酸化を実行した後の電荷蓄積層4、絶縁膜5a、および絶縁膜5cに対するXRR測定の結果を表す。図7の横軸は、図6(b)等に示すX座標を表し、図7の縦軸は、XRR測定により測定された強度を表す。 Curve C1 represents the result of XRR (X-ray reflectivity) measurement on the charge storage layer 4, the insulating film 5a, and the insulating film 5b before performing the radical oxidation of FIG. 6B. Curve C2 represents the result of XRR measurement on the charge storage layer 4, the insulating film 5a, and the insulating film 5c after performing the radical oxidation of FIG. 6 (b). The horizontal axis of FIG. 7 represents the X coordinate shown in FIG. 6B and the like, and the vertical axis of FIG. 7 represents the intensity measured by the XRR measurement.

図7に示すように、曲線C2は、電荷蓄積層4と絶縁膜5aとの間でピークを示している。これは、電荷蓄積層4と絶縁膜5aとの間に、高濃度に窒素原子を含む層Lが形成されたことを示している。XRR測定の結果によれば、この層L内の窒素濃度は、電荷蓄積層4内の窒素濃度よりも高くなっていることが分かった。 As shown in FIG. 7, the curve C2 shows a peak between the charge storage layer 4 and the insulating film 5a. This indicates that a layer L containing nitrogen atoms at a high concentration was formed between the charge storage layer 4 and the insulating film 5a. According to the result of the XRR measurement, it was found that the nitrogen concentration in the layer L was higher than the nitrogen concentration in the charge storage layer 4.

図8は、第1実施形態の絶縁膜5b、5cの特性を説明するためのグラフである。 FIG. 8 is a graph for explaining the characteristics of the insulating films 5b and 5c of the first embodiment.

図8は、Al膜の結晶構造と温度との関係を示している。例えば、矢印P1は、780℃以下でγ結晶相のAl膜が生じ得ることを示している。また、矢印P2は、約1100℃でα結晶相のAl膜が生じ得ることを示している。また、矢印P3は、約800〜1400℃でα結晶相のAl膜が生じ得ることを示している。 FIG. 8 shows the relationship between the crystal structure of the Al 2 O 3 film and the temperature. For example, the arrow P1 indicates that an Al 2 O 3 film having a γ crystal phase can be formed at 780 ° C. or lower. Further, the arrow P2 indicates that an Al 2 O 3 film having an α crystal phase can be formed at about 1100 ° C. Further, the arrow P3 indicates that an Al 2 O 3 film having an α crystal phase can be formed at about 800 to 1400 ° C.

ここで、アモルファス相のアルミニウム酸化膜(AlO膜)を、加熱により結晶相のアルミニウム酸化膜(Al膜)に変化させる場合を想定する。この場合、AlO膜の温度を常温から500〜1000℃の温度域に上昇させると、AlO膜は、矢印P3のようにα結晶相のAl膜に変化する可能性だけでなく、矢印P1のようにγ結晶相のAl膜に変化する可能性もある。後者の場合、AlO膜の温度を常温から約1100℃に上昇させると、AlO膜はγ結晶相のAl膜に変化し(矢印P1)、その後にγ結晶相のAl膜がα結晶相のAl膜に変化することになる(矢印P2)。しかしながら、この場合、α結晶相のAl膜を生じさせるために約1100℃という高温の加熱が必要となることや、γ結晶相のAl膜の影響でα結晶相のAl膜が生じにくくなるという問題がある。 Here, the aluminum oxide film in an amorphous phase (AlO X layer), heated by assuming a case of changing the aluminum oxide film of the crystalline phase (Al 2 O 3 film). In this case, increasing the temperature range of 500 to 1000 ° C. The temperature of the AlO X film from room temperature, AlO X film, not only may change the Al 2 O 3 film of α-crystal phase as indicated by the arrow P3 , There is a possibility that it changes to an Al 2 O 3 film of the γ crystal phase as shown by the arrow P1. In the latter case, if raising the temperature of the AlO X layer from room temperature to about 1100 ° C., AlO X layer changes in the Al 2 O 3 film of γ crystalline phase (arrow P1), Al 2 O subsequent to γ crystalline phase The three films will change to Al 2 O 3 films in the α crystal phase (arrow P2). However, in this case, alpha crystalline phase and may require a high temperature heating of the Al 2 O 3 film about 1100 ° C. to effect the, gamma Al crystalline phase of the Al 2 O 3 film affected by alpha crystalline phase There is a problem that the 2 O 3 film is less likely to be formed.

そこで、本実施形態では、アモルファス相のアルミニウム窒化膜(AlN膜)を、熱酸化により結晶相のアルミニウム酸化膜(Al膜)に変化させる。これにより、アモルファス相のAlN膜を少なくとも780℃まで維持し、780℃よりも高温でアモルファス相のAlN膜を結晶相のAl膜に変化させることが可能となる。この場合、AlN膜の温度はすでに矢印P1の温度域を通過しているため、AlN膜は、γ結晶相のAl膜の状態を経ずに、α結晶相のAl膜に変化することになる。すなわち、AlN膜は、γ結晶相の核形成が行われることなく、α結晶相のAl膜に変化することになる。よって、本実施形態によれば、約1100℃という高温の加熱を行わずにα結晶相のAl膜(絶縁膜5b)を生じさせること(矢印P3)や、γ結晶相のAl膜の影響でα結晶相のAl膜(絶縁膜5b)が生じにくくなることを抑制すること(矢印P2)が可能となる。 Therefore, in this embodiment, the amorphous phase of the aluminum nitride film (AlN film) by thermal oxidation is changed into aluminum oxide film of the crystalline phase (Al 2 O 3 film). Accordingly, the AlN film of the amorphous phase is maintained at least up to 780 ° C., it becomes possible to change the AlN film in an amorphous phase in the Al 2 O 3 film of the crystalline phase at a temperature higher than 780 ° C.. In this case, since passing through the temperature zone of temperature already arrow P1 of the AlN film, AlN film, without passing through the state of the Al 2 O 3 film of γ crystalline phases, alpha crystalline phase of the Al 2 O 3 film Will change to. That, AlN film, without nucleation of γ crystalline phase is carried out, it will change in the Al 2 O 3 film of α crystal phase. Therefore, according to the present embodiment, the Al 2 O 3 film (insulating film 5b) of the α crystal phase is formed without heating at a high temperature of about 1100 ° C. (arrow P3), and the Al 2 of the γ crystal phase is formed. O 3 Al 2 O 3 film of α-crystal phase under the influence of the membrane to prevent the (insulating film 5b) is less likely to occur (arrow P2) becomes possible.

以上のように、本実施形態のブロック絶縁膜5は、絶縁膜5bとしてα結晶相のAl膜を含んでいる。よって、本実施形態によれば、α結晶相のAl膜により、ブロック絶縁膜5の性能を向上させることが可能となる。 As described above, the block insulating film 5 of the present embodiment includes an α crystal phase Al 2 O 3 film as the insulating film 5b. Therefore, according to the present embodiment, the performance of the block insulating film 5 can be improved by the Al 2 O 3 film of the α crystal phase.

例えば、α結晶相のAl膜は、γ結晶相のAl膜と同様に、高い誘電率を有している。よって、本実施形態によれば、α結晶相のAl膜を用いることで、γ結晶相のAl膜を用いる場合と同様に高い性能のブロック絶縁膜5を実現することが可能となる。 For example, the Al 2 O 3 film of α crystalline phase, like the Al 2 O 3 film of γ crystalline phase, has a high dielectric constant. Therefore, according to the present embodiment, by using the Al 2 O 3 film of the α crystal phase, it is possible to realize the block insulating film 5 having high performance as in the case of using the Al 2 O 3 film of the γ crystal phase. It will be possible.

また、α結晶相のAl膜のSi層に対するバリアハイトは、γ結晶相のAl膜のSi層に対するバリアハイトよりも0.7eV高くなっている。よって、本実施形態によれば、α結晶相のAl膜を用いることで、γ結晶相のAl膜を用いる場合に比べてリーク電流をより低減することが可能となる。 Further, the barrier height with respect to Si layer of the Al 2 O 3 film of α crystalline phase, 0.7 eV is higher than the barrier height to Si layer of the Al 2 O 3 film of γ crystalline phase. Therefore, according to the present embodiment, by using the Al 2 O 3 film of the α crystal phase, it is possible to further reduce the leakage current as compared with the case of using the Al 2 O 3 film of the γ crystal phase.

また、本実施形態によれば、AlO膜より高密度のAlN膜からα結晶相のAl膜を形成することで、例えば欠陥の少ない絶縁膜5bを形成することが可能となる。 Further, according to this embodiment, by forming an Al 2 O 3 film of α-crystal phase from the dense AlN film from AlO X film, it is possible to form a less insulating film 5b e.g. defects.

以上、いくつかの実施形態を説明したが、これらの実施形態は、例としてのみ提示したものであり、発明の範囲を限定することを意図したものではない。本明細書で説明した新規な装置および方法は、その他の様々な形態で実施することができる。また、本明細書で説明した装置および方法の形態に対し、発明の要旨を逸脱しない範囲内で、種々の省略、置換、変更を行うことができる。添付の特許請求の範囲およびこれに均等な範囲は、発明の範囲や要旨に含まれるこのような形態や変形例を含むように意図されている。 Although some embodiments have been described above, these embodiments are presented only as examples and are not intended to limit the scope of the invention. The novel devices and methods described herein can be implemented in a variety of other forms. In addition, various omissions, substitutions, and changes can be made to the forms of the apparatus and method described in the present specification without departing from the gist of the invention. The appended claims and their equivalent scope are intended to include such forms and variations contained within the scope and gist of the invention.

1:コア絶縁膜、2:チャネル半導体層、3:トンネル絶縁膜、
3a、3b:絶縁膜、4:電荷蓄積層、5:ブロック絶縁膜、
5a、5b、5c:絶縁膜、6:電極層、6a:バリアメタル層、6b:電極材層、
11:基板、12:下地層、12a:下部絶縁膜、12b:半導体層、
12c:上部絶縁膜、13:犠牲層、14:絶縁層、15、16:積層膜
1: Core insulating film 2: Channel semiconductor layer 3: Tunnel insulating film,
3a, 3b: Insulating film, 4: Charge storage layer, 5: Block insulating film,
5a, 5b, 5c: Insulating film, 6: Electrode layer, 6a: Barrier metal layer, 6b: Electrode material layer,
11: Substrate, 12: Underlayer, 12a: Lower insulating film, 12b: Semiconductor layer,
12c: Upper insulating film, 13: Sacrificial layer, 14: Insulating layer, 15, 16: Laminated film

Claims (12)

複数の電極層と複数の絶縁層とを交互に含む積層膜と、
前記積層膜内に順に設けられた第1絶縁膜、電荷蓄積層、第2絶縁膜、および半導体層と、
前記積層膜内において、前記電極層と前記絶縁層との間と、前記電極層と前記第1絶縁膜との間とに設けられ、α結晶相のアルミニウム酸化膜を含む第3絶縁膜と、
を備える半導体装置。
A laminated film containing a plurality of electrode layers and a plurality of insulating layers alternately,
A first insulating film, a charge storage layer, a second insulating film, and a semiconductor layer, which are sequentially provided in the laminated film,
In the laminated film, a third insulating film provided between the electrode layer and the insulating layer and between the electrode layer and the first insulating film and containing an aluminum oxide film having an α crystal phase, and a third insulating film.
A semiconductor device equipped with.
前記第1絶縁膜は、シリコン元素と酸素元素とを含む、請求項1に記載の半導体装置。 The semiconductor device according to claim 1, wherein the first insulating film contains a silicon element and an oxygen element. 前記第1絶縁膜と前記電荷蓄積層との間に、シリコン元素、酸素元素、および窒素元素を含む第1層を備える、請求項1または2に記載の半導体装置。 The semiconductor device according to claim 1 or 2, further comprising a first layer containing a silicon element, an oxygen element, and a nitrogen element between the first insulating film and the charge storage layer. 前記第1層は、前記複数の電極層および前記複数の絶縁層の側方に設けられている、請求項3に記載の半導体装置。 The semiconductor device according to claim 3, wherein the first layer is provided on the side of the plurality of electrode layers and the plurality of insulating layers. 前記電荷蓄積層は、シリコン元素と窒素元素とを含み、
前記第1層内の窒素濃度は、前記電荷蓄積層内の窒素濃度よりも高い、請求項3または4に記載の半導体装置。
The charge storage layer contains a silicon element and a nitrogen element, and contains
The semiconductor device according to claim 3 or 4, wherein the nitrogen concentration in the first layer is higher than the nitrogen concentration in the charge storage layer.
複数の第1膜と複数の絶縁層とを交互に含む積層膜を形成し、
前記積層膜内に第1絶縁膜、電荷蓄積層、第2絶縁膜、および半導体層を順に形成し、
前記第1膜を除去して前記絶縁層間に複数の凹部を形成し、
前記凹部内に、α結晶相のアルミニウム酸化膜を含む複数の第3絶縁膜と、複数の電極層とを順に形成する、
ことを含む半導体装置の製造方法。
A laminated film containing a plurality of first films and a plurality of insulating layers alternately is formed.
A first insulating film, a charge storage layer, a second insulating film, and a semiconductor layer are formed in this laminated film in this order.
The first film is removed to form a plurality of recesses between the insulating layers.
A plurality of third insulating films including an aluminum oxide film having an α crystal phase and a plurality of electrode layers are sequentially formed in the recesses.
A method of manufacturing a semiconductor device including the above.
前記第3絶縁膜は、
前記凹部内に、アルミニウム化合物膜を含む第2膜を形成し、
前記第2膜を前記第3絶縁膜に変化させる、
ことで形成される、請求項6に記載の半導体装置の製造方法。
The third insulating film is
A second film containing an aluminum compound film is formed in the recess.
The second film is changed to the third insulating film.
The method for manufacturing a semiconductor device according to claim 6, which is formed by the above.
前記第2膜は、熱酸化により前記第3絶縁膜に変化する、請求項7に記載の半導体装置の製造方法。 The method for manufacturing a semiconductor device according to claim 7, wherein the second film changes to the third insulating film by thermal oxidation. 前記第2膜は、アモルファス相の前記アルミニウム化合物膜を含む、請求項7または8に記載の半導体装置の製造方法。 The method for manufacturing a semiconductor device according to claim 7 or 8, wherein the second film includes the aluminum compound film having an amorphous phase. 前記第2膜が前記第3絶縁膜に変化する際、前記アルミニウム化合物膜は、γ結晶相のアルミニウム酸化膜の状態を経ずに、前記α結晶相のアルミニウム酸化膜に変化する、請求項9に記載の半導体装置の製造方法。 9. When the second film changes to the third insulating film, the aluminum compound film changes to the aluminum oxide film of the α crystal phase without going through the state of the aluminum oxide film of the γ crystal phase. The method for manufacturing a semiconductor device according to. 前記アルミニウム化合物膜は、アルミニウム元素と窒素元素とを含む、請求項7から10のいずれか1項に記載の半導体装置の製造方法。 The method for manufacturing a semiconductor device according to any one of claims 7 to 10, wherein the aluminum compound film contains an aluminum element and a nitrogen element. 前記アルミニウム化合物膜は、アルミニウム窒化膜、アルミニウム酸窒化膜、アルミニウム炭窒化膜、またはアルミニウム炭酸窒化膜を含む、請求項11に記載の半導体装置の製造方法。 The method for manufacturing a semiconductor device according to claim 11, wherein the aluminum compound film includes an aluminum nitride film, an aluminum oxynitride film, an aluminum carbon nitride film, or an aluminum carbonate nitride film.
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