JP2021114325A - Semiconductor device, battery monitoring system, and reference voltage generation method - Google Patents

Abstract

To provide a semiconductor device, a battery monitoring system, and a reference voltage generation method capable of improving a PSRR characteristic.SOLUTION: A semiconductor device includes: a second filter which performs filtering processing on a signal according to a supply voltage inputted from an input terminal via a first filter and has a different time constant from that of the first filter; and a reference voltage generation circuit which generates a reference voltage based on the signal subjected to the filtering processing by the second filter and outputs a signal according to the generated reference voltage to an outside via an output terminal.SELECTED DRAWING: Figure 1

Description

The present invention relates to a semiconductor device, a battery monitoring system, and a reference voltage generation method.

Conventionally, a reference voltage generation circuit has been used as a semiconductor device that generates an electric signal corresponding to a reference voltage (hereinafter referred to as "reference voltage VREF") from an electric signal corresponding to the power supply voltage VDD (hereinafter referred to as "power supply voltage VDD"). Are known. A technique for improving PSRR (Power Supply Rejection Ratio) is known in order to reduce the influence of fluctuations in the power supply voltage VDD and noise superimposed on the power supply voltage VDD.

As the technique, for example, Patent Documents 1 and 2 describe a technique for removing noise of a high frequency component superimposed on a power supply voltage VDD by an LPF by inputting a power supply voltage VDD to a reference voltage generation circuit via an LPF. Is described.

Further, as such a reference voltage generation circuit, as shown in FIG. 8, a reference voltage generation circuit 132 provided with a BGR (Bandgap reference) 134 and an AMP (Amplifier) 136 is known. In the reference voltage generation circuit 132 included in the semiconductor device 100 shown in FIG. 8, the power supply voltage VDD is input to the terminal 130 via the LPF 112 including the resistance element 120 and the capacitance element 122. Then, the power supply voltage VDD is input from the terminal 130 to the BGR 134 of the reference voltage generation circuit 132. The reference voltage VREF generated by the BGR 134 based on the power supply voltage VDD is output to the outside via the terminal 40.

Japanese Unexamined Patent Publication No. 2012-118808 Japanese Unexamined Patent Publication No. 2009-301551

By the way, in the conventional reference voltage generation circuit 132 shown in FIG. 8, the band of the BGR 134 is narrower than that of the AMP 136. Therefore, a capacitive element for expanding the band of the BGR 134 is connected between the BGR 134 and the AMP 136. In the reference voltage generation circuit 132 shown in FIG. 8, a capacitance element 147 provided outside the semiconductor device 100 is connected between the output of the BGR 134 and the input of the AMP 136 via the terminal 141.

FIG. 9 shows an example of the frequency characteristics of PSRR (hereinafter, referred to as “PSRR characteristics”) in the reference voltage generation circuit 132 of the conventional semiconductor device 100 shown in FIG. In FIG. 9, for comparison of PSRR characteristics, the PSRR characteristics when the capacitance element 147 and the BGR 134 are not connected in the conventional semiconductor device 100 shown in FIG. 8 are shown as Comparative Example 1.

FIG. 9 shows that the lower the gain, the better the PSRR characteristics. The PSRR characteristic improves as the capacitance value of the capacitance element 147 increases. For example, in the PSRR characteristic shown in FIG. 9, the gain in the intermediate frequency region decreases as the capacitance value of the capacitance element 147 increases (see arrow A). ..

However, if the capacitance value of the capacitance element 147 is increased in this way, the cost may increase or the overall circuit scale may increase. Therefore, if the capacitance value of the capacitance element 147 is limited, the PSRR characteristics may not be sufficiently improved as described above.

In order to suppress the increase in the overall circuit scale and the cost due to the increase in the capacitance of the capacitive element in this way, the PSRR characteristics of the semiconductor device (reference voltage generation circuit) are improved. Is desired.

An object of the present invention is to provide a semiconductor device, a battery monitoring system, and a reference voltage generation method capable of improving PSRR characteristics.

In order to achieve the above object, the semiconductor device of the present disclosure filters a signal corresponding to a power supply voltage input from an input terminal via a first filter, and has a time constant different from that of the first filter. It includes two filters and a reference voltage generation circuit that generates a reference voltage based on the signal filtered by the second filter and outputs a signal corresponding to the generated reference voltage to the outside via an output terminal.

Further, in order to achieve the above object, the semiconductor device of the present disclosure includes an externally provided capacitance element and an internally provided resistance element that can be connected via a connection terminal, and the resistance element and the above. In a state where the capacitive element is connected via the connection terminal, the signal corresponding to the power supply voltage input from the input terminal is filtered through the first filter, and the time constant is different from that of the first filter. A second filter and a reference voltage generation circuit that generates a reference voltage based on the signal filtered by the second filter and outputs a signal corresponding to the generated reference voltage to the outside via an output terminal are provided. ..

Further, in order to achieve the above object, the battery monitoring system of the present disclosure drives the semiconductor device of the present disclosure and a reference voltage output from the semiconductor device as a drive voltage, and a plurality of battery cells connected in series. A control unit that outputs a control signal for controlling the measurement of the battery voltage of the battery cell to be measured from the battery provided with the above, and the voltage at one end and the voltage at the other end of each of the plurality of battery cells are input and input. A cell selection unit that selects a voltage corresponding to the battery cell to be measured from the voltage according to the control signal and outputs a signal corresponding to the selected voltage, and a reference voltage output from the semiconductor device as a driving voltage. An analog-digital converter that converts a signal corresponding to the voltage output from the cell selection unit into a digital signal and outputs the signal to the control unit.

Further, in order to achieve the above object, in the reference voltage generation method of the present disclosure, a signal corresponding to the power supply voltage input from the input terminal via the first filter has a time constant different from that of the first filter. This includes a process of filtering with two filters, generating a reference voltage based on the signal filtered by the second filter, and outputting a signal corresponding to the generated reference voltage to the outside via an output terminal.

Further, in order to achieve the above object, the reference voltage generation method of the present disclosure includes an externally provided capacitance element that can be connected via a connection terminal and an internally provided resistance element, and the resistance element. And the capacitance element are connected via the connection terminal, and the signal corresponding to the power supply voltage input from the input terminal via the first filter is sent to the second filter having a time constant different from that of the first filter. It includes a process of filtering with a filter, generating a reference voltage based on the signal filtered by the second filter, and outputting a signal corresponding to the generated reference voltage to the outside via an output terminal.

According to the present invention, there is an effect that the PSRR characteristics can be improved.

It is a block diagram which shows the outline of the example of the semiconductor device in 1st Embodiment. It is a figure which shows an example of the frequency characteristic of PSRR of the semiconductor device (reference voltage generation circuit) of 1st Embodiment. It is a block diagram which shows the outline of the example of the semiconductor device in 2nd Embodiment. It is a block diagram which shows the outline of the example of the semiconductor device in 3rd Embodiment. It is a block diagram which shows the outline of another example of the semiconductor device in 3rd Embodiment. It is a block diagram which shows the outline of the position example of the battery monitoring system in 4th Embodiment. It is a block diagram which shows the outline of another example of the semiconductor device in 1st Embodiment. It is a block diagram which shows the outline of an example of the semiconductor device which is a comparative example. It is a figure which shows an example of the PSRR characteristic of the semiconductor device (reference voltage generation circuit) which is a comparative example.

Hereinafter, each embodiment will be described in detail with reference to the drawings.

[First Embodiment]
First, the configuration of the semiconductor device of this embodiment will be described. FIG. 1 shows a configuration diagram showing an outline of an example of the semiconductor device 10 of the present embodiment.

As shown in FIG. 1, the semiconductor device 10 of the present embodiment includes a terminal 30, a reference voltage generation circuit 32, a terminal 38, a terminal 40, and an LPF (Low Pass Filter) 42.

An electric signal (hereinafter, referred to as “power supply voltage VDD”) corresponding to the power supply voltage VDD is input to the terminal 30 from the outside via an LPF 12 provided outside the semiconductor device 10. The LPF 12 includes a resistance element 20 and a capacitance element 22, and performs a filtering process for removing power supply noise of a high frequency component superimposed on the power supply voltage VDD. The terminal 30 of the present embodiment is an example of the input terminal of the present disclosure, and the LPF 12 of the present embodiment is an example of the first filter of the present disclosure.

The power supply voltage VDD input to the terminal 30 is input to the reference voltage generation circuit 32 via the LPF 42. The LPF 42 of the present embodiment includes a resistance element 44 and a capacitance element 46. The LPF 42 of the present embodiment has a function of assisting the LPF 12, and further cuts off the power supply noise (filtering process) with respect to the power supply voltage VDD in which the power supply noise is cut off (filtering process) by the LPF 12. Therefore, the time constant (frequency to be cut off) of the LPF 42 of the present embodiment is different from that of the LPF 12.

The capacitance element 46 of the LPF 42 of the present embodiment is provided outside the semiconductor device 10, and is connected to the capacitance element 46 via a terminal 38. That is, in the semiconductor device 10 of the present embodiment, the LPF 42 functions as a low-pass filter by connecting the resistance element 44 and the capacitance element 46 via the terminal 38. One end of the resistance element 44 is connected to the terminal 30, and the other end is connected to the reference voltage generation circuit 32 and the terminal 38. The LPF 42 of the present embodiment is an example of the second filter of the present disclosure, and the terminal 38 of the present embodiment is an example of the connection terminal of the present disclosure.

The reference voltage generation circuit 32 includes a BGR (Bandgap reference) circuit (hereinafter referred to as “BGR”) 34 and an amplifier circuit (hereinafter referred to as “AMP”) 36. The BGR 34 is connected to the terminal 30 via the LPF 42, and generates a reference voltage VREF from the input power supply voltage VDD. A terminal 30 and a BGR 34 are connected to the AMP 36, and the reference voltage VREF generated by the BGR 34 is amplified by the AMP 36. The reference voltage VREF amplified by the AMP 36 is output to the outside of the semiconductor device 10 via the terminal 40. The terminal 40 of this embodiment is an example of the output terminal of the present disclosure.

Next, the frequency characteristics of PSRR (hereinafter, referred to as “PSRR characteristics”) in the reference voltage generation circuit 32 of the semiconductor device 10 of the present embodiment will be described. FIG. 2 shows an example of PSRR characteristics in the reference voltage generation circuit 32 of the semiconductor device 10 of the present embodiment. In addition to the PSRR characteristics of the semiconductor device 10 of the present embodiment, in FIG. 2, for comparison, unlike the semiconductor device 10 shown in FIG. 1, the power supply voltage VDD is input without going through the LPF 12, and the LPF 42. The PSRR characteristics of the semiconductor device in the case where the above is not provided are shown as Comparative Example A. Further, for comparison, FIG. 2 shows the PSRR characteristics of the semiconductor device when the semiconductor device is not provided as Comparative Example B, unlike the semiconductor device 10 shown in FIG.

FIG. 2 shows that the lower the gain, the better the PSRR characteristics. As shown in FIG. 2, in Comparative Example B, since the high frequency component is removed by LPF 12, Comparative Example B has improved PSRR characteristics in the high frequency region as compared with Comparative Example A. The time constant in the LPF 12, that is, the resistance value of the resistance element 20 and the capacitance value of the capacitance element 22 is based on the noise state superimposed on the power supply voltage VDD, the PSSR characteristics when the LPF 12 is not provided (see Comparative Example A), and the like. The values obtained on the basis can be used, and these values can be obtained experimentally.

On the other hand, as shown in FIG. 2, when the present embodiment and Comparative Example B are compared, it can be seen that the semiconductor device 10 of the present embodiment has improved PSRR characteristics in the intermediate frequency region. The time constant in the LPF 42, that is, the resistance value of the resistance element 44 and the capacitance value of the capacitance element 46 are the state of overlapping noise, the PSSR characteristics when the LPF 42 is not provided (see Comparative Example A and Comparative Example B), and the characteristics. It is possible to use the values obtained based on the intermediate frequency region or the like for which the improvement is desired, and these values can be obtained experimentally.

As described above, in the semiconductor device 10 of the present embodiment, the power supply voltage VDD is input from the terminal 30 via the LPF 12. The LPF 42 includes an externally provided capacitance element 46 that can be connected via the terminal 38 and an internally provided resistance element 44, and the resistance element 44 and the capacitance element 46 are connected via the terminal 38. In this state, the power supply voltage VDD input via the terminal 30 is filtered. The reference voltage generation circuit 32 generates a reference voltage VREF based on the signal filtered by the LPF 42, and outputs the generated reference voltage VREF to the outside via the terminal 40. Further, the time constants of LPF12 and LPF42 are different.

According to the semiconductor device 10 of the present embodiment, the power supply voltage VDD is input to the reference voltage generation circuit 32 via the two LPFs, the LPF 12 and the LPF 42, so that the PSRR characteristics can be improved.

[Second Embodiment]
In the first embodiment, a mode in which the semiconductor device 10 includes one reference voltage generation circuit (reference voltage generation circuit 32) has been described. On the other hand, in the present embodiment, a mode in which the semiconductor device 10 includes a plurality of reference voltage generation circuits will be described. Since the semiconductor device 10 of the present embodiment includes the same configuration as the semiconductor device 10 of the first embodiment, detailed description of the same configuration will be omitted.

FIG. 3 shows a configuration diagram showing an outline of an example of the semiconductor device 10 of the present embodiment. As shown in FIG. 3, the semiconductor device 10 of the present embodiment includes a reference voltage generation circuit 32A and a reference voltage generation circuit 32B in place of the reference voltage generation circuit 32 of the semiconductor device 10 of the first embodiment.

The power supply voltage VDD input to the terminal 30 is input to the first reference voltage generation circuit 32A and the second reference voltage generation circuit 32B via the LPF42. The resistance element 44 of the LPF 42 is connected to the BGR 34A and the BGR 34B.

The first reference voltage generation circuit 32A includes BGR34A and AMP36A. The BGR 34A is connected to the terminal 30 via the LPF 42, and generates a reference voltage VREF1 from the input power supply voltage VDD. The AMP36A is connected to the terminal 30 and the BGR34A, and the reference voltage VREF1 generated by the BGR34A is amplified by the AMP36A. The reference voltage VREF1 amplified by the AMP 36A is output to the outside of the semiconductor device 10 via the terminal 40A. The terminal 40A in this case is an example of the first output terminal of the present disclosure.

On the other hand, the second reference voltage generation circuit 32B includes BGR34B and AMP36B. The BGR 34B is connected to the terminal 30 via the LPF 42, and generates a reference voltage VREF2 from the input power supply voltage VDD. The AMP36B is connected to the terminal 30 and the BGR34B, and the reference voltage VREF2 generated by the BGR34B is amplified by the AMP36B. The reference voltage VREF2 amplified by the AMP 36B is output to the outside of the semiconductor device 10 via the terminal 40B. The terminal 40B in this case is an example of the second output terminal of the present disclosure.

In the semiconductor device 10 of the present embodiment, the first reference voltage generation circuit 32A and the second reference voltage generation circuit 32B have the same configuration, and the BGR34A and BGR34B, and the AMP36A and AMP36B have the same configuration, respectively. .. Further, the first reference voltage generation circuit 32A and the second reference voltage generation circuit 32B have the same connection relationship with the terminal 30 and the LPF 42. Further, the reference voltage VREF1 and the reference voltage VREF2 have the same values when the error is ignored.

As described above, each of the first reference voltage generation circuit 32A and the second reference voltage generation circuit 32B in the semiconductor device 10 of the present embodiment is the same as the reference voltage generation circuit 32 in the semiconductor device 10 of the first embodiment.

Therefore, similarly to the semiconductor device 10 of the first embodiment, according to the semiconductor device 10 of the present embodiment, the power supply voltage VDD is set to the first reference voltage generation circuit 32A and the second reference voltage generation circuit 32A via two LPFs, LPF12 and LPF42. Since it is input to each of the reference voltage generation circuits 32B, the PSRR characteristics can be improved in each of the reference voltage VREF1 and the reference voltage VREF2.

In addition, unlike this embodiment, the voltage value of the reference voltage VREF1 generated by the first reference voltage generation circuit 32A and the voltage value of the reference voltage VREF2 generated by the second reference voltage generation circuit 32B may be different. Needless to say. In this case, if each of the first reference voltage generation circuit 32A and the second reference voltage generation circuit 32B includes BGR34A and AMP36A, or BGR34B and AMP36B according to the voltage values of the generated reference voltage VREF1 or reference voltage VREF2, good.

However, for example, when complying with the provisions of ISO 26262, which is a functional safety standard in the automobile field, it may be necessary to provide a plurality of reference voltage generation circuits that generate a similar reference voltage VREF. In such a case, as in the semiconductor device 10 of the present embodiment, the first reference voltage generation circuit 32A that generates the reference voltage VREF1 and the second reference voltage that generates the reference voltage VREF2 that is the same voltage value as the reference voltage VREF1. It is preferable to include a voltage generation circuit 32B.

Further, in the semiconductor device 10 of the present embodiment, a case where two reference voltage generation circuits, a first reference voltage generation circuit 32A and a second reference voltage generation circuit 32B, is provided has been described, but the semiconductor device 10 has three or more reference points. Needless to say, a voltage generation circuit may be provided. In this case, regardless of the number of reference voltage generation circuits included in the semiconductor device 10, the number of LPF 42s may be one.

[Third Embodiment]
In each of the above embodiments, the semiconductor device 10 that generates a reference voltage (VREF, or a reference voltage VREF1 and a reference voltage VREF2) based on a power supply voltage VDD input from the outside has been described. On the other hand, in the semiconductor device 10 of the present embodiment, a case where the power supply voltage VDD is generated internally will be described. Since the semiconductor device 10 of the present embodiment includes the same configuration as the semiconductor device 10 of the first embodiment, detailed description of the same configuration will be omitted.

FIG. 4 shows a configuration diagram showing an outline of an example of the semiconductor device 10 of the present embodiment. As shown in FIG. 4, in the semiconductor device 10 of the present embodiment, the power supply voltage VCC, which is higher than the power supply voltage VDD, is input to the terminal 30 via the LPF 12.

Further, the semiconductor device 10 of the present embodiment includes a high withstand voltage regulator circuit (hereinafter referred to as “REG”) 50 between the terminal 30 and the LPF 42. The REG50 converts (generates) the power supply voltage VCS input from the terminal 30 into the power supply voltage VDD and outputs it. The power supply voltage VDD generated by the REG 50 is supplied to the LPF 42 and output to the outside of the semiconductor device 10 via the terminal 52. The REG50 of the present embodiment is an example of the conversion circuit of the present disclosure.

As described above, the semiconductor device 10 of the present embodiment is the same as the semiconductor device 10 of the first embodiment except that the LPF 42 is connected to the REG 50 and the power supply voltage VDD is input from the REG 50 instead of the terminal 30. Is.

Therefore, similarly to the semiconductor device 10 of the first embodiment, according to the semiconductor device 10 of the present embodiment, the power supply voltage VDD is input to the reference voltage generation circuit 32 via the two LPFs, the LPF 12 and the LPF 42. , PSRR characteristics can be improved at the reference voltage VREF.

Although the case where one reference voltage generation circuit (reference voltage generation circuit 32) is provided in the semiconductor device 10 shown in FIG. 4 has been described, a plurality of reference voltage generation circuits are provided as in the second embodiment. Needless to say, it's good. As an example of this case, FIG. 5 shows a configuration diagram showing an outline of an example of the semiconductor device 10 of the present embodiment when the first reference voltage generation circuit 32A and the second reference voltage generation circuit 32B are provided. The semiconductor device 10 shown in FIG. 5 is a combination of the semiconductor device 10 of the present embodiment shown in FIG. 4 and the semiconductor device 10 shown in FIG. 3 of the second embodiment.

In the semiconductor device 10 shown in FIG. 5, similarly to the semiconductor device 10 shown in FIG. 4, the power supply voltage VDD is set to the first reference voltage generation circuit 32A and the second reference via the two LPFs LPF12 and LPF42. Since it is input to each of the voltage generation circuits 32B, the PSRR characteristics can be improved at each of the reference voltage VREF1 and the reference voltage VREF2.

[Fourth Embodiment]
The semiconductor device 10 of each of the above embodiments is preferably applied to a battery voltage monitoring system that monitors the battery voltage by measuring the battery voltage of the battery cell. In particular, as described above, it is preferable to apply the semiconductor device 10 shown in FIG. 5 in the third embodiment to the system for monitoring the battery voltage of the battery cell used in an automobile or the like. Therefore, in the present embodiment, the semiconductor device 10 is preferably applied. A battery monitoring system to which the semiconductor device 10 of FIG. 5 is applied will be described with reference to FIG.

The battery monitoring system 60 to which the semiconductor device 10 shown in FIG. 6 is applied has a function of measuring the battery voltage of each of the battery cells V of the battery 61 having a plurality of battery cells V connected in series. As an example, in the battery monitoring system 60 shown in FIG. 6, the case where the battery 61 includes n (n = 2) battery cells V (Vn, Vn-1) is shown, but the battery 61 is The number of battery cells V provided is not particularly limited.

The high potential side of the battery cell Vn is connected to the terminal 70n, and the voltage on the high potential side of the battery cell Vn is input to the terminal 70n. Further, the low potential side of the battery cell Vn and the low potential side of the battery cell Vn-1 are connected to the terminal 70n-1, and the voltage on the low potential side of the battery cell Vn (battery cell Vn-) is connected to the terminal 70n-1. The voltage on the high potential side of 1) is input. Further, the low potential side of the battery cell Vn-1 is connected to the terminal 70n-2, and the voltage on the low potential side of the battery cell Vn-1 is input to the terminal 70n-2.

As shown in FIG. 6, the voltage on the high potential side of the battery cell Vn is input as the power supply voltage VCS to the terminal 30 of the battery monitoring system 60 of the present embodiment via the LPF12. The power supply voltage VCS input to the terminal 30 is converted into the power supply voltage VDD by the REG50. The power supply voltage VDD is output from the terminal 52 and input to the first reference voltage generation circuit 32A and the second reference voltage generation circuit 32B via the LPF 42.

As shown in FIG. 6, the battery monitoring system 60 of the present embodiment includes a cell voltage measurement circuit 62A including a first reference voltage generation circuit 32A and a cell voltage measurement circuit 62B including a second reference voltage generation circuit 32B. I have.

The cell voltage measuring circuit 62A measures the battery voltage of each of the battery cells Vn-1 and Vn and outputs the measurement result. Further, the cell voltage measuring circuit 62B measures the battery voltage of each of the battery cells Vn-1 and Vn and outputs the measurement result. As described above, the battery monitoring system 60 of the present embodiment includes two measurement paths for measuring the battery voltage of each battery cell.

In the battery monitoring system 60 of the present embodiment, the battery voltage is monitored by measuring the battery voltage of the battery cell V to be measured under the control of an external MCU (Microcontroller) 80.

The cell voltage measuring circuit 62A further includes a cell selection switch (hereinafter referred to as “cell selection SW”) 64A, an analog level shifter 66A, an analog digital converter (hereinafter referred to as “A / D”) 68A, and a control unit 69A. There is. Further, the cell voltage measuring circuit 62B further includes a cell selection SW64B, an analog level shifter 66B, an A / D68B, and a control unit 69B. The cell selection SW64A and the cell selection SW64B of the present embodiment are examples of the cell selection unit of the present disclosure.

As described above, the cell voltage measuring circuit 62A and the cell voltage measuring circuit 62B differ only in whether the provided reference voltage generation circuit is the first reference voltage generation circuit 32A or the second reference voltage generation circuit 32B. Since the other parts are the same, the configuration and operation of the cell voltage measuring circuit 62A will be described in detail below, and the detailed description of the configuration and operation of the cell voltage measuring circuit 62B will be omitted.

The control unit 69A of the present embodiment is driven by the power supply voltage VDD supplied from the cell voltage measurement circuit 62A, and outputs a control signal for measuring the battery voltage to be measured according to the control of the MCU 80 of the battery monitoring system 60. Generate and output to cell selection SW64A. In FIG. 6, the description of the signal line connecting the control unit 69A and the cell selection SW64A is omitted in order to avoid complication. Further, the control unit 69A of the present embodiment transmits the measurement result input from the A / D 68A to the MCU 80 via a communication unit (not shown).

The cell selection SW64A is connected to terminals 70n-2 to 70n, and voltages corresponding to battery cells Vn and Vn-1 are input from each of the terminals 70n-2 to 70n. The cell selection SW64A selects a voltage corresponding to the battery cell V to be measured by the cell selection SW64A according to the control signal input from the control unit 69A, and outputs the selected voltage to the analog level shifter 66B. For example, the cell selection SW64A selects the voltage input from the terminal 70n and the voltage input from the terminal 70n-1 when the battery cell to be measured is the battery cell Vn, and selects these voltages as analog level shifters. Output to 66A.

The analog level shifter 66A outputs a differential voltage, which is a voltage difference according to the battery cell V input from the cell selection SW64A, at a level based on the ground potential. For example, when the battery cell to be measured is the battery cell Vn as described above, the differential voltage, which is the difference between the voltage input from the terminal 70n and the voltage input from the terminal 70n-1, is used as a reference for the ground potential. Output at level.

The A / D68A drives the reference voltage VREF1 supplied from the first reference voltage generation circuit 32A as a drive voltage to generate and output a digital signal corresponding to the difference voltage input from the analog level shifter 66A. This digital signal is output to the MCU 80 by the control unit 69B as a measurement result of the battery voltage of the battery cell V to be measured via a communication unit (not shown).

As described above, by applying the semiconductor device 10 of each of the above embodiments to the battery monitoring system 60, it is possible to improve the PSRR characteristics while suppressing an increase in cost and an increase in the circuit scale of the entire battery monitoring system 60. .. In particular, when a reference voltage generation circuit 32 that generates a similar reference voltage VREF is provided, such as when complying with the above-mentioned ISO26262 regulations, one LPF42 may be provided regardless of the number of reference voltage generation circuits 32, so that the cost is high. It is possible to improve the PSRR characteristics while further suppressing the increase in the voltage and the increase in the circuit scale of the battery monitoring system 60 as a whole.

As described above, in the semiconductor device 10 of each of the above embodiments, the power supply voltage VDD or the power supply voltage VDD converted from the power supply voltage VCS is input to the reference voltage generation circuit 32 via the two LPFs LPF12 and LPF42. NS. Therefore, according to the semiconductor device 10 of each of the above embodiments, the noise superimposed on the power supply voltage VDD can be blocked in two steps, so that the PSRR characteristics, particularly the PSRR characteristics in the intermediate frequency region, can be improved.

In the conventional semiconductor device 100 shown in FIG. 8 described above, in order to improve the PSRR characteristics in the intermediate frequency region, the capacitance value of the externally provided capacitive element 147 must be increased. On the other hand, in the semiconductor device 10 of each of the above embodiments, the PSRR characteristics are improved according to the time constant of the LPF 42. Here, the capacitance value of the capacitance element 46 of the LPF 42 may be relatively smaller than the capacitance value of the capacitance element 147 connected to the semiconductor device 100 of the prior art. Therefore, according to the semiconductor device 10 of each of the above embodiments, it is possible to suppress the cost and the increase in the scale of the entire circuit as compared with the semiconductor device 100 of the prior art.

Further, in the conventional semiconductor device 100, when a plurality of reference voltage generation circuits are to be provided, a capacitance element 147 is required for each reference voltage generation circuit. Therefore, both the cost and the scale of the entire circuit increase according to the number of reference voltage generation circuits included in the semiconductor device 100. On the other hand, in the semiconductor device 10 shown in FIG. 3 of the second embodiment and the semiconductor device 10 shown in FIG. 5 of the third embodiment, a plurality of reference voltage generation circuits (FIG. In 3 and 5, the PSRR characteristics can be improved for each of the first reference voltage generation circuit 32A and the second reference voltage generation circuit 32B). Therefore, according to the semiconductor device 10 of each of the above-described embodiments, it is possible to dramatically reduce the cost and suppress the increase in the scale of the entire circuit as compared with the semiconductor device 100 of the prior art.

Further, in the semiconductor device 10 of each of the above embodiments, when increasing the time constant of the LPF 42 in order to improve the PSRR characteristics, at least one of the resistance value of the resistance element 44 and the capacitance value of the capacitance element 46 may be increased. .. Therefore, in the semiconductor device 10 of each of the above embodiments, which of the resistance value of the resistance element 44 and the capacitance value of the capacitance element 46 should be increased, and what value each should be, is determined by the power supply voltage VDD by the resistance element 44. It can be appropriately selected according to the voltage drop, the cost of the capacitive element 46, the circuit scale, and the like.

In general, unlike the semiconductor device 10 of each of the above embodiments, when the PSRR characteristics are to be improved by using only the LPF 12, the time constant of the LPF 12 is increased. In this case, at least one of the resistance value of the resistance element 20 and the capacitance value of the capacitance element 22 is increased. When the resistance value of the resistance element 20 is increased, the voltage drop of the power supply voltage VDD becomes large. On the other hand, when the capacitance value of the capacitance element 22 is increased, the cost generally increases relatively. Therefore, it is often not very preferable to improve the PSRR characteristics of the semiconductor device 10 only by the LPF 12.

On the other hand, according to the semiconductor device 10 of each of the above-described embodiments, the LPF 42 functions as an auxiliary to the LPF 12 to improve the PSRR characteristics, so that the problem of voltage drop due to the above-mentioned resistance element 20 and the cost due to the capacitance element 22 are reduced. It is possible to suppress the rise and the like.

In each of the above embodiments, the case where the capacitance element 46 of the LPF 42 is provided outside the semiconductor device 10 and is connected to the resistance element 44 provided inside via the terminal 38 has been described. As shown, the capacitive element 46 may be provided in the semiconductor device 10. In this case, unlike the semiconductor device 10 of each of the above embodiments, the semiconductor device 10 shown in FIG. 7 does not have a terminal 38, and the resistance element 44 and the capacitance element 46 are connected without passing through the terminal 38. ..

Further, the configuration and operation of the semiconductor device 10 and the battery monitoring system 60 described in each of the other embodiments described above are examples, and can be changed depending on the situation within a range not deviating from the gist of the present invention. Not to mention.

10 Semiconductor device 12, 42 LPF
20, 44 Resistor elements 22, 46 Capacitive elements 30, 38, 40, 52 Terminals 32 Reference voltage generation circuit, 32A 1st reference voltage generation circuit, 32B 2nd reference voltage generation circuit 60 Battery monitoring system 61 Battery 62A, 62B Cell voltage Measurement circuit 64A, 64B Cell selection SW
68A, 68B A / D (analog-to-digital converter)
69A, 69B Control unit Vn, Vn-1 (V) Battery cell

Claims (8)

A second filter that filters signals according to the power supply voltage input from the input terminal via the first filter and has a time constant different from that of the first filter.
A reference voltage generation circuit that generates a reference voltage based on the signal filtered by the second filter and outputs a signal corresponding to the generated reference voltage to the outside via an output terminal.
Semiconductor device equipped with. The second filter is a low-pass filter including a resistance element and a capacitance element.
The semiconductor device according to claim 1. A capacitance element provided outside and a resistance element provided inside are provided so as to be connectable via a connection terminal, and the resistance element and the capacitance element are connected via the connection terminal. A second filter that filters signals according to the power supply voltage input from the input terminal via one filter and has a different time constant from the first filter.
A reference voltage generation circuit that generates a reference voltage based on the signal filtered by the second filter and outputs a signal corresponding to the generated reference voltage to the outside via an output terminal.
Semiconductor device equipped with. The output terminal includes a first output terminal and a second output terminal.
The reference voltage generation circuit generates a first reference voltage based on the signal filtered by the second filter, generates the first reference voltage, and outputs the first reference voltage via the first output terminal. Includes a circuit and a second reference voltage generation circuit that generates a second reference voltage based on a signal filtered by the second filter and outputs the generated second reference voltage via a second output terminal. ,
The semiconductor device according to any one of claims 1 to 3. A first power supply voltage is input to the input terminal, and the second filter is converted by a conversion circuit that converts the first power supply voltage input from the input terminal via the first filter into a second power supply voltage. The signal corresponding to the second power supply voltage is filtered.
The semiconductor device according to any one of claims 1 to 4. The semiconductor device according to any one of claims 1 to 5.
Control that drives a reference voltage output from the semiconductor device as a drive voltage and outputs a control signal for controlling the measurement of the battery voltage of the battery cell to be measured from a battery having a plurality of battery cells connected in series. Department and
The voltage at one end and the voltage at the other end of each of the plurality of battery cells are input, and a voltage corresponding to the battery cell to be measured is selected from the input voltage according to the control signal, and according to the selected voltage. A cell selection unit that outputs the signal
An analog-digital converter that drives a reference voltage output from the semiconductor device as a drive voltage, converts a signal corresponding to the voltage output from the cell selection unit into a digital signal, and outputs the signal to the control unit.
Battery monitoring system with. The signal corresponding to the power supply voltage input from the input terminal via the first filter is filtered by the second filter having a time constant different from that of the first filter.
A reference voltage is generated based on the signal filtered by the second filter.
Output the signal corresponding to the generated reference voltage to the outside via the output terminal,
Reference voltage generation method. A capacitance element provided outside and a resistance element provided inside are provided so as to be connectable via a connection terminal, and the resistance element and the capacitance element are connected via the connection terminal. The signal corresponding to the power supply voltage input from the input terminal via the 1 filter is filtered by the 2nd filter having a time constant different from that of the 1st filter.
A reference voltage is generated based on the signal filtered by the second filter.
Output the signal corresponding to the generated reference voltage to the outside via the output terminal,
Reference voltage generation method.

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