JP2020167229A - Semiconductor device - Google Patents

Abstract

To provide a semiconductor device capable of suppressing ringing during reverse recovery operation.SOLUTION: There is provided a semiconductor device 1 including: a semiconductor layer 2 having a first main surface 3; an n type drift region 10 formed on a surface portion of the first main surface 3; a p type body region 13 formed on a surface portion of the drift region 10; a p type column region 17 formed in the drift region 10 so as to extend from the body region 13 toward a bottom of the drift region 10; and an insulator 21 formed in a floating state in a region between the bottom of the drift region 10 and a bottom of the body region 13 in the semiconductor layer 2 so as to be overlapped on the column region 17 in planar view from a normal direction Z of the first main surface 3.SELECTED DRAWING: Figure 3

Description

The present invention relates to a semiconductor device.

Patent Document 1 discloses a semiconductor device including a semiconductor substrate and a super junction structure formed on the semiconductor substrate. The superjunction structure includes n-type semiconductor layers and p-type semiconductor layers alternately arranged in a direction parallel to the main surface of the semiconductor substrate.

Japanese Unexamined Patent Publication No. 2006-261562

One embodiment of the present invention provides a semiconductor device capable of suppressing ringing during reverse recovery operation.

One embodiment of the present invention comprises a semiconductor layer having a main surface, a first conductive type drift region formed on the surface layer portion of the main surface, and a second conductive type formed on the surface layer portion of the drift region. The body region, a second conductive column region formed in the drift region so as to extend from the body region toward the bottom of the drift region, and the column in a plan view seen from the normal direction of the main surface. Provided is a semiconductor device including an insulator formed in a floating state in a region between the bottom of the drift region and the bottom of the body region in the semiconductor layer so as to overlap the regions.

According to this semiconductor device, a part of the current flowing between the drift region and the column region can be shielded by an insulator during the reverse recovery operation. As a result, ringing during the reverse recovery operation can be suppressed.

FIG. 1 is a plan view showing a semiconductor device according to an embodiment of the present invention. FIG. 2 is an enlarged view of the region II shown in FIG. FIG. 3 is a cross-sectional view taken along the line III-III shown in FIG. 2, showing a form including an insulator according to the first embodiment. FIG. 4 is a cross-sectional view taken along the line IV-IV shown in FIG. FIG. 5A is a cross-sectional view corresponding to FIG. 3, showing a form including an insulator according to a second embodiment. FIG. 5B is a cross-sectional view corresponding to FIG. 3, showing a form including an insulator according to a third embodiment. FIG. 5C is a cross-sectional view corresponding to FIG. 3, showing a form including an insulator according to a fourth embodiment. FIG. 5D is a cross-sectional view corresponding to FIG. 3, showing a form including an insulator according to a fifth embodiment. FIG. 5E is a cross-sectional view corresponding to FIG. 3, showing a form including an insulator according to a sixth embodiment. FIG. 6 is a graph showing the reverse recovery characteristics of the semiconductor device. FIG. 7 is a cross-sectional view corresponding to FIG. 3, showing a form including an insulator according to the first modification. FIG. 8 is a cross-sectional view corresponding to FIG. 3, showing a form including an insulator according to a second modification. FIG. 9 is a cross-sectional view corresponding to FIG. 4, showing a form including an insulator according to a third modification.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
FIG. 1 is a plan view showing a semiconductor device 1 according to an embodiment of the present invention. FIG. 2 is an enlarged view of the region II shown in FIG. FIG. 3 is a cross-sectional view taken along the line III-III shown in FIG. 2, showing a form including the insulator 21 according to the first embodiment. FIG. 4 is a cross-sectional view taken along the line IV-IV shown in FIG. In FIG. 1, a part of the internal structure of the semiconductor device 1 is transparently shown in the region II.

With reference to FIGS. 1 to 4, the semiconductor device 1 is a semiconductor switching device including a MISFET (Metal Insulator Semiconductor Field Effect Transistor) as an example of an insulated gate type transistor. The semiconductor device 1 includes a semiconductor layer 2 formed in a rectangular parallelepiped shape. The semiconductor layer 2 is made of Si (silicon) in this form.
The semiconductor layer 2 includes a first main surface 3 on one side, a second main surface 4 on the other side, and side surfaces 5A, 5B, 5C, and 5D connecting the first main surface 3 and the second main surface 4. More specifically, the side surfaces 5A to 5D include a first side surface 5A, a second side surface 5B, a third side surface 5C, and a fourth side surface 5D.

The first main surface 3 and the second main surface 4 are formed in a quadrangular shape in a plan view (hereinafter, simply referred to as “plan view”) viewed from their normal direction Z. The first side surface 5A and the second side surface 5B extend along the first direction X and face the second direction Y intersecting the first direction X. More specifically, the second direction Y is orthogonal to the first direction X. The third side surface 5C and the fourth side surface 5D extend along the second direction Y and face the first direction X.

The semiconductor device 1 includes a gate terminal electrode 6 formed on the first main surface 3. The gate terminal electrode 6 is arranged on the first main surface 3 in a region along the third side surface 5C. In this embodiment, the gate terminal electrode 6 is arranged on the first main surface 3 in a region along the central portion of the third side surface 5C. The gate terminal electrode 6 may be arranged in a region along an arbitrary corner portion of the semiconductor layer 2 in a plan view. The gate terminal electrode 6 may be formed in a rectangular shape in a plan view.

The semiconductor device 1 includes a gate wiring electrode 7 connected to a gate terminal electrode 6 on the first main surface 3. The gate wiring electrode 7 is drawn out from the gate terminal electrode 6 in a strip shape. In this embodiment, the gate wiring electrode 7 extends from the gate terminal electrode 6 in a strip shape along the first side surface 5A, the second side surface 5B, and the third side surface 5C, and partitions the inner region of the semiconductor layer 2 from three directions. There is.
The semiconductor device 1 includes a source terminal electrode 8 formed on the first main surface 3 of the semiconductor layer 2. The source terminal electrode 8 is formed in a region partitioned by the gate terminal electrode 6 and the gate wiring electrode 7. The source terminal electrode 8 is formed on the first main surface 3 at a distance from the gate terminal electrode 6 and the gate wiring electrode 7.

The gate terminal electrode 6, the gate wiring electrode 7, and the source terminal electrode 8 are among the Ti layer, TiN layer, Ni layer, Pd layer, Au layer, Al layer, Cu layer, AlSiCu alloy layer, AlSi alloy layer, and AlCu alloy layer. It may contain at least one of each.
The gate terminal electrode 6, the gate wiring electrode 7, and the source terminal electrode 8 are composed of a Ti layer, a TiN layer, a Ni layer, a Pd layer, an Au layer, an Al layer, a Cu layer, an AlSiCu alloy layer, an AlSi alloy layer, or an AlCu alloy layer. Each may have a single-layer structure. The gate terminal electrode 6, the gate wiring electrode 7, and the source terminal electrode 8 are among the Ti layer, TiN layer, Ni layer, Pd layer, Au layer, Al layer, Cu layer, AlSiCu alloy layer, AlSi alloy layer, and AlCu alloy layer. Each of the above may have a laminated structure in which one or two or more of the above is laminated in any manner.

With reference to FIGS. 3 and 4, the semiconductor layer 2 includes an n-type drift region 10 and an n ⁺ -type drain region 11. The drift region 10 is formed on the surface layer portion of the first main surface 3 of the semiconductor layer 2. The drift region 10 forms the first main surface 3. The concentration of n-type impurities in the drift region 10 may be 1 × 10 ¹⁵ cm ^-3 or more and 1 × 10 ¹⁸ cm ^-3 or less.
The drift region 10 may have a thickness of 10 μm or more and 100 μm or less. The thickness of the drift region 10 may be 10 μm or more and 25 μm or less, 25 μm or more and 50 μm or less, 50 μm or more and 75 μm or less, or 75 μm or more and 100 μm or less. The thickness of the drift region 10 is preferably 45 μm or more and 65 μm or less.

The drain region 11 is formed in the semiconductor layer 2 in a region directly below the drift region 10. More specifically, the drain region 11 is formed in a region on the bottom side of the drift region 10 with respect to the drift region 10. The drain region 11 forms the second main surface 4.
The boundary between the drift region 10 and the drain region 11 extends parallel to the first main surface 3. The drain region 11 has an n-type impurity concentration that exceeds the n-type impurity concentration of the drift region 10. The concentration of n-type impurities in the drain region 11 may be 1 × 10 ¹⁸ cm ^-3 or more and 1 × 10 ²⁰ cm ^-3 or less.

The drain region 11 has a thickness exceeding the thickness of the drift region 10. The thickness of the drain region 11 may be 50 μm or more and 450 μm or less. The thickness of the drain region 11 may be 50 μm or more and 150 μm or less, 150 μm or more and 250 μm or less, 250 μm or more and 350 μm or less, or 350 μm or more and 450 μm or less. The thickness of the drain region 11 is preferably 150 μm or more and 350 μm or less.

The drift region 10 is formed by an n-type epitaxial layer in this form. In this form, the drain region 11 is formed of an n ⁺ type semiconductor substrate.
The semiconductor device 1 includes a drain terminal electrode 12 formed on the second main surface 4. The drain terminal electrode 12 is electrically connected to the drain region 11. The drain terminal electrode 12 may include at least one of a Ti layer, a Ni layer, an Au layer, an Ag layer and an Al layer. The drain terminal electrode 12 may have a single-layer structure including a Ti layer, a Ni layer, an Au layer, an Ag layer or an Al layer. The drain terminal electrode 12 may have a laminated structure in which one or two or more of the Ti layer, the Ni layer, the Au layer, the Ag layer and the Al layer are laminated in any manner.

The semiconductor device 1 includes a plurality of p-type body regions 13 formed on the surface layer portion of the drift region 10. The plurality of body regions 13 are exposed from the first main surface 3. The p-type impurity concentration in the body region 13 may be 1 × 10 ¹⁶ cm ^-3 or more and 1 × 10 ¹⁸ cm ^-3 or less.
The plurality of body regions 13 are formed in the surface layer portion of the drift region 10 at intervals in the first direction X, and are formed in a band shape extending along the second direction Y, respectively. As a result, the plurality of body regions 13 are formed in a striped shape as a whole in a plan view. Each body region 13 is formed at intervals from the bottom of the drift region 10 to the first main surface 3 side. As a result, the bottom of each body region 13 is located in the region between the first main surface 3 and the bottom of the drift region 10.

The semiconductor device 1 includes a plurality of n ⁺ type source regions 14 formed on the surface layer portions of the plurality of body regions 13. In this form, two source regions 14 are formed on the surface layer of each body region 13. The plurality of source regions 14 are exposed from the first main surface 3. Each of the plurality of source regions 14 has an n-type impurity concentration that exceeds the n-type impurity concentration of the drift region 10. The n-type impurity concentration of the plurality of source regions 14 may be 1 × 10 ¹⁹ cm ^-3 or more and 1 × 10 ²¹ cm ^-3 or less.

The plurality of source regions 14 are formed in the surface layer portion of each body region 13 at intervals in the first direction X, and are formed in a band shape extending along the second direction Y, respectively. Each source region 14 is formed at intervals from the bottom of the body region 13 to the first main surface 3 side. As a result, the bottom of each source region 14 is located in the region between the first main surface 3 and the bottom of the body region 13.

Each source region 14 is formed inward of each body region 13 at intervals from the edge of each body region 13. Each source region 14 defines a channel region 15 with a drift region 10 in the surface layer portion of each body region 13.
The semiconductor device 1 includes a plurality of p ⁺ type contact regions 16 formed on the surface layer portions of the plurality of body regions 13. In this form, one contact region 16 is formed in a region between a plurality of source regions 14 adjacent to each other in the surface layer portion of each body region 13. The plurality of contact regions 16 have a p-type impurity concentration that exceeds the p-type impurity concentration of the body region 13. The concentration of p-type impurities in the plurality of contact regions 16 may be 1 × 10 ¹⁹ cm ^-3 or more and 1 × 10 ²¹ cm ^-3 or less.

The plurality of contact regions 16 are formed in a band shape extending along the second direction Y. Each contact region 16 is formed at intervals from the bottom of the body region 13 to the first main surface 3 side. As a result, the bottom of each contact region 16 is located in the region between the first main surface 3 and the bottom of the body region 13.
The semiconductor device 1 includes a plurality of p-type column regions 17 formed in the drift region 10 so as to extend from the plurality of body regions 13 toward the bottom of the drift region 10. The plurality of column regions 17 are formed in a region between the bottom of each body region 13 and the bottom of the drift region 10. Each of the plurality of column regions 17 forms a pn junction with the drift region 10. As a result, the plurality of column regions 17 form an SJ (Super Junction) structure with the drift region 10.

The plurality of column regions 17 have a p-type impurity concentration lower than the p-type impurity concentration of the contact region 16. The p-type impurity concentration in the plurality of column regions 17 may be equal to the p-type impurity concentration in the body region 13. The p-type impurity concentration in the plurality of column regions 17 may exceed the p-type impurity concentration in the body region 13. The p-type impurity concentration in the plurality of column regions 17 may be less than the p-type impurity concentration in the body region 13.

The plurality of column regions 17 are formed at intervals in the first direction X, and are formed in a band shape extending along the second direction Y, respectively. The plurality of column regions 17 are formed in a one-to-one correspondence with the plurality of body regions 13. As a result, the plurality of column regions 17 are formed in a striped shape as a whole in a plan view.
Each column region 17 is formed in a region overlapping the central portion of each body region 13 in a plan view. Each column region 17 faces the contact region 16 with a part of each body region 13 interposed therebetween. The width WC of the first direction X of each column region 17 is less than the width WB of the first direction X of each body region 13 (WC <WB). Each width WC is the width of the widest region in each column region 17.

Each column area 17 is connected to a corresponding body area 13. Each column region 17 is formed at intervals from the bottom of the drift region 10 to the body region 13 side. More specifically, each column region 17 has a first end portion on the first main surface 3 side and a second end portion on the second main surface 4 side.
The first end of each column area 17 is connected to the corresponding body area 13. The second end of each column region 17 is formed at intervals from the bottom of the drift region 10 to the first main surface 3 side. As a result, the bottom of each column region 17 is located in the region between the bottom of the drift region 10 and the bottom of the body region 13.

In this form, each column region 17 has a laminated structure in which a plurality of column portions are laminated along the normal direction Z. The plurality of column portions are connected to each other in the stacking direction, and form one column region 17 as a whole. The number of column portions is arbitrary and is not limited to a specific value. The plurality of column portions may be formed by a multiepitaxial growth method in which a p-type impurity introduction step and an epitaxial growth step are alternately performed.

Each column region 17 includes eight column portions 18A, 18B, 18C, 18D, 18E, 18F, 18G, 18H, respectively, in this form. The first end of each column region 17 is formed by the top column portion 18H. The second end of each column region 17 is formed by the bottom column portion 18A.
The semiconductor device 1 includes a plurality of insulators 21 embedded in the semiconductor layer 2 so as to be suspended in a region between the bottom of the drift region 10 and the bottom of the body region 13. The plurality of insulators 21 are formed at positions overlapping the column region 17 in a plan view.

The plurality of insulators 21 may contain silicon oxide. The plurality of insulators 21 are formed, for example, by introducing oxygen molecules into the semiconductor layer 2 by an ion irradiation method and then reacting the silicon and oxygen molecules of the semiconductor layer 2 by a thermal oxidation method. The plurality of insulators 21 may be formed after the step of forming the column region 17, or may be formed prior to the step of forming the column region 17.

More specifically, the plurality of insulators 21 are formed at intervals in the first direction X, and are formed in a band shape extending along the second direction Y, respectively. Further, the plurality of insulators 21 are formed in a one-to-one correspondence with respect to the plurality of column regions 17. As a result, the plurality of insulators 21 are formed in a striped shape as a whole in a plan view.
The plurality of insulators 21 are formed at intervals from the body region 13 to the bottom side of the drift region 10. The plurality of insulators 21 are formed at intervals from the bottom of the drift region 10 to the body region 13 side. As a result, the plurality of insulators 21 are each formed in a floating state in the semiconductor layer 2.

It is preferable that the plurality of insulators 21 are formed in a region on the bottom side of the plurality of column regions 17 with respect to an intermediate portion in the depth direction of the plurality of column regions 17. The plurality of insulators 21 are in contact with each of the plurality of column regions 17 in this form.
Each of the plurality of insulators 21 is in contact with the bottom of the corresponding column region 17 in this form. More specifically, the plurality of insulators 21 include a portion in contact with the bottom of the corresponding column region 17 and a portion exposed from the bottom of the corresponding column region 17.

The exposed portions of the plurality of insulators 21 are in contact with the drift region 10. The plurality of insulators 21 face the drain region 11 with the drift region 10 interposed therebetween. The plurality of insulators 21 face the contact region 16 with the column region 17 and the body region 13 interposed therebetween in the normal direction Z.
The width WI of each insulator 21 in the first direction X is preferably less than the width WC of each column region 17 (WI <WC). The width WI of each insulator 21 may exceed the width WC of each column region 17 (WC <WI). The width WI of each insulator 21 may be equal to the width WC of each column region 17 (WC = WI).

It is preferable that each insulator 21 has a thickness TI (TI <TC) of less than the thickness TC of each column portion 18A to 18H in the normal direction Z. The thickness TI of each insulator 21 may exceed the thickness TC of each column portion 18A-18H (TC <TI). The thickness TI of each insulator 21 may be equal to the thickness TI of each column portion 18A-18H less than the thickness TC (TI = TC).

The plurality of insulators 21 may have the forms shown in FIGS. 5A to 5D.
FIG. 5A is a cross-sectional view corresponding to FIG. 3, showing a form including the insulator 21 according to the second embodiment. The structures corresponding to the structures shown in FIGS. 1 to 4 in FIG. 5A are designated by the same reference numerals and the description thereof will be omitted.
With reference to FIG. 5A, in this embodiment, the plurality of insulators 21 are formed in the bottom region of the plurality of column regions 17 with respect to the intermediate portion in the depth direction of the plurality of column regions 17. In this form, the plurality of insulators 21 are respectively embedded in the column region 17 in the region on the bottom side of the corresponding column region 17.

More specifically, the plurality of insulators 21 are embedded in the column portion 18A in the vicinity of the boundary between the corresponding column portion 18A and the column portion 18B, respectively. The plurality of insulators 21 are not exposed from the corresponding column region 17. The entire area of the plurality of insulators 21 is covered by the corresponding column regions 17.
FIG. 5B is a cross-sectional view corresponding to FIG. 3, showing a form including the insulator 21 according to the third embodiment. The structures corresponding to the structures shown in FIGS. 1 to 4 in FIG. 5B are designated by the same reference numerals and the description thereof will be omitted.

With reference to FIG. 5B, in this embodiment, the plurality of insulators 21 are formed in the bottom region of the plurality of column regions 17 with respect to the depth direction intermediate portion of the plurality of column regions 17. The plurality of insulators 21 are respectively embedded in the bottom of the corresponding column region 17 in this form.
More specifically, the plurality of insulators 21 are embedded in the column portion 18B in the vicinity of the boundary between the corresponding column portion 18B and the column portion 18C, respectively. The plurality of insulators 21 are not exposed from the corresponding column region 17. The entire area of the plurality of insulators 21 is covered by the corresponding column regions 17.

FIG. 5C is a cross-sectional view corresponding to FIG. 3, showing a form including the insulator 21 according to the fourth embodiment. The structures corresponding to the structures shown in FIGS. 1 to 4 in FIG. 5C are designated by the same reference numerals and the description thereof will be omitted.
With reference to FIG. 5C, the plurality of insulators 21 include, in this embodiment, a plurality of insulators 21A, 21B in contact with the corresponding column regions 17 at different depth positions. The plurality of insulators 21A and 21B are formed in the bottom region of the drift region 10 with respect to the depth direction intermediate portion of the corresponding column region 17, respectively. The plurality of insulators 21A and 21B are in contact with the bottom of the corresponding column region 17 in this form, respectively.

The plurality of insulators 21A and 21B are arranged in the corresponding column regions 17 at intervals along the normal direction Z. The plurality of insulators 21A and 21B are not exposed from the corresponding column region 17. The entire area of the plurality of insulators 21A and 21B is covered with the corresponding column region 17.
More specifically, the plurality of insulators 21A are embedded in the column portion 18A in the vicinity of the boundary between the corresponding column portion 18A and the column portion 18B. The plurality of insulators 21B are embedded in the column portion 18B in the vicinity of the boundary between the corresponding column portion 18B and the column portion 18C.

FIG. 5D is a cross-sectional view corresponding to FIG. 3, showing a form including the insulator 21 according to the fifth embodiment. The structures corresponding to the structures shown in FIGS. 1 to 4 in FIG. 5D are designated by the same reference numerals and the description thereof will be omitted.
With reference to FIG. 5D, the plurality of insulators 21 include, in this embodiment, a plurality of insulators 21A, 21B, 21C in contact with the corresponding column regions 17 at different depth positions. The plurality of insulators 21A to 21C are formed in the bottom region of the drift region 10 with respect to the depth direction intermediate portion of the corresponding column region 17. The plurality of insulators 21A to 21C are in contact with the bottom of the corresponding column region 17 in this form, respectively.

The plurality of insulators 21A to 21C are arranged in the corresponding column regions 17 at intervals along the normal direction Z. The plurality of insulators 21A to 21C are arranged at equal intervals in this form. The plurality of insulators 21A to 21C may be arranged at different intervals from each other. The plurality of insulators 21A to 21C are not exposed from the corresponding column region 17. The entire area of the plurality of insulators 21A to 21C is covered with the corresponding column region 17.

A plurality of insulators 21A are embedded in the column portion 18A near the boundary between the corresponding column portion 18A and the column portion 18B. The plurality of insulators 21B are embedded in the column portion 18B in the vicinity of the boundary between the corresponding column portion 18B and the column portion 18C. A plurality of insulators 21C are embedded in the column portion 18C in the vicinity of the boundary between the corresponding column portion 18C and the column portion 18D.

FIG. 5E is a cross-sectional view corresponding to FIG. 3, showing a form including the insulator 21 according to the sixth embodiment. The structures corresponding to the structures shown in FIGS. 1 to 4 in FIG. 5E are designated by the same reference numerals and the description thereof will be omitted.
With reference to FIG. 5E, the plurality of insulators 21 are formed in a floating state in the region between the bottom of the drift region 10 and the bottom of the column region 17 in the semiconductor layer 2, respectively. The plurality of insulators 21 are formed one by one in the region between the bottom of the drift region 10 and the bottom of the column region 17. The plurality of insulators 21 are formed at intervals from the drift region 10 and the column region 17. That is, the plurality of insulators 21 are not in contact with the drift region 10 and the column region 17.

With reference to FIGS. 1 to 4 again, the semiconductor device 1 includes a plurality of planar gate structures 31 (gate structures) formed on the first main surface 3 of the semiconductor layer 2. The plurality of planar gate structures 31 are formed at intervals in the first direction X, and are formed in a strip shape extending along the second direction Y, respectively.
The plurality of planar gate structures 31 are respectively arranged in the region between the plurality of body regions 13 adjacent to each other. As a result, the plurality of planar gate structures 31 are formed in a striped shape as a whole in a plan view. The plurality of planar gate structures 31 are formed at intervals from the plurality of insulators 21 in a plan view. The plurality of planar gate structures 31 do not overlap the plurality of insulators 21 in a plan view.

The plurality of planar gate structures 31 include a gate insulating layer 32 and a gate electrode 33, respectively. The gate insulating layer 32 covers the drift region 10, the body region 13, the source region 14, and the channel region 15. More specifically, the gate insulating layer 32 is formed so as to straddle two body regions 13 adjacent to each other with the drift region 10 in between.
The gate insulating layer 32 covers the source region 14 and the channel region 15 on one body region 13 side, and covers the source region 14 and the channel region 15 on the other body region 13 side. The gate insulating layer 32 may contain at least one of silicon oxide, silicon nitride and aluminum oxide.

The gate electrode 33 is formed on the gate insulating layer 32. The gate electrode 33 faces the drift region 10, the body region 13, the source region 14, and the channel region 15 with the gate insulating layer 32 interposed therebetween.
The gate electrode 33 may contain at least one of conductive polysilicon, tungsten, aluminum, copper, aluminum alloy and copper alloy. The gate electrode 33 includes conductive polysilicon in this form. The gate electrode 33 may include n-type polysilicon or p-type polysilicon.

The semiconductor device 1 includes a main surface insulating layer 40 that collectively covers a plurality of planar gate structures 31 on the first main surface 3. The main surface insulating layer 40 may contain silicon oxide. A plurality of contact holes 41 are formed in the main surface insulating layer 40. The plurality of contact holes 41 are formed in a one-to-one correspondence with respect to the plurality of body regions 13.
Each contact hole 41 exposes a plurality of source regions 14 and contact regions 16 formed in the corresponding body regions 13. Each contact hole 41 overlaps the column region 17 and the insulator 21 in a plan view.

The source terminal electrode 8 described above is formed on the main surface insulating layer 40. The source terminal electrode 8 enters into each contact hole 41 from above the main surface insulating layer 40. The source terminal electrode 8 is electrically connected to a plurality of source regions 14 and contact regions 16 in each contact hole 41.
A gate contact hole (not shown) for exposing the gate electrode 33 is formed in a region of the main surface insulating layer 40 (not shown). The gate wiring electrode 7 described above is connected to the gate electrode 33 via a gate contact hole. As a result, the gate terminal electrode 6 described above is electrically connected to the gate electrode 33 via the gate wiring electrode 7.

FIG. 6 is a graph for explaining the reverse recovery characteristic of the semiconductor device 1. In FIG. 6, the vertical axis represents the current [A] and the horizontal axis represents the time [sec].
When the semiconductor device 1 changes from the bias state to the reverse bias state, the semiconductor device 1 goes to the off state through the first phase, the second phase, and the third phase in which the current states are different. The first phase is the period during which the forward current IF decreases at the reduction rate dIF / dT.

The second phase is the period during which the reverse recovery current IR flows. The reverse recovery current IR decreases to the peak value Irr after the first reverse recovery time Ta, and recovers from the peak value Irr to the zero point after the second reverse recovery time Tb. The reverse recovery time Trr is defined by the total value of the first reverse recovery time Ta and the second reverse recovery time Tb.
The third phase is a ringing period in which the forward current IF and the reverse recovery current IR flow alternately. In the third phase, a ringing waveform including a positive first ringing portion R1, a negative second ringing portion R2, and a positive third ringing portion R3 is formed.

The first ringing unit R1 has a first peak value P1 of the forward current IF. The second ringing unit R2 has a second peak value P2 of the reverse recovery current IR. The third ringing unit R3 has a third peak value P3 of the forward current IF. The absolute value of the second peak value P2 is less than the absolute value of the first peak value P1 (| P2 | << | P1 |). The absolute value of the third peak value P3 is less than the absolute value of the second peak value P2 (| P3 | << | P2 | <| P1 |).

Table 1 shows the results of simulating the absolute value of the first peak value P1, the absolute value of the second peak value P2, and the absolute value of the third peak value P3. Table 1 shows the measurement results of the semiconductor device according to the comparative example and the semiconductor device 1 having the insulator 21 according to the first to sixth embodiments. The semiconductor device according to the comparative example does not have the insulator 21.
Table 1 shows the first peak according to the first to sixth embodiments when the first peak value P1, the second peak value P2 and the third peak value P3 according to the comparative example are set to “1.00”, respectively. The ratio of the value P1, the ratio of the second peak value P2, and the ratio of the third peak value P3 are shown, respectively.

With reference to Table 1, the first peak value P1 according to the first to sixth forms was less than the first peak value P1 according to the comparative example. The second peak value P2 according to the first to sixth forms was less than the second peak value P2 according to the comparative example except for the third form. The third peak value P3 according to the first to sixth forms was less than the third peak value P3 according to the comparative example except for the second form example and the third form example.

In the second form example, the third peak value P3 increased, and in the third form example, the second peak value P2 and the third peak value P3 increased, but the insulator 21 according to the first to sixth forms was formed. As a result, the first peak value P1, which is the largest value, could be reduced. In the second form example and the third form example, it is considered that the second peak value P2 and the third peak value P3 can be improved by finely adjusting the arrangement of the insulator 21.

In this way, it was found that ringing during the reverse recovery operation can be suppressed by forming the insulator 21 according to the first to sixth embodiments. Further, it was found that the first peak value P1, the second peak value P2, and the third peak value P3 can be adjusted by adjusting the arrangement and the number of the insulators 21 with respect to one column region 17.
As described above, according to the semiconductor device 1, any one of the insulators 21 according to the first to sixth embodiments is included. The insulator 21 is embedded in the semiconductor layer 2 so as to be suspended in a region between the bottom of the drift region 10 and the bottom of the body region 13 so as to overlap the column region 17 in a plan view. As a result, a part of the current flowing between the drift region 10 and the column region 17 can be shielded by the insulator 21 during the reverse recovery operation. As a result, ringing during the reverse recovery operation can be suppressed.

More specifically, the insulator 21 retains holes, which are a large number of carriers, in the region immediately below the insulator 21 during the reverse recovery operation. As a result, the rapid movement of holes, which are a large number of carriers, can be suppressed, so that ringing during the reverse recovery operation can be suppressed.
Further, according to the semiconductor device 1, the insulator 21 formed in the region on the bottom side of the column region 17 with respect to the intermediate portion in the depth direction of the column region 17 is included. In the ringing period (third phase) during the reverse recovery operation, the depletion layer extending from the column region 17 expands and contracts (vibrates) near the bottom of the column region 17.

Therefore, due to the expansion and contraction of the depletion layer, holes flow from the region on the bottom side of the column region 17 into the drift region 10, and holes flow from the drift region 10 into the region on the bottom side of the column region 17. Therefore, by arranging the insulator 21 in the region on the bottom side of the column region 17 with respect to the intermediate portion in the depth direction of the column region 17, holes can be appropriately retained during the reverse recovery operation. As a result, ringing during the reverse recovery operation can be appropriately suppressed.

Although the embodiment of the present invention has been described, the embodiment of the present invention can be implemented in other embodiments.
In the above-described embodiment, an example in which each column region 17 includes a plurality of column portions 18A to 18H has been described. However, a column region 17 that does not have a plurality of column portions 18A to 18H may be formed. As an example, the plurality of column regions 17 may include a trench formed on the first main surface 3 and a p-type polysilicon layer embedded in the trench, respectively.

In the above-described embodiment, an example in which the semiconductor layer 2 made of silicon is adopted has been described. However, in the above-described embodiment, the semiconductor layer 2 made of a wide bandgap semiconductor may be adopted. The semiconductor layer 2 may be made of SiC (silicon carbide) as an example of a wide bandgap semiconductor.
In the above-described embodiment, a structure in which the conductive type of each semiconductor portion is inverted may be adopted. That is, the p-type portion may be n-type and the n-type portion may be p-type.

In the above-described embodiment, a p ⁺ type impurity region may be adopted instead of the drain region 11. According to this structure, an IGBT (Insulated Gate Bipolar Transistor) can be provided instead of the MISFET. In this case, in the above-described embodiment, the "source" of the MISFET is read as the "emitter" of the IGBT, and the "drain" of the MISFET is read as the "collector" of the IGBT.

In the above-described embodiment, the number and arrangement of the insulators 21 are arbitrary as long as ringing during the reverse recovery operation can be suppressed, and are not limited to a specific number and arrangement. A form in which at least two of the insulators 21 according to the first to sixth forms are combined may be adopted. Further, the plurality of insulators 21 may have the forms shown in FIGS. 7 to 9.
FIG. 7 is a cross-sectional view corresponding to FIG. 3, showing a form including the insulator 21 according to the first modification. Hereinafter, the structures corresponding to the structures described in FIGS. 1 to 6 are designated by the same reference numerals and the description thereof will be omitted.

With reference to FIG. 7, the plurality of insulators 21 includes a plurality of insulators 21A, 21B, 21C, 21D, 21E, 21F, 21G that are in contact with the corresponding column regions 17 at different depth positions. The plurality of insulators 21A to 21G are formed in a region on the bottom side of the drift region 10 and a region on the body region 13 side with respect to the intermediate portion in the depth direction of the corresponding column region 17, respectively.

The plurality of insulators 21A to 21G are arranged in the corresponding column regions 17 at intervals along the normal direction Z. The plurality of insulators 21A to 21G are arranged at equal intervals in this form. The plurality of insulators 21A to 21G may be arranged at different intervals from each other. The plurality of insulators 21A to 21G are not exposed from the corresponding column region 17. The entire area of the plurality of insulators 21A to 21G is covered with the corresponding column region 17.

A plurality of insulators 21A are embedded in the column portion 18A near the boundary between the corresponding column portion 18A and the column portion 18B. The plurality of insulators 21B are embedded in the column portion 18B in the vicinity of the boundary between the corresponding column portion 18B and the column portion 18C.
A plurality of insulators 21C are embedded in the column portion 18C in the vicinity of the boundary between the corresponding column portion 18C and the column portion 18D. A plurality of insulators 21D are embedded in the column portion 18D near the boundary between the corresponding column portion 18D and the column portion 18E.

A plurality of insulators 21E are embedded in the column portion 18E in the vicinity of the boundary between the corresponding column portion 18E and the column portion 18F. A plurality of insulators 21F are embedded in the column portion 18F in the vicinity of the boundary between the corresponding column portion 18F and the column portion 18G. A plurality of insulators 21G are embedded in the column portion 18G in the vicinity of the boundary between the corresponding column portion 18G and the column portion 18H.

FIG. 8 is a cross-sectional view corresponding to FIG. 3, showing a form including the insulator 21 according to the second modification. Hereinafter, the structures corresponding to the structures described in FIGS. 1 to 6 are designated by the same reference numerals and the description thereof will be omitted.
With reference to FIG. 8, the plurality of insulators 21 includes a plurality of insulators 21A, 21B, 21C that are in contact with the corresponding column regions 17 at different depth positions. The plurality of insulators 21A to 21C are formed in the region on the body region 13 side with respect to the depth direction intermediate portion of the corresponding column region 17, respectively.

The plurality of insulators 21A to 21C are arranged in the corresponding column regions 17 at intervals along the normal direction Z. The plurality of insulators 21A to 21C are arranged at equal intervals in this form. The plurality of insulators 21A to 21C may be arranged at different intervals from each other. The plurality of insulators 21A to 21C are not exposed from the corresponding column region 17. The entire area of the plurality of insulators 21A to 21C is covered with the corresponding column region 17.

A plurality of insulators 21A are embedded in the column portion 18E near the boundary between the corresponding column portion 18E and the column portion 18F. The plurality of insulators 21B are embedded in the column portion 18F in the vicinity of the boundary between the corresponding column portion 18F and the column portion 18G. A plurality of insulators 21C are embedded in the column portion 18G in the vicinity of the boundary between the corresponding column portion 18G and the column portion 18H.

FIG. 9 is a cross-sectional view corresponding to FIG. 4, and shows an insulator 21 according to a third modification. Hereinafter, the structures corresponding to the structures described in FIGS. 1 to 6 are designated by the same reference numerals and the description thereof will be omitted.
With reference to FIG. 9, each insulator 21 includes, in this form, a plurality of portions 50 formed at intervals along the first direction X. The structure in which each insulator 21 includes a plurality of portions 50 can be applied to the insulator 21 according to the first to sixth embodiments and the insulator 21 according to the first and second modifications.

Although the embodiments of the present invention have been described in detail, these are only specific examples used for clarifying the technical contents of the present invention, and the present invention is construed as being limited to these specific examples. Should not, the scope of the invention is limited only by the appended claims.

1 Semiconductor device 2 Semiconductor layer 3 First main surface 4 Second main surface 6 Gate terminal electrode 8 Source terminal electrode 10 Drift region 11 Drain region 12 Drain terminal electrode 13 Body region 14 Source region 16 Contact region 17 Column region 21 Insulator 32 Gate insulating layer 33 Gate electrode

Claims (19)

A semiconductor layer with a main surface and
The first conductive type drift region formed on the surface layer of the main surface and
A second conductive body region formed on the surface layer of the drift region and
A second conductive column region formed in the drift region so as to extend from the body region toward the bottom of the drift region,
An insulator formed in a floating state in a region between the bottom of the drift region and the bottom of the body region in the semiconductor layer so as to overlap the column region in a plan view seen from the normal direction of the main surface. , Including semiconductor devices. The semiconductor device according to claim 1, wherein the insulator is formed at a distance from the bottom of the body region to the drift region side. The semiconductor device according to claim 1 or 2, wherein the insulator is formed at intervals from the bottom of the drift region to the body region side. The semiconductor device according to any one of claims 1 to 3, wherein the insulator is formed in a region on the bottom side of the column region with respect to an intermediate portion in the depth direction of the column region. The semiconductor device according to any one of claims 1 to 4, wherein the insulator is in contact with the column region. The semiconductor device according to claim 5, wherein the insulator is in contact with the bottom of the column region. The semiconductor device according to claim 5 or 6, wherein the insulator includes a portion in contact with the bottom of the column region and a portion exposed from the bottom of the column region. The semiconductor device according to claim 5 or 6, wherein the insulator is embedded in the bottom of the column region. The semiconductor device according to any one of claims 5 to 8, wherein a plurality of the insulators are formed so as to be in contact with the column region at different depth positions. The semiconductor device according to any one of claims 1 to 4, wherein the insulator is formed in a region between the bottom of the drift region and the bottom of the column region. The semiconductor device according to claim 10, wherein the insulator is formed at a distance from the drift region and the column region. The semiconductor device according to any one of claims 1 to 11, wherein the insulator has a width less than the width of the column region. A second conductive type contact region formed on the surface layer portion of the body region and having a second conductive type impurity concentration exceeding the second conductive type impurity concentration of the body region is further included.
The semiconductor device according to any one of claims 1 to 12, wherein the insulator faces the contact region in the normal direction. The semiconductor layer further includes a first conductive type drain region formed in a region immediately below the drift region and having a first conductive type impurity concentration exceeding the first conductive type impurity concentration in the drift region.
The semiconductor device according to any one of claims 1 to 13, wherein the column region is formed in the drift region at intervals from the drain region to the main surface side. The semiconductor device according to claim 14, wherein the drain region has a thickness exceeding the thickness of the drift region. The first conductive type source region formed on the surface layer of the body region and
A gate insulating layer formed on the main surface and facing the drift region, the body region, and the source region.
The aspect of any one of claims 1 to 15, further comprising a gate electrode formed on the gate insulating layer and facing the drift region, the body region and the source region with the gate insulating layer interposed therebetween. The semiconductor device described. The semiconductor device according to claim 16, further comprising a gate terminal electrode electrically connected to the gate electrode on the main surface. The semiconductor device according to claim 16 or 17, further comprising a source terminal electrode electrically connected to the source region on the main surface. The semiconductor device according to any one of claims 1 to 18, further comprising a drain terminal electrode electrically connected to the semiconductor layer on the opposite surface of the main surface.

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