JP7147510B2 - switching element - Google Patents

Description

The technology disclosed in this specification relates to switching elements.

A switching element disclosed in Patent Document 1 has a gate insulating film and a gate electrode arranged in a trench. A semiconductor substrate has a source region, a body region, a drift region, and a bottom region. The source region is n-type and is in contact with the gate insulating film. The body region is p-type and is in contact with the gate insulating film below the source region. The drift region is n-type and is in contact with the gate insulating film below the body region. The bottom region is p-type and is located below the bottom surface of the trench. In addition, the switching element has a p-type connection region arranged so as to be in contact with part of the side surface of the trench. A connection region extends along the sides of the trench and connects the body region and the bottom region. The connection region is provided to stabilize the potential of the bottom region.

When the switching element is turned off, the depletion layer extends from the bottom region to the surrounding drift region, thereby suppressing electric field concentration near the bottom of the trench. A switching element with a bottom region and a connection region therefore has a high breakdown voltage.

When the switching element is turned on, a channel is formed in the body region. In a region where the drift region is arranged below the body region, the channel connects to the drift region. Thus, the channel connects the drift region and the source region, allowing current to flow between the drift region and the source region. Hereinafter, the region where the drift region is provided below the body region (that is, the region through which the current flows when the switching element is turned on) is called the active region.

On the other hand, even if a channel is formed in the region where the connection region is arranged, the channel is not connected to the drift region and little current flows. Hereinafter, a region in which the connection region is provided (that is, a region in which almost no current flows when the switching element is turned on) will be referred to as a non-active region.

JP 2007-242852 A

Since the connection region is made of a p-type semiconductor, it has a relatively high electrical resistance. In the switching element of Patent Document 1, it is necessary to provide a connection region over a relatively wide range in order to connect the body region and the bottom region with low resistance. That is, it is necessary to provide a non-active region over a relatively wide range. As described above, no current flows in the inactive region when the switching element is turned on. If the non-active region is provided over a wide range, it becomes difficult to pass current through the switching element at a high density, and the size of the switching element increases. Therefore, the present specification proposes a technique that allows the bottom region to be connected to the body region with low resistance.

A switching element disclosed in the present specification includes a semiconductor substrate having a trench on its upper surface, a gate insulating film covering the inner surface of the trench, and a gate insulating film disposed in the trench and the semiconductor substrate through the gate insulating film. and a low resistance film. The semiconductor substrate includes an n-type source region in contact with the gate insulating film, a p-type body region in contact with the gate insulating film below the source region, and below the bottom surface of the trench. It has a p-type bottom region, an n-type drift region, and a p-type connection region located therein. The semiconductor substrate has an active area and a non-active area. The drift region contacts the gate insulating film below the body region in the active region. The low resistance film has a lower electrical resistance than the connection region, is insulated from the gate electrode, and extends from the depth of the body region along the sides of the trench within the non-active region. It extends to the depth of the bottom region. The connection region extends in contact with the low resistance film within the non-active region and connects the body region and the bottom region.

In this switching element, a low resistance film is provided in the non-active region, extending from the depth of the body region to the depth of the bottom region along the sides of the trench. A connection region extends in contact with the low resistance film to connect the body region and the bottom region. The low resistance film reduces the electrical resistance between the body region and the bottom region. Therefore, in this switching element, the body region and the bottom region can be connected with low resistance without providing a wide non-active region.

2 is a plan view of the switching element 10; FIG. Sectional drawing in the II-II line of FIG. Sectional drawing in the III-III line of FIG. Sectional drawing corresponding to FIG. 3 of the switching element of a 1st modification. Sectional drawing corresponding to FIG. 3 of the switching element of a 2nd modification. Sectional drawing corresponding to FIG. 3 of the switching element of a 3rd modification. Sectional drawing corresponding to FIG. 3 of the switching element of a 4th modification. Sectional drawing corresponding to FIG. 2 of the switching element of a 5th modification. FIG. 11 is an enlarged cross-sectional view of a low-resistance film of a switching element of a sixth modification;

The switching element 10 of the embodiment shown in FIGS. 1-3 is a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). The switching element 10 includes a semiconductor substrate 12, electrodes, an insulating layer, and the like. In FIG. 1, the electrodes and insulating layers on the upper surface 12a of the semiconductor substrate 12 are omitted for the sake of clarity. Hereinafter, one direction parallel to the upper surface 12a of the semiconductor substrate 12 is called the x direction, the direction parallel to the upper surface 12a and perpendicular to the x direction is called the y direction, and the thickness direction of the semiconductor substrate 12 is called the z direction. The semiconductor substrate 12 is a SiC substrate whose main material is SiC (silicon carbide).

As shown in FIG. 1, a lattice trench 22 is provided in the upper surface 12a of the semiconductor substrate 12 . The lattice trench 22 has a plurality of trenches 22a elongated in the x-direction and a plurality of trenches 22b elongated in the y-direction. The multiple trenches 22a are arranged at intervals in the y direction. The multiple trenches 22b are arranged at intervals in the x direction. Each trench 22b extends across the plurality of trenches 22a and is connected to the plurality of trenches 22a.

As shown in FIGS. 2 and 3, the inner surface of lattice trench 22 is covered with gate insulating film 24 . A gate electrode 26 is arranged in the grid trench 22 . Gate electrode 26 is insulated from semiconductor substrate 12 by gate insulating film 24 . The gate electrode 26 inside the trench 22a is connected to the gate electrode 26 inside the trench 22b. An upper surface of the gate electrode 26 is covered with an interlayer insulating film 28 .

As shown in FIGS. 2 and 3, an upper electrode 70 is arranged on the upper surface 12 a of the semiconductor substrate 12 . The upper electrode 70 is in contact with the upper surface 12a of the semiconductor substrate 12 at a portion where the interlayer insulating film 28 is not provided. The upper electrode 70 is insulated from the gate electrode 26 by the interlayer insulating film 28 . A lower electrode 72 is arranged on the lower surface 12 b of the semiconductor substrate 12 . The lower electrode 72 is in contact with the lower surface 12 b of the semiconductor substrate 12 .

As shown in FIGS. 2 and 3, semiconductor substrate 12 includes source region 30 , body region 32 , drift region 33 , drain region 34 , bottom region 36 and connection region 38 . Further, as shown in FIG. 3, a low resistance film 40 is provided inside the semiconductor substrate 12 .

Source region 30 is an n-type region. As shown in FIGS. 1 to 3, the source region 30 is arranged in a range facing the upper surface 12a of the semiconductor substrate 12 and is in ohmic contact with the upper electrode . As shown in FIG. 1, source regions 30 are provided along the sides of grid trenches 22 . As shown in FIG. 2, the source region 30 is in contact with the gate insulating film 24 on the side surface of the trench 22a.

Body region 32 is a p-type region. As shown in FIGS. 1-3, the body region 32 has a body contact region 32a and a main body region 32b. Body contact region 32a has a higher p-type impurity concentration than main body region 32b. Body contact region 32 a is arranged in a range facing upper surface 12 a of semiconductor substrate 12 and is in ohmic contact with upper electrode 70 . As shown in FIG. 1 , body contact region 32 a is arranged in a range surrounded by source region 30 . As shown in FIGS. 2 and 3, the main body region 32b is located below the source region 30 and the body contact region 32a. As shown in FIG. 2, the main body region 32b is in contact with the gate insulating film 24 on the side surfaces of the trench 22a. The main body region 32 b is in contact with the gate insulating film 24 below the source region 30 . The lower end of the main body region 32b is arranged above the lower end of the gate electrode 26. As shown in FIG.

Drift region 33 is an n-type region. As shown in FIGS. 2 and 3, the drift region 33 is arranged below the main body region 32b. As shown in FIG. 2, the drift region 33 is in contact with the gate insulating film 24 on the side surfaces of the trench 22a. The drift region 33 is in contact with the gate insulating film 24 below the main body region 32b. Drift region 33 is separated from source region 30 by body region 32 .

The drain region 34 is an n-type region having a higher n-type impurity concentration than the drift region 33 . As shown in FIGS. 2 and 3, the drain region 34 is located below the drift region 33 . The drain region 34 is arranged in a range facing the lower surface 12 b of the semiconductor substrate 12 . Drain region 34 is in ohmic contact with lower electrode 72 .

Bottom region 36 is a p-type region. As shown in FIGS. 2 and 3, the bottom region 36 contacts the gate insulating film 24 at the bottom surfaces of the trenches 22a and 22b. The bottom region 36 extends along the bottom surface of the grid trench 22 in a grid pattern. The bottom region 36 contacts the gate insulating film 24 over the entire bottom surface of the grid trench 22 . Bottom region 36 contacts drift region 33 . In the vicinity of trench 22a, bottom region 36 is separated from body region 32 by drift region 33, as shown in FIG.

A dashed line in FIG. 1 indicates a range in which the connection region 38 and the low resistance film 40 are provided. As shown in FIGS. 1 and 3, the connection region 38 and the low resistance film 40 are provided in a range in contact with the trench 22b. As shown in FIGS. 1 and 2, the connection region 38 and the low-resistance film 40 are not provided in the range in contact with the trench 22a (excluding the crossing portion of the trench 22a and the trench 22b).

The low resistance film 40 is a thin film made of metal. As shown in FIG. 3, the low resistance film 40 is in contact with the gate insulating film 24 over the entire side surface of the trench 22b. That is, the low resistance film 40 is provided at the interface between the gate insulating film 24 and the semiconductor substrate 12 . The low resistance film 40 is insulated from the gate electrode 26 by the gate insulating film 24 . The electrical resistance of the low resistance film 40 is lower than that of the connection region 38 . The low resistance film 40 extends from the upper end to the lower end of the side surface of the trench 22b. That is, the low resistance film 40 extends from the depth of the source region 30 to the depth of the bottom region 36 . A lower end of the low-resistance film 40 is in contact with the bottom region 36 .

Connection region 38 is a p-type region. As shown in FIG. 3, the connection region 38 is in contact with the side surface of the low resistance film 40 . The connection region 38 extends from the top end to the bottom end of the low resistance film 40 . Connection region 38 contacts source region 30 , main body region 32 b , drift region 33 and bottom region 36 . A connection region 38 connects the bottom region 36 to the main body region 32b.

As shown in FIG. 2, the region below the main body region 32b where the drift region 33 is in contact with the gate insulating film 24 is an active region through which current flows when the switching element 10 is turned on. As shown in FIG. 3, the region where the connection region 38 is arranged in the vicinity of the trench 22b (the region where the drift region 33 is not in contact with the gate insulating film 24) is a non-conductive region in which almost no current flows when the switching element 10 is turned on. Active area.

Next, operation of the switching element 10 will be described. When the switching element 10 is used, a potential higher than that of the upper electrode 70 is applied to the lower electrode 72 . When a gate-on potential (potential higher than the gate threshold) is applied to the gate electrode 26, a channel (inversion layer) is formed in the p-type region (that is, the main body region 32b and the connection region 38) in contact with the gate insulating film 24. be. In the cross section (active region) shown in FIG. 2, when a channel is formed in main body region 32b, source region 30 is connected to drift region 33 by the channel. Therefore, electrons flow from the upper electrode 70 to the lower electrode 72 via the source region 30 , the channel, the drift region 33 and the drain region 34 . That is, current flows in the active region. On the other hand, in the cross section (inactive region) shown in FIG. 3, even if a channel is formed in the connection region 38, the channel is not connected to the drift region 33 because the lower end of the connection region 38 is connected to the bottom region 36. Therefore, almost no current flows through the channel formed in the non-active region. Thus, when the switching element 10 is turned on, current mainly flows through the active region.

When the potential of the gate electrode 26 is lowered to the gate-off potential (potential below the gate threshold), the channel disappears and the switching element 10 is turned off. When the switching element 10 is turned off, the potential of the lower electrode 72 rises. Since the drift region 33 is connected to the lower electrode 72 via the drain region 34, the potential of the drift region 33 increases as the potential of the lower electrode 72 increases. On the other hand, since the main body region 32b is connected to the upper electrode 70 via the body contact region 32a, the potential of the main body region 32b is maintained substantially at the same potential as that of the upper electrode 70. FIG. Therefore, a high reverse voltage is applied to the pn junction at the interface between the main body region 32b and the drift region 33. FIG. Therefore, when the switching element 10 is turned off, a depletion layer spreads from the main body region 32b to the drift region 33. FIG. A depletion layer extending in the drift region 33 maintains the potential difference between the lower electrode 72 and the upper electrode 70 .

Also, the bottom region 36 is connected to the main body region 32b via a connection region 38. As shown in FIG. That is, the bottom region 36 is connected to the upper electrode 70 via the connection region 38, the main body region 32b, and the body contact region 32a. Therefore, the bottom region 36 is maintained at substantially the same potential as the upper electrode 70 when the switching element 10 is turned off. Therefore, when the switching element 10 is turned off, a high reverse voltage is also applied to the pn junction at the interface between the bottom region 36 and the drift region 33 . As a result, a depletion layer extends from the bottom region 36 to the surrounding drift region 33 . The depletion layer extending from the bottom region 36 suppresses electric field concentration near the lower ends of the trenches 22a, 22b. Therefore, switching element 10 has a high breakdown voltage.

When the switching element 10 is turned off and the potential of the lower electrode 72 rises, holes flow from the bottom region 36 to the main body region 32b. If the resistance of the path through which holes flow from the bottom region 36 to the main body region 32b (hereinafter referred to as a connection path) is high, the holes cannot be sufficiently discharged from the bottom region 36 to the main body region 32b. As the potential rises, the potential of the bottom region 36 rises. In this case, it is difficult for the depletion layer to spread around the bottom region 36, and electric field concentration tends to occur near the lower ends of the trenches 22a and 22b. On the other hand, in the switching element 10 of the embodiment, the connection path that connects the bottom region 36 and the main body region 32b is composed of the connection region 38 and the low resistance film 40 . Since the electrical resistance of the low resistance film 40 is extremely low, the electrical resistance of the connection path is extremely low. Therefore, when the switching element 10 is turned off, the potential of the bottom region 36 is maintained at substantially the same potential as that of the upper electrode 70, thereby preventing the potential of the bottom region 36 from rising. As a result, the depletion layer quickly spreads around the bottom region 36, suppressing electric field concentration near the lower ends of the trenches 22a and 22b.

Moreover, as described above, if the connection path connecting the bottom region 36 and the main body region 32b includes the low-resistance film 40, the electrical resistance of the connection path can be made extremely low. Therefore, even if the area in which the connection path is provided is reduced, the electrical resistance of the connection path can be made sufficiently low, and an increase in the potential of the bottom area 36 can be prevented. The area in which the connection path is provided is an inactive area, in which no current flows when the switching element 10 is turned on. By reducing the non-active region, the active region can be increased and the current can be passed through the semiconductor substrate 12 at high density. As a result, the size of the switching element 10 can be reduced. Thus, by providing the low-resistance film 40 in the connection path, it is possible to reduce the size of the switching element 10 by reducing the non-active region.

Note that in FIG. 3, the low resistance film 40 extends from the depth of the source region 30 to the depth of the bottom region 36 . However, the low resistance film 40 only needs to extend at least from the depth of the main body region 32 b to the depth of the bottom region 36 . Also, in FIG. 3, the low resistance film 40 is arranged so as to be in contact with the side surface of the trench 22b, but as shown in FIG. 40 may be provided. In FIG. 3, the low resistance film 40 is arranged only near the side surfaces of the trench 22b, but as shown in FIG. It may have a contact portion. With this configuration, the bottom region 36 can be connected to the upper electrode 70 with a lower resistance. In FIG. 3, the low resistance film 40 was not provided at the position in contact with the bottom surface of the trench 22b, but as shown in FIG. good. Further, as shown in FIG. 7, the low resistance film 40 may have a portion extending along the upper surface 12a of the semiconductor substrate 12 and a portion in contact with the bottom surface of the trench 22b. In FIG. 2, the low resistance film 40 is not provided under the trench 22a, but the low resistance film 40 may extend under the trench 22a as shown in FIG. In FIG. 8, the low resistance film 40 is in contact with the bottom surface of the trench 22a and the bottom region 36 at the bottom of the trench 22a. With this configuration, the bottom region 36 below the trench 22a can be connected to the main body region 32b with a lower resistance.

Moreover, in the above-described embodiment, the low resistance film 40 is made of metal (eg, Al, Ti, W, Ni), but the low resistance film 40 may be made of polysilicon or the like. Alternatively, as shown in FIG. 9, the low resistance film 40 may be composed of a metal layer 40a and a silicide layer 40b.

Although the embodiments have been described in detail above, they are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above. The technical elements described in this specification or drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the techniques exemplified in this specification or drawings simultaneously achieve a plurality of purposes, and achieving one of them has technical utility in itself.

10: switching element 12: semiconductor substrate 22: lattice trench 22a: trench 22b: trench 24: gate insulating film 26: gate electrode 28: interlayer insulating film 30: source region 32: body region 32a: body contact region 32b: main body region 33: drift region 34: drain region 36: bottom region 38: connection region 40: low resistance film 70: upper electrode 72: lower electrode

Claims (7)

A switching element,
a semiconductor substrate having a trench on its top surface;
a gate insulating film covering the inner surface of the trench;
a gate electrode disposed in the trench and insulated from the semiconductor substrate by the gate insulating film;
low resistance film,
and
The semiconductor substrate is
an n-type source region in contact with the gate insulating film;
a p-type body region in contact with the gate insulating film below the source region;
a p-type bottom region located below the bottom surface of the trench;
an n-type drift region;
a p-type connection region;
and
the semiconductor substrate having an active area and a non-active area;
the drift region is in contact with the gate insulating film below the body region in the active region and in contact with the bottom region in the active region;
The low-resistance film is made of metal or polysilicon, has a lower electrical resistance than the connection region, is insulated from the gate electrode, and extends along the side of the trench within the non-active region. extending from the depth of the body region to the depth of the bottom region along
the connection region extends in contact with the low resistance film within the non-active region and connects the body region and the bottom region;
switching element. 2. The switching element according to claim 1, wherein said low resistance film is in contact with said gate insulating film on side surfaces of said trench within said non-active region. 2. The switching element according to claim 1, wherein said low resistance film is located within said non-active region at a position away from the side surfaces of said trench. further comprising an upper electrode covering the upper surface of the semiconductor substrate;
wherein the low-resistance film has a portion extending along the upper surface of the semiconductor substrate within the non-active region and in contact with the upper electrode;
A switching element according to any one of claims 1 to 3. The low-resistance film is disposed in the non-active region, extends along the bottom surface of the trench, contacts the gate insulating film at the bottom surface of the trench, and has a portion contacting the bottom region from above,
A switching element according to any one of claims 1 to 4. The low-resistance film is disposed in the active region, extends along the bottom surface of the trench, contacts the gate insulating film at the bottom surface of the trench, and has a portion contacting the bottom region from above,
A switching element according to any one of claims 1 to 5. the low-resistance film has a metal layer in contact with the gate insulating film on the side surface of the trench and a silicide layer in contact with the metal layer from a side opposite to the side of the gate insulating film;
the connection region is in contact with the silicide layer;
7. A switching element according to any one of claims 1, 2, 4, 5 and 6.

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