JP2020087179A - Controller and controller control method - Google Patents

Abstract

To realize a technique that can efficiently share necessary data between multiplexed CPU modules.SOLUTION: A control system CPU module (100A) includes a first arithmetic unit (111A) that performs arithmetic processing based on a user program, and a first memory (130A) in which an arithmetic result is written. A standby system CPU module (100B) includes a second arithmetic unit (111B) that performs arithmetic processing based on a user program when an abnormality occurs in the control system CPU module (100A), and a second memory (130B). The control system CPU module (100A) further includes a first memory processing unit (121) configured to output an instruction to write the calculation result to the first memory (130A) and transfer it to the second memory (130B) of the standby system CPU module (100B).SELECTED DRAWING: Figure 1

Description

The present invention relates to a controller having CPU modules to be multiplexed, and a controller control method.

Conventionally, a PLC (Programmable Logic Controller) is known to have a configuration in which CPU modules are multiplexed for the purpose of improving system safety and reliability. In these multiplexed CPU modules, any one CPU module operates as a control system CPU module that executes arithmetic processing, and another CPU module operates as a standby system CPU module.

When an abnormality occurs in the control system CPU module, the standby system CPU module replaces the control system CPU module in which the abnormality has occurred, executes the arithmetic processing, and continues the control operation by the PLC. The control system CPU module and the standby system CPU module use a part of the data used in the control system CPU module so that the system can continue to operate when an abnormality occurs in the control system CPU module. Transfer to and share.

Generally, the user determines which data is shared between the control system CPU module and the standby system CPU module, and the user manually selects the data. In a program that uses a large number of variables, an erroneous operation may occur when the CPU module that performs the control operation is switched due to a mistake in setting a shared variable.

Therefore, a technique for automatically selecting data to be transferred from the control CPU module to the standby CPU module in order to suppress an abnormal operation at the time of switching operation modules due to an error in setting a shared variable and reduce a user's burden of setting a shared variable. Has been proposed (for example, see Patent Document 1).

JP, 2013-23531, A

In the conventional technique as described above, the compiler refers to the input/output data to confirm what purpose each memory is used in the program, and sets the data of the memory determined to be tracking-necessary as the initial value data. And the input/output data are extracted and transferred from the control system CPU module to the standby system CPU module. As described above, in the configuration in which each memory is scanned to extract data after the program is executed and the extracted data is transferred from the control system CPU module to the standby system CPU module, the memory scan time becomes long. Therefore, there is a problem that the execution of the program is delayed (the execution cycle becomes long).

One aspect of the present invention has been made in view of the above circumstances, and an object of the present invention is to realize a technique capable of appropriately and efficiently sharing data between multiplexed CPU modules.

In order to solve the above problems, a controller according to an aspect of the present invention is a controller in which CPU modules are multiplexed, and includes a control system CPU module and a standby system CPU module. The module includes a first arithmetic unit that performs arithmetic processing based on a user program, and a first memory in which the arithmetic result of the first arithmetic unit is written, and the standby CPU module has an abnormality in the control CPU module. And a second memory for performing a calculation process based on a user program when the occurrence of the error occurs, the control system CPU module further writes the calculation result received from the first calculation unit. Is output to the first memory and is transferred to the second memory of the standby CPU module.

In a controller in which CPU modules are multiplexed, the user does not need to set a shared variable between the control CPU module and the standby CPU module, which reduces the user's trouble and prevents a setting error. be able to. Further, since it is not necessary to scan the data and extract and transfer the variable to be shared at each timing of sharing the variable, the time required for the memory scan can be suppressed.

Therefore, it is possible to efficiently share necessary data among the CPU modules to be multiplexed. Further, when the CPU modules are switched, necessary data is not shared, and malfunctions due to the switching of the CPU modules can be suppressed and the CPU modules can be switched efficiently.

In the controller according to the aspect of the present invention, the first memory processing unit of the control system CPU module may be configured to send an input data write instruction received by the control system CPU module from an external I/O unit to the first memory. Output to the second memory of the standby CPU module.

According to the above configuration, the control system CPU module shares the input data received from the external I/O unit with the standby system CPU module at the same timing as writing to the first memory of the control system CPU module. be able to. The control system CPU module does not need to scan the first memory again in order to share the input data. Therefore, it is possible to efficiently share necessary data among the CPU modules to be multiplexed.

In the controller according to the aspect of the present invention, the control system CPU module may include a memory access controller, and the memory access controller may include the first memory processing unit.

According to the above configuration, the memory access controller distributes the output to the first memory and the transfer to the standby system CPU module, so that the first arithmetic unit does not wait for the write processing to perform the next arithmetic processing. Can be executed.

In the controller according to the aspect of the present invention, the first arithmetic unit and the first memory processing unit may be formed in one integrated circuit.

According to the above configuration, the first memory processing unit distributes the output to the first memory and the transfer to the standby CPU module, so that the first arithmetic unit does not wait for the writing process and then Arithmetic processing can be executed.

In the controller according to the aspect of the present invention, the standby CPU module includes a second memory processing unit, and the second memory processing unit receives the write instruction of the calculation result from the control CPU module. The write instruction may be output to the second memory.

According to the above configuration, since the second memory processing unit executes writing to the second memory, the first memory processing unit only needs to deliver the write instruction to the second memory processing unit, and It is not necessary to wait for the writing process of. Therefore, it is possible to efficiently share necessary data among the CPU modules to be multiplexed.

In the controller according to the aspect of the present invention, the second memory processing unit may issue a write instruction of a calculation result received from the second calculation unit when an abnormality occurs in the control system CPU module, to the second memory. May be output to.

According to the above configuration, when an abnormality occurs in the control system CPU module, the processing can be completed in the standby system CPU module, and the operation of the controller can be efficiently continued.

In the controller according to one aspect of the present invention, the control system CPU module includes a first arithmetic processing unit including the first arithmetic unit and a first register, and the standby CPU module includes the second arithmetic unit. And a second register including a second register, wherein the first memory processing unit issues a write instruction to the first register of the first calculation processing unit to the second CPU of the standby system CPU module. It may be transferred to the second register of the arithmetic processing unit.

According to the above configuration, the information written in the first register of the control CPU module is shared by the second register of the standby CPU module. As a result, the intermediate data stored in the register necessary for the arithmetic processing based on the user program can be shared with the standby CPU module. The standby CPU module can appropriately know the processing executed by the control CPU module. Therefore, when an abnormality occurs in the control system CPU module and the operation is switched to the standby system CPU module, the standby system CPU module can execute the next process from an appropriate position in the user program.

A controller according to an aspect of the present invention is a cable that connects the control system CPU module and the standby system CPU module to each other separately from a cable that transmits the input data from the external I/O unit. A cable for transmitting the instruction to write the calculation result may be provided.

According to the above configuration, the write instruction can be transmitted via a cable different from the cable that transmits the input data, and it is possible to suppress the occurrence of delay in data transmission (that is, sharing).

In order to solve the above problems, a control method according to an aspect of the present invention is a control method for a controller in which a control system CPU module and a standby system CPU module are multiplexed, and A memory for outputting an operation step of performing an operation process based on a user program and an instruction for writing an operation result of the operation process to a first memory of the control system CPU module and transferring the instruction to a second memory of the standby system CPU module. And a processing step.

In a controller in which CPU modules are multiplexed, the user does not need to set a shared variable between the control CPU module and the standby CPU module, which reduces the user's trouble and prevents a setting error. be able to. Further, since it is not necessary to scan the data and extract and transfer the variable to be shared at each timing of sharing the variable, the time required for the memory scan can be suppressed.

Therefore, it is possible to efficiently share necessary data among the CPU modules to be multiplexed. Further, when the CPU modules are switched, necessary data is not shared, and malfunctions due to the switching of the CPU modules can be suppressed and the CPU modules can be switched efficiently.

According to one aspect of the present invention, there is an effect that data can be appropriately and efficiently shared between multiplexed CPU modules.

It is a block diagram which shows the principal part structure of PLC which concerns on Embodiment 1 of this invention. FIG. 2 is a block diagram showing a main configuration of the memory access controller shown in FIG. 1. It is a figure explaining the specific example of the flow of the data transfer process between the two CPU modules shown in FIG. It is a figure explaining the specific example of the flow of the operation switching process between the two CPU modules shown in FIG. FIG. 6 is a block diagram showing a main configuration of a PLC according to a second embodiment.

Hereinafter, an embodiment according to one aspect of the present invention (hereinafter, also referred to as “this embodiment”) will be described with reference to the drawings.

§1 Application Example An example of a situation in which the present invention is applied will be described with reference to FIG. FIG. 1 is a block diagram showing a main configuration of a PLC (controller) 10 according to this embodiment. The PLC 10 includes a plurality of CPU modules 100A and 100B that are multiplexed. The PLC 10 is connected to a plurality of host devices and a plurality of I/O units (input/output units) to be controlled. The I/O unit is a sensor that collects, for example, a control unit of a drive device such as a machine tool and a servo motor of a belt conveyor, or sensor data related to the operating state of the drive device, and generates data indicating the operating state It is a unit. The host device is, for example, a user PC (personal computer) or a server that edits a user program.

In the PLC 10, any one of the plurality of CPU modules 100A and 100B functions as a control system CPU module. In the control system CPU module, the PLC 10 executes a user program corresponding to the I/O unit to be controlled based on the input data from the I/O unit, thereby generating an operation control instruction to the drive device.

In each of the plurality of CPU modules 100A and 100B, a plurality of programs for controlling each of the plurality of driving devices are written in the program memories 140A and 140B in advance. Further, the initial setting data used in these programs are written in advance in the internal memories 130A and 130B.

In the PLC 10, in a normal state, the control system CPU module performs arithmetic processing based on the user program, and controls the operation of the drive device according to the arithmetic result. In the normal state, the standby CPU module does not perform arithmetic processing based on the user program.

In the PLC 10, when an abnormality occurs in the control system CPU module, the standby system CPU module, which is another CPU module to be multiplexed, replaces the control system CPU module and controls the operation of the drive device. Control operation continues. Data is shared between the control CPU module and the standby CPU module so that the CPU module that performs the control operation can be efficiently switched when an abnormality occurs in the control CPU module. Has been done.

The control CPU module outputs an instruction to write the input data from the I/O unit to the I/O memory (simply referred to as a memory) to the I/O memory of its own module and transfers it to the standby CPU module. Further, the control CPU module outputs an instruction to write the calculation result of the arithmetic processing to the I/O memory to the memory of its own module and transfers it to the standby CPU module.

In this way, in the control system CPU module and the standby system CPU module, the calculation result (and the input data) are simultaneously written in the respective memories. As a result, it is not necessary to scan the memory to extract the data to be transferred, and the necessary data can be shared efficiently. Moreover, since the calculation result can be always shared between the control system CPU module and the standby system CPU module, and the CPU module can be efficiently switched, the PLC 10 continues the control operation without delay. be able to.

§2 Configuration example [Embodiment 1]
The configuration of the PLC 10 according to the first embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2. FIG. 1 is a block diagram showing a main configuration of the PLC 10.

As shown in FIG. 1, the PLC 10 includes a first CPU module 100A and a second CPU module 100B. The first CPU module 100A and the second CPU module 100B are multiplexed in the PLC 10. Although FIG. 1 shows an example in which the PLC 10 includes the first CPU module 100A and the second CPU module 100B that are duplicated, the present invention is not limited to this, and three or more multiple CPUs are provided. It may be configured. Each of the first CPU module 100A and the second CPU module 100B is configured to be able to integrally control the entire PLC 10.

The first CPU module 100A functions as a control system module that acquires input data from the I/O unit in a normal state and executes arithmetic processing based on a user program. The first CPU module 100A is also referred to as a control system CPU module. The second CPU module 100B functions as a standby system module that executes a control operation in place of the first CPU module 100A when an abnormality occurs in the first CPU module 100A. The second CPU module 100B is also referred to as a standby CPU module. While the first CPU module 100A is operating normally, the second CPU module 100B does not execute the arithmetic processing based on the user program necessary for the control operation.

The first CPU module 100A and the second CPU module 100B have the same configuration as each other, and each include an arithmetic processing unit 110, a memory access controller 120, and an I/O memory 130. The first CPU module 100A and the second CPU module 100B include a program memory 140 and an MPU (Micro Processor Unit) 150.

The arithmetic processing unit 110 is a processor formed of one integrated circuit (for example, ASIC (Application Specific Integrated Circuit) or FPGA (Field-Programmable Gate Array)). The memory access controller 120 is formed by one integrated circuit. The arithmetic processing unit 110 and the memory access controller 120 may each include a plurality of integrated circuits.

The first CPU module 100A and the second CPU module 100B are each connected to a cable that transmits input data from an external I/O unit, such as an EtherNet (registered trademark) cable. Further, the first CPU module 100A and the second CPU module 100B are connected to each other by a transmission cable 50, separately from a cable for transmitting input data from an external I/O unit. The first CPU module 100A and the second CPU module 100B share the input data from the external I/O unit and the calculation result by the calculation processing unit 110 via the transmission cable 50.

The MPU 150 controls communication with a host device. The MPU 150 acquires the user program from the server, for example, and stores the user program in the program memory 140.

The program memory 140 stores a user program that is a control program for controlling the drive device to be controlled. The user program is, for example, a control program written in a ladder language or the like.

The arithmetic processing unit of the first CPU module 100A is referred to as a first arithmetic processing unit 110A, and the arithmetic processing unit of the second CPU module 110B is referred to as a second arithmetic processing unit 110B. Further, the memory access controller of the first CPU module 100A is referred to as a first memory access controller 120A, and the memory access controller of the second CPU module 110B is referred to as a second memory access controller 120B. Further, the I/O memory of the first CPU module 100A is referred to as the first memory 130A, and the I/O memory of the second CPU module 110B is referred to as the second memory 130B. Further, the program memory of the first CPU module 100A is referred to as a first program memory 140A, and the program memory of the second CPU module 110B is referred to as a second program memory 140B. The MPU of the first CPU module 100A is referred to as the first MPU 150A, and the MPU of the second CPU module 110B is referred to as the second MPU 150B.

The first CPU module 100A periodically receives input data from the I/O unit. The input data includes, for example, data indicating the driving state of the driving device and data indicating the measurement value measured by the sensor. The first CPU module 100A stores the input data from the I/O unit in the first memory 130A as it is through the first arithmetic processing unit 110A. Specifically, the first CPU module 100A transfers the input data from the I/O unit to the first arithmetic processing unit 110A. The first arithmetic processing unit 110A outputs the input data write instruction to the first memory access controller 120A in order to write the received input data in the first memory 130A. The first memory access controller 120A outputs the instruction to write the input data output from the first arithmetic processing unit 110A to the first memory 130A.

The first CPU module 100A also stores the calculation result by the first calculation processing unit 110A in the first memory 130A. Specifically, the first CPU module 100A outputs a calculation result write instruction to the first memory access controller 120A in order to write the calculation result of the first calculation unit 111A of the first calculation processing unit 110A to the first memory 130A. To do. The first memory access controller 120A outputs, to the first memory 130A, the instruction to write the operation result output by the first operation processing unit 110A.

Further, the first CPU module 100A transfers the input data from the I/O unit and the calculation result obtained by the first calculation processing section 110A to the second CPU module 100B at the timings of writing them in the first memory 130A.

The first arithmetic processing unit 110A includes a first arithmetic unit 111A and a first register 112A. Similarly, the second arithmetic processing unit 110B includes a second arithmetic unit 111B and a second register 112B.

The first calculation unit 111A reads the user program stored in the first program memory 140A and the input data from the I/O unit stored in the first memory 130A, and calculates based on the user program. Perform processing. The contents of the processing executed by the first arithmetic processing unit 110A (variables used inside the user program) are written in the first register 112A.

The second computing unit 111B is configured to input the user program stored in the second program memory 140B and the input data from the I/O unit stored in the second memory 130B when an abnormality occurs in the first CPU module 100A. And are read, and arithmetic processing based on the user program is performed. The contents of the processing executed by the second arithmetic processing unit 110B (variables used inside the user program) are written in the second register 112B.

FIG. 2 is a block diagram showing a main configuration of the memory access controllers 120A and 120B shown in FIG. Each of the memory access controllers 120A and 120B includes a distribution circuit unit 121, a data buffer 122, and a data transceiver and receiver IC 123. The distribution circuit unit 121 of the first memory access controller 120A is also referred to as the first memory processing unit 121A. The distribution circuit unit 121 of the second memory access controller 120B is also referred to as a second memory processing unit 121B.

The first memory access controller 120A acquires a write instruction for writing the calculation result in the first memory from the first calculation unit 111A. The instruction to write the operation result includes the operation result and information on the address (logical address or physical address) in which the operation result is to be stored. The distribution circuit unit 121 of the first memory access controller 120A outputs the instruction to write the calculation result received from the first calculation unit 111A to the first memory 130A. Further, the distribution circuit unit 121 of the first memory access controller 120A transfers the received write instruction of the calculation result to the second memory 130B of the second CPU module 100B via the data buffer 122 and the data transceiver and receiver IC 123. .. In this way, the distribution circuit unit 121 distributes one write instruction to the first memory 130A and the second memory 130B.

Specifically, the distribution circuit unit 121 of the first memory access controller 120A outputs the write instruction of the calculation result from the first calculation unit 111A to the data buffer 122 of the first memory access controller 120A. The data transceiver and receiver IC 123 controls communication between the CPU modules 100A and 100B. The data transceiver and receiver IC 123 of the first memory access controller 120A transmits the write instruction of the calculation result stored in the data buffer 122 to the second memory access controller 120B of the second CPU module 110B via the transmission cable 50.

Further, the distribution circuit unit 121 of the first memory access controller 120A sends a write instruction from the first arithmetic processing unit 110A, which writes the input data received from the external I/O unit to the first memory 130A, to the first memory 130A. The data is output and transferred to the second memory 130B of the second CPU module 110B. The instruction to write the input data includes the input data and information on the address at which the input data should be stored. The distribution circuit unit 121 of the first memory access controller 120A transmits the write instruction of the input data received from the first arithmetic unit 111A via the data buffer 122, the data transceiver and receiver IC 123, and the transmission cable 50 to the second CPU module 100B. To the second memory 130B. The input data itself from the I/O unit is transferred from the first CPU module 100A to the second CPU module 100B via a cable, which is different from the transmission cable 50, for transmitting the input data from the I/O unit. May be done. Alternatively, the input data from the I/O unit may be input from the I/O unit to the second CPU module 100B.

Further, the distribution circuit unit 121 of the first memory access controller 120A acquires a write instruction to the register 112A of the first arithmetic processing unit 110A from the first arithmetic processing unit 110A, and the write instruction is stored in the second CPU module 100B. 2 Transfer to the register 112B of the arithmetic processing unit 110B. The write instruction to the register includes the content of the process executed by the first arithmetic processing unit 110A (variable used inside the user program) and the information of the address on the register in which the data is to be stored. The distribution circuit unit 121 of the first memory access controller 120A transmits the write instruction to the register received from the first arithmetic processing unit 110A via the data buffer 122, the data transceiver and receiver IC 123, and the transmission cable 50 to the second CPU module. Transfer to the register 112B of 100B.

The second CPU module 110B receives, via the second memory access controller 120B, the input data write instruction, the calculation result write instruction, and the register write instruction transmitted via the transmission cable 50.

The second memory access controller 120B receives the write instruction from the first CPU module 100B via the data transceiver and receiver IC 123 of the second memory access controller 120B. The data transceiver and receiver IC 123 of the second memory access controller 120B outputs the received write instruction to the data buffer 122 of the second memory access controller 120B. The distribution circuit (second memory processing unit) 121 of the second memory access controller 120B issues a write instruction if the write instruction stored in the data buffer 122 is an input data write instruction or an operation result write instruction. , To the second memory 130B. If the write instruction stored in the data buffer 122 is the write instruction to the register, the distribution circuit unit 121 of the second memory access controller 120B outputs the write instruction to the register 112B of the second arithmetic processing unit 110B. ..

The second CPU module 100B receives information indicating that an abnormality has occurred in the first CPU module 100A from the first CPU module 100A via the second memory access controller 120B. When the second CPU module 100B receives the information indicating that the abnormality has occurred in the first CPU module 100A, the second arithmetic processing unit 110B starts executing the arithmetic processing based on the user program. The second arithmetic processing unit 110B performs arithmetic processing based on the user program by the function of the second arithmetic unit 111B and outputs an instruction to write the arithmetic result of the second arithmetic unit 111B to the memory to the second memory access controller 120B. .. When the second memory access controller 120B receives the instruction to write the calculation result by the second calculation unit 111B into the memory, the second memory access controller 120B performs the calculation received from the second calculation processing unit 110B by the function of the distribution circuit unit 121 of the second memory access controller 120B. The instruction to write the result is output to the second memory 130B.

When an abnormality occurs in the first CPU module 100A, the distribution circuit unit 121 of the second memory access controller 120B outputs the operation result write instruction received from the second operation processing unit 110B to the second memory 130B.

[Flow of data transfer processing between CPU modules]
FIG. 3 is a flowchart showing a flow of data transfer processing between the first CPU module 100A and the second CPU module 100B.

The first CPU module 100A and the second CPU module 100B respectively initialize the I/O memories 130A and 130B after turning on the power of the PLC 10 (steps S1 and S11). In the initial setting, initial values of parameters used in each user program are registered in the I/O memories 130A and 130B.

[Processing cycle of the first CPU module 100A]
Subsequently, the first CPU module 100A repeatedly executes the state check process, the program execution process, the memory refresh, and the event process in this order as a set. This set of state check process, program execution process, memory refresh, and event process is called "1 cycle".

In the status check process, the first CPU module 100A confirms whether or not each hardware and software included in the module itself operate normally (step S2).

Subsequently, in the program execution process, the first CPU module 100A uses the function of the first arithmetic unit 111A of the first arithmetic processing unit 110A to execute a predetermined user program and the user program stored in the first memory 130A. The parameters used internally are read and arithmetic processing based on the user program is performed. The first operation unit 111A outputs a write instruction for writing the operation result to the I/O memory to the first memory access controller 120A. The first memory access controller 120A outputs a calculation result write instruction received from the first calculation unit 111A to the first memory 130A by the function of the distribution circuit unit 121, and writes the calculation result to the first memory 130A.

Further, the distribution circuit unit 121 outputs a write instruction of the calculation result (O data) received from the first calculation unit 111A to the first memory 130A, and also outputs the write instruction (including O data) to the data buffer 122. , And via the data transceiver and receiver IC 123 to the second memory access controller 120B of the second CPU module 110A (step S3).

Subsequently, the first CPU module 100A refreshes the parameters stored in the first memory 130A using the input data (I data) received from the external I/O unit. The distribution circuit unit 121 of the first CPU module 100A outputs a write instruction to write the input data received from the external I/O unit to the first memory 130A to the first memory 130A, and also outputs the write instruction (including the I data). ) Is transferred to the second memory access controller 120B of the second CPU module 110A via the data buffer 122 and the data transceiver and receiver IC 123 (step S4).

The first CPU module 100A performs an event process for communicating with a higher-level device (step S5). For example, in order to record or analyze the input data received from the external I/O unit, the specific input data is transmitted to the server which is the host device. When the first CPU module 100A finishes the process of one cycle of step S2 to step S5, it starts the next cycle. Further, although not shown, the first arithmetic processing unit 110A outputs the content of the processing to the first register 112A, for example, during the execution processing of the user program, and at the same time, through the second memory access controller 120B. The data is transferred to the second register 112B of the 2CPU module 100B.

[Processing of Second CPU Module 100B]
Next, the processing of the second CPU module 100B during one cycle of processing in the first CPU module 100A will be described.

After the initial setting, the second CPU module 100B performs a state check process to confirm whether or not each hardware and software included in the second CPU module 100B operates normally (step S12).

The second CPU module 100B waits until it receives the data transferred from the first CPU module 100A. While the first CPU module 100A is operating normally, the second arithmetic unit 111B stands by without executing the user program. The second CPU module 100B receives a write instruction for writing the calculation result in the memory from the first CPU module 100A by the function of the second memory access controller 120B. The second memory access controller 120B outputs a calculation result write instruction to the second memory 130B by the function of the distribution circuit unit 121 to write the calculation result by the first calculation unit 111A of the first CPU module 100A, and outputs the calculation result to the second memory 130B. Write (step S13). When the distribution circuit unit 121 of the second memory access controller 120B receives the write instruction to the register, it transfers the write instruction to the register to the second register 112B of the second arithmetic processing unit 110B. As a result, the data written in the first register 112A is also written in the second register 112B.

Further, the second CPU module 100B waits until it receives the data transferred from the first CPU module 100A. By the function of the second memory access controller 120B, the second CPU module 100B receives a write instruction from the first CPU module 100A to write the input data received by the first CPU module 100A from the external I/O unit into the memory. The second memory access controller 120B outputs an input data write instruction from an external I/O unit to the second memory 130B by the function of the distribution circuit unit 121, and writes the input data to the second memory 130B (step S14).

The second CPU module 100B executes the set of processes of steps S12 to S14 as one cycle of processing, and when the one cycle is completed, starts the next cycle.

As described above, in the PLC 10, in the normal state where the first CPU module 100A is operating normally, the calculation result and the external I/O between the first CPU module 100A and the second CPU module 100B, which are multiplexed, are obtained. The input data received from the unit can be written in the respective memories 130A and 130B at the same timing. The distribution circuit unit 121 of the first CPU module 100A transfers the write instruction to the first memory 130A to the second memory 130B of the second CPU module 100B as it is in addition to the first memory 130A. Therefore, since the data of the first memory 130A of the first CPU module 100A is shared by the second memory 130B of the second CPU module 100B, it is not necessary to scan the first memory 130A. Therefore, the data can be appropriately and efficiently shared between the CPU modules to be multiplexed. As a result, when an abnormality occurs in the control system CPU module, the control function can be efficiently switched to the standby system CPU module and the operation can be continued.

[Process Flow When Abnormality Occurs in First CPU Module 100A]
FIG. 4 is a flowchart showing the flow of processing by the first CPU module 100A and the second CPU module 100B when an abnormality occurs in the first CPU module 100A.

The first CPU module 100A performs a state check process (step S2) after performing an initial setting process (step S1). When the first CPU module 100A detects an abnormality as a result of the state check processing (step S23), the first CPU module 100A transmits a notification that the abnormality has occurred to the second CPU module 100B (step S24). The first CPU module 100A returns to the state check process without performing the program execution process.

The second CPU module 100B receives the notification indicating that the abnormality has occurred in the first CPU module 100A via the second memory access controller 120B (step S31), and executes the program execution process in place of the first CPU module 100A. The function of the second arithmetic unit 111B performs arithmetic processing based on a user program.

In the program execution process, the second CPU module 100B reads a predetermined user program and a predetermined parameter stored in the second memory 130B by the function of the second calculation unit 111B of the second calculation processing unit 110B, Performs arithmetic processing based on a user program. The second arithmetic unit 111B outputs a write instruction for writing the arithmetic result to the memory to the second memory access controller 120B. The second memory access controller 120B outputs a calculation result write instruction received from the second calculation unit 111B to the second memory 130B by the function of the distribution circuit unit 121, and writes the calculation result to the second memory 130B (step S32).

Subsequently, the second CPU module 100B refreshes the parameters stored in the second memory 130B using the input data received from the external I/O unit. The distribution circuit unit 121 of the second CPU module 100B outputs, to the second memory 130B, a write instruction for writing the input data received from the external I/O unit into the second memory 130B (step S33).

The second CPU module 100B performs an event process for controlling the drive device to be controlled according to the result of the calculation process based on the user program by the second calculation unit 111B (step S34). When the second CPU module 100B finishes the processing of step S12 and steps S33 to S34 in one cycle, it repeats the processing of step S12 and steps S33 to S34, which is the next cycle.

When the first CPU module 100A recovers from the abnormal state while the second CPU module 100B is performing the control operation instead of the first CPU module 100A, the second CPU module 100B continues the control operation. May be.

Further, when the first CPU module 100A recovers from the abnormal state while the second CPU module 100B is performing the control operation in place of the first CPU module 100A, the second CPU module 100B displays data (calculation result and input Transfer of data etc.) to the first CPU module 100A may be started. After the sharing of the data is completed, the first CPU module 100A and the second CPU module 100B switch the control operation to the first CPU module 100A, and start the data transfer from the first CPU module 100A to the second CPU module 100B. You may.

As described above, the first CPU module 100A receives from the external I/O unit as the calculation result by the first arithmetic processing unit 110A of the first CPU module 100A, which is the control system CPU module that controls the operation of the drive device in the normal state. The input data and the information written in the first register 112A of the first arithmetic processing unit 110A are all stored in the first CPU module 100A at the same timing, and the second CPU module 100B, which is a standby CPU module, is stored. Shared with. As a result, when an abnormality occurs in the first CPU module 100A, the control operation can be switched to the second CPU module 100B promptly and without malfunction, and the operation of the PLC 10 can be continued.

[Embodiment 2]
The second embodiment of the present invention will be described below. For convenience of description, members having the same functions as those described in the first embodiment will be designated by the same reference numerals, and the description thereof will not be repeated.

In the first embodiment, the first CPU module 100A and the second CPU module 100B include the memory access controllers 120A and 120B including the distribution circuit unit 121, in addition to the arithmetic processing units 110A and 110B. The distribution circuit unit 121 is not limited to this, and may be formed in the circuit of the arithmetic processing unit.

FIG. 5 is a diagram showing a main configuration of the PLC 10 according to the second embodiment. The PLC 10 includes a first CPU module 200A and a second CPU module 200B. The first CPU module 200A is a module that mainly controls the drive device to be controlled in the PLC 10, and is referred to as a control system CPU module as in the first embodiment. The second CPU module 200B is a module that controls the drive device to be controlled in place of the first CPU module 200A when an abnormality occurs in the first CPU module 200A, and is called a standby CPU module as in the first embodiment. ..

The first CPU module 200A includes a first arithmetic processing unit 210A. The second CPU module 200B includes a second arithmetic processing section 210B. Each of the first arithmetic processing unit 210A and the second arithmetic processing unit 210B is configured to be able to integrally control the entire PLC 10.

The first arithmetic processing unit 210A includes a first arithmetic unit 211A, a first distribution circuit unit (first memory processing unit) 212A, and a first data buffer 213A. The second arithmetic processing unit 210B includes a second arithmetic unit 211B, a second distribution circuit unit (second memory processing unit) 212B, and a second data buffer 213B. The first calculation unit 211A, the first distribution circuit unit 212A, and the first data buffer 213A are formed in one integrated circuit. Similarly, the second calculation unit 211B, the second distribution circuit unit 212B, and the second data buffer 213B are formed in one integrated circuit.

Although not shown, each of the first arithmetic processing unit 210A and the second arithmetic processing unit 210B includes a register in which the content of the executed process and the information indicating that the process is completed are written. There is.

The first distribution circuit unit 212A and the second distribution circuit unit 212B each have the same function as the distribution circuit unit 212 described in the first embodiment. The first data buffer 213A and the second data buffer 213B each have the same function as the data buffer 213 described in the first embodiment.

The first CPU module 200A also includes a first driver IC 225A that connects the transmission cable 50 and the first arithmetic processing unit 210A. The second CPU module 200B includes a second driver IC 225B that connects the transmission cable 50 and the second arithmetic processing unit 210B. The first and second driver ICs 225A and 225B convert the parallel signals output from the first and second arithmetic processing units 210A and 210B into serial signals, transfer the serial signals to the other CPU module through the transmission cable, and transmit the transmission cable. The serial signal received via 50 is converted into a parallel signal and provided to the CPU module.

The first arithmetic unit 211A performs arithmetic processing based on a user program. The calculation result by the first calculation unit 211A and the write instruction for writing the calculation result in the first memory 130A are passed to the first distribution circuit unit 212A. The first distribution circuit unit 212A outputs the write instruction of the calculation result received from the first calculation unit 211A to the first memory 130A and transfers it to the second memory 130B of the second CPU module 200B. Further, the first distribution circuit unit 212A outputs an instruction to write the input data received from the external I/O unit to the memory to the first memory 130A and transfers it to the second memory 130B of the second CPU module 200B. .. Further, the first distribution circuit unit 212A transfers the write instruction to the register of the first arithmetic processing unit 210A to the register of the second arithmetic processing unit 210B of the second CPU module 200B.

The second distribution circuit unit 212B outputs the instruction to write the calculation result received from the first CPU module 100A to the second memory 130B. Further, the second distribution circuit unit 212B outputs the input data write instruction received from the first CPU module 100A to the second memory 130B. Further, the second distribution circuit unit 212B outputs the write instruction to the register received from the first CPU module 100A to the register of the second arithmetic processing unit 210B.

[Example of software implementation]
Each control block of the first CPU module 100A and the second CPU module 100B (in particular, the arithmetic processing units 110A and 110B), and each control block of the first CPU module 200A and the second CPU module 200B (in particular, the arithmetic processing unit 210A, 210B) may be realized by a logic circuit (hardware) formed in an integrated circuit (IC chip) or the like, or may be realized by software using a CPU (Central Processing Unit).

In the latter case, each of the first CPU module 100A, the second CPU module 100B, the first CPU module 200A, and the second CPU module 200B executes a command of a program that is software that realizes each function, the above-mentioned program and various data. Is provided with a ROM (Read Only Memory) or a storage device (these are referred to as a "recording medium") recorded so that they can be read by a computer (or a CPU), a RAM (Random Access Memory) for expanding the above program, and the like. Then, the computer (or CPU) reads the program from the recording medium and executes the program to achieve the object of the present invention. As the recording medium, a “non-transitory tangible medium”, for example, a tape, a disk, a card, a semiconductor memory, a programmable logic circuit, or the like can be used. The program may be supplied to the computer via any transmission medium (communication network, broadcast wave, etc.) capable of transmitting the program. The present invention can also be realized in the form of a data signal embedded in a carrier wave, in which the above program is embodied by electronic transmission.

The present invention is not limited to the above-described embodiments, and various modifications can be made within the scope of the claims, and the embodiments obtained by appropriately combining the technical means disclosed in the different embodiments. Is also included in the technical scope of the present invention.

10 PLC (Controller)
50 Transmission cable 100A, 200A First CPU module (CPU module, control system CPU module)
100B, 200B Second CPU module (CPU module, standby CPU module)
111A, 211A 1st operation part 111B, 211B 2nd operation part 112A 1st register 112B 2nd register 120A 1st memory access controller 120B 2nd memory access controller 130A 1st memory 130B 2nd memory 121 Distribution circuit part (1st memory Processing unit, second memory processing unit)
212A First distribution circuit unit (first memory processing unit)
212B Second distribution circuit unit (second memory processing unit)

Claims (9)

A controller in which CPU modules are multiplexed,
A control system CPU module and a standby system CPU module,
The control system CPU module is
A first arithmetic unit that performs arithmetic processing based on a user program;
A first memory in which a calculation result by the first calculation unit is written,
The standby system CPU module is
A second arithmetic unit that performs arithmetic processing based on a user program when an abnormality occurs in the control system CPU module;
A second memory,
The control CPU module further outputs a write instruction of the calculation result received from the first calculation unit to the first memory and transfers the write instruction to the second memory of the standby CPU module. A controller that includes a processing unit. The first memory processing unit of the control system CPU module is
2. The control system CPU module outputs a write instruction of input data received from an external I/O unit to the first memory and transfers the write instruction to the second memory of the standby system CPU module. controller. The control system CPU module includes a memory access controller,
The controller according to claim 1, wherein the memory access controller includes the first memory processing unit. The controller according to claim 1, wherein the first arithmetic unit and the first memory processing unit are formed in one integrated circuit. The standby CPU module includes a second memory processing unit,
The controller according to claim 1, wherein the second memory processing unit receives the write instruction of the calculation result from the control system CPU module and outputs the write instruction to the second memory. .. The controller according to claim 5, wherein the second memory processing unit outputs to the second memory a write instruction of a calculation result received from the second calculation unit when an abnormality occurs in the control system CPU module. . The control system CPU module is
A first arithmetic processing unit including the first arithmetic unit and a first register;
The standby system CPU module is
A second arithmetic processing unit including the second arithmetic unit and a second register;
The first memory processing unit,
7. The write instruction to the first register of the first arithmetic processing unit is transferred to the second register of the second arithmetic processing unit of the standby system CPU module, according to claim 1. controller. A cable for connecting the control CPU module and the standby CPU module to each other, separately from the cable for transmitting the input data from the external I/O unit, and transmitting the instruction to write the calculation result. The controller of claim 2 comprising a cable. A control method for a controller in which a control CPU module and a standby CPU module are multiplexed,
An arithmetic step of performing arithmetic processing based on a user program in the control system CPU module;
A memory processing step of outputting a write instruction of the calculation result of the calculation processing to the first memory of the control system CPU module and transferring it to the second memory of the standby system CPU module;
Control method including.

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