JP2019068246A - Image pick-up device and imaging apparatus - Google Patents

Abstract

To provide an image pick-up device and an imaging apparatus capable of realizing power saving of the image pick-up device, while restraining reduction of frame rate due to increase in amount of data.SOLUTION: In an image pick-up device laminating a first substrate having a pixel array where multiple pixels performing photoelectric conversion are arranged in matrix, and a second substrate having a circuit array where multiple signal processing parts processing signals based on the photoelectric conversion are arranged in matrix, the pixel array includes a pixel block formed of multiple pixels, and connected with a pixel block corresponding to the signal processing part by multiple signal lines, and the signal processing part includes an adder circuit for adding the signal inputted from the multiple signal lines in the same period, and a conversion circuit performing analog-digital conversion of the signals added by the adder circuit.SELECTED DRAWING: Figure 9

Description

  The present invention relates to an imaging device and an imaging device.

  In recent years, in an imaging apparatus using an imaging element such as a CMOS sensor, multifunctionalization proceeds and not only generation of a captured image such as a still image or a moving image but also, for example, Patent Document 1 describes a signal obtained from an imaging element There is disclosed an imaging apparatus configured to be capable of using the pupil division type focus detection. In the configuration described in Patent Document 1, the amount of data increases, the read time becomes long, and a decrease in frame rate and an increase in power consumption occur. Further, in Patent Document 2, for the purpose of power saving of an analog-to-digital conversion circuit (denoted as an ADC circuit) in an imaging device, an operation state and a standby state are calculated according to the calculation result of the calculation unit for each pixel block. Control to switch is disclosed.

Japanese Patent Application Publication No. 2001-124984 JP, 2016-184843, A

  However, each pixel in Patent Document 2 is premised on a conventional configuration for acquiring a captured image, and it is not clear how to configure a pixel block. Furthermore, it is not clear how to configure a pixel block and control each of them in the case of a pixel configuration capable of acquiring focus detection other than generating a captured image as in Patent Document 1, etc. There is also the concern that it will increase.

  An object of the present invention is to provide an imaging element and an imaging apparatus that can realize power saving of an imaging element while suppressing a decrease in frame rate due to an increase in data amount.

  An imaging device according to the present invention includes a first substrate having a pixel array in which a plurality of pixels for performing photoelectric conversion are arranged in a matrix, and a plurality of signal processing units for processing signals based on the photoelectric conversion. An image pickup element in which a second substrate having a circuit array arranged in two layers is stacked, wherein the pixel array includes a pixel block formed by a plurality of pixels, and a plurality of pixel blocks corresponding to the signal processing unit It is connected by a signal line, and the signal processing unit includes an addition circuit that adds the signals input from the plurality of signal lines during a synchronization period, and a conversion circuit that analog-digital converts the signal added by the addition circuit. It features.

  According to the present invention, it is possible to provide an imaging device and an imaging device capable of realizing power saving of the imaging device while suppressing a decrease in frame rate due to an increase in data amount.

It is a block diagram showing a schematic structure of an imaging device by a 1st embodiment of the present invention. It is a block diagram showing a schematic structure of an image sensor by a 1st embodiment of the present invention. It is a top view which shows an example of the pixel array of the image pick-up element in the imaging device by the 1st Embodiment of this invention. It is a schematic diagram which shows the relationship between the light beam which comes out of the exit pupil of an imaging optical system, and a unit pixel. It is a graph which shows the example of the image signal waveform obtained from two sub pixels of an image pick-up element. It is the schematic which shows an example of a structure of the image pick-up element in the imaging device by the 1st Embodiment of this invention. It is a figure which shows an example of a circuit structure of the unit pixel of the image pick-up element in the imaging device by the 1st Embodiment of this invention. It is a figure showing an example of composition of a common row readout circuit of an image sensor in an imaging device by a 1st embodiment of the present invention. It is a timing chart which shows read-out operation of an image sensor in an imaging device by a 1st embodiment of the present invention. It is a timing chart which shows read-out operation of an image sensor in an imaging device by a 1st embodiment of the present invention. It is a figure which shows an example of a structure of the row common readout circuit of the image pick-up element in the imaging device by 2nd Embodiment of this invention. It is a timing chart which shows read-out operation of an image sensor in an imaging device by a 2nd embodiment of the present invention. 7 is an example of a pixel block according to a second embodiment of the present invention. It is a figure which shows an example of a structure of the row common readout circuit of the image pick-up element in the imaging device by 3rd Embodiment of this invention. It is a timing chart which shows read-out operation of an image sensor in an imaging device by a 3rd embodiment of the present invention. It is a timing chart which shows read-out operation of an image sensor in an imaging device by a 4th embodiment of the present invention. It is a timing chart which shows read-out operation of an image sensor in an imaging device by a 4th embodiment of the present invention. It is a timing chart which shows read-out operation of an image sensor in an imaging device by a 4th embodiment of the present invention. It is the schematic which shows an example of a structure of the image pick-up element in the imaging device by 5th Embodiment of this invention. It is the schematic which shows an example of wiring of the image pick-up element in the imaging device by 5th Embodiment of this invention. It is a figure which shows an example of a structure of the row common readout circuit of the image pick-up element in the imaging device by 5th Embodiment of this invention. It is a timing chart which shows read-out operation of an image sensor in an imaging device by a 6th embodiment of the present invention. It is an example of the pixel block by 7th Embodiment of this invention. It is the schematic which shows an example of a structure of the image pick-up element in the imaging device by 7th Embodiment of this invention. It is a block diagram of the correction parameter by 7th Embodiment of this invention. It is an internal block diagram of the ADC circuit by 8th Embodiment of this invention. It is a timing chart which shows the operation of the ADC circuit by an 8th embodiment of the present invention.

First Embodiment
An image sensor and an image pickup apparatus according to a first embodiment of the present invention will be described with reference to the drawings. In that case, what has the same function in all the figures attaches | subjects the same number, The description of the repetition is abbreviate | omitted.

  First, a schematic configuration of the imaging device 100 according to the present embodiment will be described with reference to FIG.

  As shown in FIG. 1, the imaging apparatus 100 according to the present embodiment includes a first lens group 101, an aperture 102, a second lens group 103, a third lens group 104, an optical low pass filter 105, and an imaging element 106. There is. The imaging apparatus 100 further includes an aperture actuator 117, a focus actuator 118, an aperture drive circuit 115, and a focus drive circuit 116. The imaging device 106 also includes a signal processing unit 107. The imaging apparatus 100 further includes a digital front end (DFE) 108 and a digital signal processor (DSP) 109. The imaging apparatus 100 further includes a display unit 111, a RAM 112, a timing generation circuit (TG) 113, a CPU 114, a ROM 119, and a recording medium 110.

  The first lens group 101, the diaphragm 102, the second lens group 103, the third lens group 104, and the optical low pass filter 105 are disposed along the optical axis in this order from the object side, and the imaging optical system Configured. The imaging optical system corresponds to an optical system for forming an optical image of a subject. The first lens group 101 is a lens group disposed at the foremost part (subject side) of the imaging optical system, and is held so as to be movable back and forth along the optical axis direction. The diaphragm 102 has a function of adjusting the light amount at the time of imaging by adjusting the aperture diameter. The second lens group 103 advances and retracts along the optical axis direction integrally with the diaphragm 102, and realizes a variable power operation (zoom function) by interlocking with the forward and backward operation of the first lens group 101. The third lens group 104 has a function of performing focusing by advancing and retracting along the optical axis direction. The optical low pass filter 105 is an optical element for reducing false color and moiré of a captured image.

  Although the present embodiment shows an example in which the lens apparatus having the imaging optical system is integrally formed with the main body of the imaging apparatus 100, the embodiment of the present invention is not limited to this. The present invention is also applicable to an imaging system constituted by an imaging apparatus main body and a lens apparatus (imaging optical system) detachably attached to the imaging apparatus main body.

  The diaphragm actuator 117 is provided with a mechanism for changing the aperture diameter of the diaphragm 102. The diaphragm drive circuit 115 is a drive circuit for controlling the aperture diameter of the diaphragm 102 by the diaphragm actuator 117 to adjust the imaging light quantity and performing exposure time control at the time of still image imaging. The focus actuator 118 has a mechanism for driving the third lens group 104 back and forth along the optical axis direction. The focus drive circuit 116 is a drive circuit for adjusting the focus position by driving the focus actuator 118.

  The imaging element 106 is a two-dimensional CMOS image sensor disposed on the imaging plane of the imaging optical system. The imaging device 106 according to the present embodiment is a stacked image sensor having a stacked structure unlike the normal image sensor as shown in FIG. More specifically, a first substrate 10 including a pixel unit 11 that performs photoelectric conversion on incident light, a signal processing unit 21 that processes a signal from the pixel unit 11, and a second substrate 20 that includes peripheral circuits and the like. And a stacked structure. In each substrate, a plurality of pixel units 11 and signal processing units 21 are periodically arranged in the row direction and the column direction. In the present embodiment, two substrates are stacked, but more substrates may be stacked. For example, by stacking a substrate having a memory such as a DRAM or a substrate including different signal processing circuits, the imaging element 106 can have a new function. The peripheral circuits included in the second substrate in this embodiment include a power supply circuit, a timing generation circuit, a register, an output amplifier, and the like.

  The imaging element 106 converts an object image (optical image) formed by the imaging optical system into an electrical signal by photoelectric conversion. In the present specification, the imaging element 106 may be referred to as an imaging unit. The TG 113 is for supplying a drive signal for driving the imaging device 106 and the like at a predetermined timing to the imaging device 106 and the like. The drive signal includes a clock signal and a synchronization signal for operating the imaging device 106, and further includes various setting parameters for mode change for selecting driving of the imaging device 106 and the like. The TG 113 may be provided as an internal TG inside the imaging device 106, or may be configured to generate a drive signal based on a synchronization signal supplied from the outside. Further, as modes for selecting driving of the imaging element 106, at least a still image mode, a moving image mode, and a live view mode are provided.

  The signal processing unit 107 is provided in the imaging device 106, and includes an ADC circuit that converts at least an analog image signal output from the pixel unit into a digital image signal.

  The DFE 108 has a function of executing predetermined arithmetic processing on the digital image signal output from the imaging element 106. The DSP 109 has a function of performing correction processing, development processing, and the like on the digital image signal output from the DFE 108. The DSP 109 also has a function of performing an AF (Auto Focus) operation for calculating an amount of focus shift from an image signal (digital image signal). The DFE 108 and the DSP 109 also include reconfigurable circuits such as FPGA circuits. By taking various circuit configurations by setting from the outside, complicated correction operation and the like can be realized with less circuit resources.

  The display unit 111 has a function of displaying a captured image, various menu screens, and the like. For the display unit 111, a liquid crystal display (LCD), an organic EL display (OLED) or the like is used. The RAM 112 is a random access memory for temporarily storing data of captured images and the like. The ROM 119 is a read only memory that stores various correction data, a program for executing a predetermined process, and the like. The recording medium 110 is for recording data of a captured image. The recording medium 110 may be removable, for example, a memory card using a non-volatile semiconductor memory such as an SD memory card. The RAM 112, the ROM 119, and the recording medium 110 are connected to the DSP 109.

  The CPU 114 is a control device that controls the entire imaging apparatus 100, and centrally controls the components. At the same time, setting of various setting parameters and the like is performed for each component. Also, the CPU 114 includes a cache memory and the like capable of electrically writing and erasing data, and executes a program recorded therein. The memory is used as a program storage area executed by the CPU, a work area during program execution, a data storage area, and the like. The CPU 114 also performs analysis and image processing of a signal output from the imaging element 106. The analysis result is output as image information. The image information is an analysis result of the image, and includes not only the brightness and color of the subject but also the presence / absence and features of the object (including the human body), the position / velocity / acceleration of the object, the detection result of the specific subject, and the like. Further, the CPU 114 controls the focus drive circuit 116 based on the AF calculation result output from the DSP 109, and adjusts the focus position of the imaging optical system by the focus actuator 118.

  Next, an example of the pixel array of the imaging element 106 in the imaging device 100 according to the present embodiment will be described with reference to FIG. The pixel array shown in FIG. 3 corresponds to the array of the pixel units 11 included in the first substrate 10.

  For example, as shown in FIG. 3, the imaging element 106 has a pixel area PA (pixel array) in which a plurality of pixel units 11 (unit pixels) are arranged in a two-dimensional array along the row direction and the column direction. There is. Although the pixel area PA is not particularly limited, it can include, for example, a pixel array of pixel units 11 of 4000 rows × 8000 columns. In FIG. 3, among these, a pixel array of 6 rows × 8 columns is extracted and shown.

  Each pixel unit 11 includes two photodiodes (hereinafter referred to as "PD") 401a and 401b, one microlens (not shown), and a color filter (not shown). The PD 401 a and the PD 401 b are photoelectric conversion units of two sub-pixels a and b configured in the pixel unit 11, respectively. One microlens is provided in each of the pixel units 11 and condenses incident light on two photoelectric conversion units of the same pixel unit 11.

  Reference symbols a and b shown in the pixel unit 11 in FIG. 2 denote sub-pixels a and b divided into pupils in the left and right directions. The output signal a (A signal) output from the sub pixel a and the output signal b (B signal) output from the sub pixel b are focus detection signals used for focus detection. A signal (A + B signal) obtained by adding the A signal and the B signal is used for image generation (generation of a captured image). Further, symbols R, G, and B represent colors (spectral characteristics) of the color filter, R is a red filter, G is a green filter, and B is a blue filter. Color filters of the same color are assigned to the two PDs 401 a and 401 b constituting one pixel unit 11. In addition, although the example which has arrange | positioned the color filter by what is called Bayer arrangement is shown in FIG. 2, arrangement | positioning of a color filter is not limited to this. In addition, the division direction of the pupil is not limited to the left and right, and may be up and down, or may be divided into two or more.

  Next, the relationship between the light beam coming out of the exit pupil of the imaging optical system (imaging lens) and the pixel section 11 of the imaging element 106 will be described using FIG. The pixel unit 11 includes the PDs 401 a and 401 b, and the color filter 201 and the microlens 202 disposed on the PDs 401 a and 401 b. It is assumed that the light flux that has passed through the exit pupil 203 of the imaging optical system (imaging lens) enters the pixel unit 11 with the optical axis 204 of the imaging optical system as the center. Focusing on the light beams passing through different pupil regions (partial regions) 205 and 206 in the exit pupil 203 of the imaging optical system (imaging lens), the light beams passing through the pupil region 205 among these are through the microlens 202 The light is received by the PD 401 a of the sub-pixel a. On the other hand, the light flux that has passed through the pupil region 206 is received by the PD 401 b of the sub-pixel b via the microlens 202.

  Thus, the sub-pixels a and b respectively receive light passing through different areas (areas different from each other) of the exit pupil 203 of the imaging lens. For this reason, it is possible to perform focus detection of the phase difference method by comparing the A signal which is the output signal of the sub pixel a with the B signal which is the output signal of the sub pixel b.

  Next, image signal waveforms obtained from the sub-pixels a and b of the image sensor 106 will be described with reference to FIG. FIG. 5A is a graph showing an example of image signal waveforms obtained from the sub-pixels a and b when out of the in-focus state (non-in-focus state). FIG. 5B is a graph showing an example of image signal waveforms obtained from the sub-pixels a and b in the in-focus state (substantially in-focus state). In FIGS. 5A and 5B, the vertical axis represents signal output, and the horizontal axis represents position (pixel horizontal position).

  When out of focus (in the out-of-focus state), as shown in FIG. 5A, the image signal waveforms (A signal and B signal) obtained from the sub pixels a and b do not match each other. , Greatly deviated. When the in-focus state is approached from the out-of-focus state, as shown in FIG. 5B, the deviation between the image signal waveforms of the sub-pixels a and b decreases. Then, in the in-focus state, these image signal waveforms overlap each other. In this way, it is possible to detect the shift amount of defocus (defocus amount) by detecting the shift (shift amount) of the image signal waveform obtained from the sub-pixels a and b, and by using this information The focusing of the imaging optical system can be performed.

  Next, a configuration example of the imaging element 106 in the imaging device 100 according to the present embodiment will be specifically described.

  As illustrated in FIG. 2, the imaging device 106 has a stacked configuration in which a first substrate 10 including the pixel unit 11 and a second substrate 20 including the signal processing unit 21 are stacked. FIG. 6 is a view showing the arrangement of the pixel units 11 and the positional relationship on the plane of the signal processing unit 21. As shown in FIG. The squares shown in white indicate one pixel unit 11 provided on the first substrate 10, and the attached characters indicate the color of the color filter provided in each pixel unit 11. In addition, a rectangle shown in gray, which is disposed on the back of the pixel unit 11, indicates one signal processing unit 21 provided on the second substrate 20.

  As shown in FIG. 6, a plurality of pixel units 11 and signal processing units 21 are periodically arranged in the row direction and the column direction in each substrate to form a pixel array and a circuit array. The area of the pixel portion 11 in the first substrate 10 is smaller than the area of the signal processing portion 21 in the second substrate 20. Therefore, a predetermined number of pixel units 11 indicated by dotted lines are used as pixel blocks 12, and one signal processing unit 21 is disposed corresponding to each pixel block 12. Although the pixel unit 11 of 4 rows × 12 columns is one pixel block 12 in the present embodiment, this is an example, and a different number or arrangement of pixels may be used as the pixel block 12. In addition, the signal processing unit 21 corresponding to each pixel block 12 does not necessarily have to correspond in position (for example, positioned immediately below the pixel unit 11). The pixel unit 11 and the signal processing unit 21 may be arranged separately.

  As shown in FIG. 7, each of the pixel units 11 includes PDs 401 a and 401 b, transfer transistors 402 a and 402 b, a reset transistor 405, an amplification transistor 404, and a selection transistor 406. The anode of the PD 401 a is connected to the ground voltage line, and the cathode of the PD 401 a is connected to the source of the transfer transistor 402 a. The anode of the PD 401 b is connected to the ground voltage line, and the cathode of the PD 401 b is connected to the source of the transfer transistor 402 b. The drain of the transfer transistor 402 a and the drain of the transfer transistor 402 b are connected to the source of the reset transistor 405 and the gate of the amplification transistor 404. A connection node of the drains of the transfer transistors 402a and 402b, the source of the reset transistor 405, and the gate of the amplification transistor 404 forms a floating diffusion portion (hereinafter, referred to as an "FD portion") 403. The drain of the reset transistor 405 and the drain of the amplification transistor 404 are connected to the power supply voltage line (voltage Vdd). The source of the amplification transistor 404 is connected to the drain of the selection transistor 406.

  The PDs 401a and 401b of the sub-pixels a and b photoelectrically convert incident light signals (optical images) and accumulate charges according to the exposure amount. The transfer transistors 402 a and 402 b transfer the charges accumulated in the PDs 401 a and 401 b to the FD unit 403 in response to the signals PTXA and PTXB at High level. The FD unit 403 converts the charge transferred from the PDs 401 a and 401 b into a voltage according to the amount of charge by its parasitic capacitance, and applies the voltage to the gate of the amplification transistor 404. The reset transistor 405 is a switch circuit for resetting the FD unit 403, and resets the FD unit 403 in response to the high level signal PRES. In order to reset the charge of the PDs 401a and 401b, the signal PRES and the signals PTXA and PTXB are simultaneously set to High level, and the transfer transistors 402a and 402b and the reset transistor 405 are turned on. Then, the PDs 401 a and 401 b are reset via the FD unit 403. The selection transistor 406 outputs the pixel signal converted into the voltage by the amplification transistor 404 to the output node vout of the pixel unit 11 (pixel) in response to the signal PSEL at High level.

  In each row of the pixel array of the first substrate 10, drive signal lines (not shown) are arranged extending in the row direction. The drive signal line is connected to a vertical scanning circuit provided on the first substrate 10 or the second substrate 20. A predetermined drive signal for driving the pixel readout circuit of the pixel unit 11 is output to the drive signal line at a predetermined timing from the vertical scanning circuit. Specifically, each drive signal line includes a plurality of (for example, four) signal lines for supplying the above-described signal PTXA, signal PTXB, signal PRES, and signal PSEL to the plurality of pixel units 11 arranged in the row direction. including. Each signal line forms a signal line common to a plurality of pixel units 11 belonging to the same row.

  A readout circuit for reading out a signal from each pixel unit 11 in the image sensor 106 will be described with reference to FIG. FIG. 8 shows an equivalent circuit of the readout circuit of the image sensor 106. In FIG. 8, among the pixel units 11 shown in FIG. 6, only the pixel units 11 arranged in odd-numbered columns are shown. Then, four signal lines 803 a are provided for each column of the pixel portion 11 in the first substrate 10. The signal line 803 a is connected to a portion 803 b having a current source 802 in the second substrate 20 through the connection portion 801. The signal output from each pixel unit 11 is read from the first substrate 10 to the second substrate 20 via the signal line 803 a and the signal line 803 b. Note that in the following description, the signal line 803 a and the signal line 803 b are simply referred to as the signal line 803 when they are described without distinction. In addition, although four signal lines 803 are provided for each column of the pixel unit 11, each signal line is represented by col_xN (x: column number of the pixel unit 11, N: A to D). Specifically, the pixel unit 11 in the first row is connected to col_xA. Similarly, the pixel units 11 in the second to fourth rows are sequentially connected to the signal lines col_xB to col_xD. The signal line 803 is arranged in the other columns as well as the pixel section 11 in the first column. In the present embodiment, four signal lines 803 are provided for each column of the pixel unit 11, but the present invention is not limited to this. It is preferable to provide more signal lines 803 for faster reading. However, it is preferable that the number of signal lines be a multiple of two or a multiple of four. Although only one pixel block 12 is shown in FIG. 8, a plurality of pixel blocks are arranged in a matrix in the pixel array. That is, the signal line 803 is shared with the pixel units 11 of the other pixel blocks.

  Each signal line 803 is connected to the signal processing unit 21 provided on the second substrate 20. As shown in FIG. 6, in the image sensor 106 of the present embodiment, one signal processing unit 21 is provided for a pixel block 12 including a plurality of pixel units 11. Therefore, a plurality of signal lines 803 are connected to the signal processing unit 21. The signal processing unit 21 includes a multiplexer circuit 804 (hereinafter referred to as an MPX circuit), and a plurality of signal lines 803 are connected to the input of the MPX circuit 804. Furthermore, the signal processing unit 21 includes an ADC circuit 805, and the ADC circuit 805 is connected to the output of the MPX circuit 804. By providing the MPX circuit 804 between the plurality of signal lines 803 and the ADC circuit 805, the signal processing unit 21 can process a plurality of signals at high speed by time division in one ADC circuit 805. Although described in detail in the other embodiments below, in this embodiment, the ADC circuit 805 adopts a successive approximation type AD conversion format. By using this method, high speed and low power consumption of the ADC circuit 805 can be realized. Further, in the present embodiment, the MPX circuit 804 corresponds to a selection unit for selecting a signal line to be connected to the ADC circuit 805 from the plurality of signal lines 803.

  In the present embodiment, the signal processing unit 21 has two MPX circuits 804a and 804b, to which ADC circuits 805a and 805b correspond. The MPX circuit 804a is configured to be able to receive signals from col_xA and col_xC connected to a pixel having an R color filter. Also, the MPX circuit 804b is configured to be able to receive signals from col_xB and col_xD connected to a pixel having a G color filter. The output of the MPX circuit 804a is connected to the ADC circuit 805a, and the output of the MPX circuit 804b is connected to the ADC circuit 805b. Each ADC circuit 805 can independently operate the ADC function. Although the signal processing unit 21 of the present embodiment is configured to include two MPX circuits and ADC circuits, the present invention is not limited thereto, and may be configured to include only one or may be configured to include three or more. .

  Although the signal line 803 and the MPX circuit 804 are directly connected to each other, a sample and hold circuit (not shown) may be provided between the signal line 803 and the MPX circuit 804 to temporarily hold a signal read from the pixel portion 11.

  Further, the ADC circuits 805 of this embodiment can perform power saving operation (standby operation) collectively or individually. In order to control the power saving operation, a PSAVE control unit 806 is provided in the second substrate 20. In response to the control signal from the PSAVE control unit 806, each ADC circuit 805 starts or ends the power saving operation. Note that an example of the power saving operation is an operation of stopping the supply of the power supply or the clock supplied to the ADC circuit 805. The PSAVE control unit 806 may be provided in the signal processing unit 21 or may be provided in area units such as row units or column units.

  Although only the pixel units 11 provided in odd-numbered columns are shown in FIG. 8, the same circuit configuration is assumed in the pixel units 11 arranged in even-numbered columns.

  FIG. 9 is a diagram showing a normal read operation of the image sensor 106. As shown in FIG. In the operation in FIG. 9, readout is sequentially performed without adding a signal read out from the pixel unit 11. This normal readout operation is mainly used when acquiring a high definition still image. In FIG. 9, the case where only the signal for imaging is output without outputting the signal for focus detection will be described. That is, the pixel unit 11 does not output the first signal based on the signal of the PD of only a part of the plurality of PDs, but outputs only the second signal based on the signal of the plurality of PDs.

  A signal PRES in FIG. 9 indicates a signal supplied from the vertical scanning circuit to the gate of the reset transistor 405 via a control line (not shown). Similarly, a signal PSEL indicates a signal supplied from the vertical scanning circuit to the gate of the selection transistor 406 of the N-th row pixel unit 11 through the control line. Note that, with regard to the signal PSEL, the row position of the pixel unit 11 to be output is shown at the end. That is, the signal PSEL (1) indicates that the signal PSEL is output to the pixel unit 11 in the first row. A signal PTXA indicates a signal supplied from the vertical scanning circuit to the gate of the transfer transistor 402a via the control line. A signal PTXB indicates a signal supplied from the vertical scanning circuit to the gate of the transfer transistor 402b via the control line. Although the signal PSEL has been described as a signal corresponding to each row, a plurality of signals PSEL may be supplied to each row. With this configuration, it is possible to select which pixel signal is to be output periodically also in the column direction.

  A signal PSAVE in FIG. 9 indicates a signal supplied from the PSAVE control unit 806 to each ADC circuit 805. By inputting a signal corresponding to High level to the ADC circuit 805, the input ADC circuit 805 starts power saving operation. In addition, a normal operation is performed by inputting a signal corresponding to the low level to the ADC circuit 805. In the present embodiment, the signal PSAVE is described as a single signal for simplification of the description, but the present invention is not limited to this. For example, by being configured to be able to separately supply the signal PSAVE for each region in the pixel array or for each ADC circuit 805, control of the power saving operation can be performed for each region.

  FIG. 9 shows operations relating to the MPX circuit 804a and the ADC circuit 805a. As shown in FIG. 8, the MPX circuit 804 a and the ADC circuit 805 a have the R color filters in the arrangement of the pixel blocks 12 in the first and third rows, and are odd among the 1 to 12 columns. A signal of the pixel unit 11 located in the column is input. Therefore, FIG. 9 shows an operation related to the operation of the pixel unit 11 located in the first row and the third row and in the odd numbered column among the 1 to 12 columns.

  Further, in FIG. 9, the column Col_xN of the signal line indicates which column is selected as the column from which the MPX circuit 804a outputs a signal to the ADC circuit 805a. The notation of this xN will be described. x indicates the column number of the pixel unit 11. In addition, N indicates one of four signal lines 803 arranged corresponding to the pixel units 11 in one column.

  At time t1, the vertical scanning circuit sets the signal PRES output to the pixel units 11 in the first and third rows to the high level. Thus, the reset transistor 405 of the pixel unit 11 in the first row is turned on. Thus, the FD unit 403 is reset to a potential corresponding to the power supply voltage Vdd. Further, at time t1, the vertical scanning circuit sets the signal PSEL (1) to the high level. Thus, the selection transistor 406 of the pixel unit 11 in the first row is turned on. Therefore, the current supplied by the current source 802 shown in FIG. 8 is supplied to the amplification transistor 404 via the selection transistor 406 of the pixel portion 11 in the first row. Thus, a source follower circuit is formed by the power supply voltage Vdd, the amplification transistor 404, and the current source 802. That is, the amplification transistor 404 performs a source follower operation of outputting a signal corresponding to the potential of the FD portion 403 to the signal line 803 through the selection transistor 406. In the present embodiment, the period after time t1 corresponds to the N signal readout period.

  At time t2, the vertical scanning circuit sets the signal PRES output to the pixel unit 11 in the first row to the low level. Thereby, the reset transistor 405 of the pixel unit 11 in the first row is turned off. Thus, the reset of the FD unit 403 is released. The amplification transistor 404 outputs a signal based on the potential of the FD unit 403 whose reset has been released to the corresponding signal line 803 shown in FIG. This signal is denoted as N signal (noise signal). As a result, an N signal is output from the pixel unit 11 to the signal line 803 of each column. As a result, N signals corresponding to the pixel units 11 in the odd numbered columns among the 1st to 12th columns are input to the MPX circuit 804a during the synchronization.

  After time t2, the MPX circuit 804a sequentially connects the signal line 803 corresponding to the pixel section 11 in the odd numbered column among the 1 to 12 columns to the ADC circuit 805a by the signal MPX supplied from the TG 113.

  The ADC circuit 805a AD converts an N signal of the signal line 803 in the first column corresponding to the pixel unit 11 in the first row, which is output from the MPX circuit 804a, into a digital signal. Thereafter, the N signal output to the signal line 803a corresponding to the pixel section 11 in the first row of the odd-numbered column among the 1 to 12 columns is AD converted to a digital signal. Since each N signal is already input to the MPX circuit 804a, high-speed AD conversion is possible only by switching the output of the MPX circuit 804a. In the present embodiment, the period after time t2 corresponds to the N signal AD conversion period.

  At time t3, the vertical scanning circuit sets the signal PRES input to the pixel unit 11 in the third row to the low level. Thereby, the reset transistor 405 of the pixel unit 11 in the third row is turned off. Thus, the reset of the FD unit 403 is released. The amplification transistor 404 outputs an N signal, which is a signal based on the potential of the FD unit 403 whose reset has been released, to the signal line 803 shown in FIG. Thus, the N signal is output from the pixel unit 11 in the third row to the signal line 803 of each column. As a result, N signals corresponding to the pixel units 11 in the odd numbered columns among the 1st to 12th columns are input to the MPX circuit 804a during the synchronization.

  After time t3, the MPX circuit 804a sequentially connects the signal line 803 corresponding to the pixel section 11 in the odd numbered column among the 1 to 12 columns to the ADC circuit 805a by the signal MPX supplied from the TG 113.

  The ADC circuit 805a AD converts the N signal of the signal line 803 in the first column corresponding to the pixel unit 11 in the third row, which is output from the MPX circuit 804a, into a digital signal. Thereafter, the N signal output to the signal line 803 corresponding to the pixel section 11 in the odd numbered column among the 1 to 12 columns is AD converted to a digital signal sequentially. Since each N signal is already input to the MPX circuit 804a, high-speed AD conversion is possible only by switching the output of the MPX circuit 804a. In the present embodiment, the period after time t3 corresponds to the N signal AD conversion period.

  At time t3, the vertical scanning circuit sets the signals PTXA and PTXB to be output to the pixel units 11 in the first row to the high level. As a result, the charge (which is an electron in this embodiment) accumulated in the PDs 401 a and 401 b is transferred to the FD unit 403 via the transfer transistors 402 a and 402 b. The FD unit 403 adds the charges of the PDs 401 a and 401 b. As a result, the FD unit 403 has a potential corresponding to the sum of the charges of the PDs 401 a and 401 b. Suppose that the signal output from the amplification transistor 404 is an A signal on the basis of the potential of the FD section 403 due to the charge of only the PD 401a. Further, temporarily, the signal output from the amplification transistor 404 is set as a B signal based on the potential of the FD section 403 due to the charge of only the PD 401 b. According to this notation, the signal output from the amplification transistor 404 can be regarded as an A + B signal obtained by adding the A signal and the B signal, based on the potential of the FD unit 403 corresponding to the charge obtained by adding each charge of the PDs 401a and 401b. . The A + B signal of the pixel unit 11 in the first row is output to the signal line 803 of each column. As a result, the A + B signal corresponding to the pixel section 11 in the odd numbered column among the 1st to 12th columns is input to the MPX circuit 804a during the synchronization. The A + B signal is a second signal based on signals generated by a plurality of PDs. The second signal can be used as a signal for imaging. In the present embodiment, the period after time t3 corresponds to the A + B signal readout period.

  After time t4, the MPX circuit 804a sequentially connects the signal line 803 corresponding to the pixel section 11 in the odd numbered column among the 1 to 12 columns to the ADC circuit 805a by the signal MPX supplied from the TG 113.

  The ADC circuit 805a AD-converts the A + B signal of the signal line 803 in the first column corresponding to the pixel section 11 in the first row, which is output from the MPX circuit 804a, into a digital signal. Thereafter, the A + B signal output to the signal line 803 corresponding to the pixel section 11 in the odd numbered column among the 1 to 12 columns is AD converted to a digital signal. Since each A + B signal is already input to the MPX circuit 804a, high-speed AD conversion is possible only by switching the output of the MPX circuit 804a. In the present embodiment, the period after time t4 corresponds to an A + B signal AD conversion period.

  At time t4, the vertical scanning circuit sets the signals PTXA and PTXB output to the pixel units 11 in the third row to the high level. As a result, the A + B signal of the pixel unit 11 in the third row is output to the signal line 803 of each column. As a result, the A + B signal corresponding to the pixel section 11 in the odd numbered column among the 1st to 12th columns is input to the MPX circuit 804a during the synchronization. In the present embodiment, the period after time t4 corresponds to the A + B signal readout period.

  After time t5, the MPX circuit 804a sequentially connects the signal line 803 corresponding to the pixel section 11 in the odd numbered column among the 1 to 12 columns to the ADC circuit 805a by the signal MPX supplied from the TG 113.

  The ADC circuit 805a AD converts an A + B signal of the signal line 803 in the first column corresponding to the pixel unit 11 in the third row, which is output from the MPX circuit 804a, into a digital signal. Thereafter, the A + B signal output to the signal line 803 corresponding to the pixel section 11 in the odd numbered column among the 1 to 12 columns is AD converted to a digital signal. Since each A + B signal is already input to the MPX circuit 804a, high-speed AD conversion is possible only by switching the output of the MPX circuit 804a. In the present embodiment, a period after time t5 corresponds to an A + B signal AD conversion period.

  Then, these operations are performed in parallel also for the second and fourth rows provided with the G color filter. Furthermore, the same applies to the pixel units 11 located in the even columns. Parallel and sequential execution on each pixel block 12 makes it possible to obtain an image signal of one screen. When it is desired to acquire the A signal or the B signal, either the signal PTXA or the signal PTXB may not be controlled at the timing when the A + B signal is read. Although described in detail in the other embodiments, it is preferable to read out the N signals and then read out the A + B signals as the readout order.

  Here, one of the characteristic effects of the present embodiment will be described.

In the operation shown in FIG. 9, a plurality of operations are performed in parallel as follows.
(1) Parallel operation of AD conversion of N signals corresponding to the pixel units 11 in the first row and readout of N signals corresponding to the pixel units 11 in the third row (2) Correspond to the pixel units 11 in the third row Parallel operation of AD conversion of N signals and readout of A + B signals corresponding to the pixel units 11 in the first row (3) AD conversion of A + B signals corresponding to the pixel units 11 in the first row, and 3rd row Parallel operation with readout of A + B signal corresponding to pixel unit 11

  By this parallel operation, it is possible to shorten the waiting period until the next AD conversion is performed after the ADC 805a completes one AD conversion. Thereby, the period required for AD conversion of the signal which all the pixel parts 11 output can be shortened. Therefore, it is possible to make the frame rate higher in the entire imaging device 100.

  Although FIG. 9 shows an example in which the N signal read period and the A + B signal read period are simultaneously controlled by the connection line 803 connected to the same MPX circuit 804, the present invention is limited to this operation. Absent. It is an important feature that the reading operation is started to another signal line 803 which can be connected to the ADC circuit 805 at the same time when the ADC conversion circuit 805 performs AD conversion of each signal. That is, it is preferable to appropriately change the read timing for each signal line 803, the read timing and the timing of AD conversion in accordance with the imaging conditions (ISO sensitivity and frame rate) and the characteristics of the image sensor 106. For example, AD conversion of each signal is sequentially performed in each AD conversion period after time t2 and time t4, but the timing of AD conversion corresponding to the first column and other columns is different. The end of the reading period does not have to be uniform, as long as it ends by the timing of the AD conversion. Therefore, in FIG. 9, the end of the readout period of each column is collectively performed at time t2 and time t4, but it may be shifted backward according to the timing of AD conversion for each column. More specifically, the end timing of the readout period of the third column with respect to the first column is set immediately before the end of AD conversion of the first column. The end timing of the readout period of the other column can also be shifted before the end of the immediately preceding AD conversion. By operating at such timing, it is possible to perform AD conversion immediately after signal readout, and it is possible to shorten the extra time until AD conversion is started.

  In addition, although the end of the read period has been described above, the same applies to the start. In particular, when the end timing of the read period changes, it is preferable to change the start timing of the read period accordingly so that the lengths of the read periods of the respective columns become substantially the same. Further, in FIG. 9, the read period is uniformly started at, for example, time t1 and time t3, but the signal MPX (Col_xN) corresponding to the period for performing AD conversion of each column is advanced. Is possible. That is, it is not necessary to wait for the end of AD conversion of all the columns, and it is possible to start reading of the next signal at the timing when the AD conversion period for each column ends. This can further improve the frame rate. Further, the load on the current source 802 can also be reduced by shifting the readout periods for the plurality of signal lines 803 uniformly. That is, in order to individually execute the reading operation at different timings with respect to the corresponding pixel portion 11, the signal PRES, the signal PTXA, the signal PTXB and the like require a plurality of wirings for each row, and the control is also complicated. However, on the other hand, the effect of reducing the peak consumption current supplied to the imaging element 106 can be obtained, and the reduction of the power consumption can be realized as a whole. Although it is preferable to shift the timing to an appropriate timing for each signal line 803, the timing may be shifted with a predetermined number of signal lines 803 as one unit when the circuit becomes complicated.

  Next, a characteristic readout operation of the imaging element 106 in the imaging device 100 according to the present embodiment will be described with reference to FIG. FIG. 10 is a diagram showing the addition readout operation of the imaging element 106. In the operation in FIG. 10, the signals read out from the pixel unit 11 are sequentially read out while being added before AD conversion. This addition read operation is mainly used when acquiring a moving image. In FIG. 10, the case where only the signal for imaging is output without outputting the signal for focus detection will be described. The signal lines shown in FIG. 10 are the same as in FIG. Furthermore, the description of the operation common to the normal read operation is omitted.

  At time t2, the vertical scanning circuit sets the signal PRES output to the pixel unit 11 in the first row to the low level. As a result, an N signal is output from the pixel unit 11 to the signal line 803 of each column. As a result, N signals corresponding to the pixel units 11 in the odd numbered columns among the 1st to 12th columns are input to the MPX circuit 804a during the synchronization.

  After time t2, the MPX circuit 804a sequentially connects the signal line 803 corresponding to the pixel section 11 in the odd numbered column among the 1 to 12 columns to the ADC circuit 805a by the signal MPX supplied from the TG 113. Note that in the addition read operation, unlike the normal read operation, a plurality of signal lines 803 are simultaneously connected to the ADC circuit 805a. By this operation, the output of the MPX circuit 804a becomes substantially equivalent to a signal obtained by averaging the signals output to the signal line 803 connected simultaneously. Thus, signal addition can be performed between the signal lines 803. In this embodiment, corresponding signal lines 803 are simultaneously connected to the ADC circuit 805a in order to add adjacent two columns of the same color as in the first and third columns. As a result, the number of AD conversions required is half that of the normal read operation. As a whole, the AD conversion can be completed in half the time of the normal read operation. In the present embodiment, the signal line 803 and the MPX circuit 804 correspond to an addition circuit for adding the signal from the pixel unit 11.

  Further, at timing when AD conversion is completed after time t2, the signal PSAVE output to each ADC circuit 805 is set to the high level. Thus, the ADC circuit 805 switches to the power saving operation. Then, by setting the level to Low at time t3, the power saving operation is completed and AD conversion can be performed to the next signal.

  Further, in FIG. 10, the signal PSAVE is set to the high level at the timing when the AD conversion of each row or each pixel block is completed and which corresponds to the horizontal blanking period. This enables further power saving. Note that since the respective ADC circuits 805 operate independently, it is not necessary to execute the power saving operation collectively for the entire imaging device 106. It is preferable to execute the power saving operation appropriately in accordance with the operation of each ADC circuit 805.

  By performing signal addition using the MPX circuit 804 provided in the previous stage of the ADC circuit 805 in this manner, it is possible to shorten the time relating to AD conversion. Then, by performing the power saving operation of the ADC circuit 805 in the shortened time, it is possible to realize the power saving of the entire imaging device 106 while maintaining the frame rate. In the present embodiment, the number of signal additions is two columns, but three or more columns may be added. By increasing the addition number, it is possible to further shorten the AD conversion time, and it is possible to further save power. Furthermore, the frame rate can also be improved.

  Further, in the case where a sample and hold circuit is provided between the signal line 803 and the MPX circuit 804, it is not necessary to simultaneously connect a plurality of signal lines 803 to the MPX circuit 804 at the time of signal addition. For example, signal addition can be realized by further providing a switch circuit or the like for connecting capacitors (such as capacitors) holding signals in the sample and hold circuit. In addition, the addition read operation may be performed by combining a signal addition method by connecting the capacitances and an addition method in which a plurality of signal lines 803 are simultaneously connected to the MPX circuit 804.

  In the present embodiment, the operation of adding signals of the same color is described, but signals of different colors may be added. It can be used as a signal for AF and exposure calculation other than the generation of an image signal.

  Further, although only the read timing is described in each timing chart, the reset operation of each PD 401 in the pixel unit 11 is performed before the read timing. The scan timing for each pixel unit 11 in the reset operation is also performed in conjunction with the readout timing described in the present embodiment in order to make the accumulation period the same for the entire screen.

Second Embodiment
In the first embodiment, an example is shown in which signal addition in the column direction is realized by simultaneously connecting a plurality of signal lines 803 connected to the MPX circuit 804 to the ADC circuit 805. In this embodiment, an example of connection of the signal line 803 and the MPX circuit 804, which is different from the first embodiment, is shown, and an operation of performing signal addition also in the row direction is shown.

  A read out circuit for reading out a signal from each pixel unit 11 in the image pickup device 106 in the present embodiment will be described with reference to FIG. FIG. 11 corresponds to FIG. 8 in the first embodiment, and shows an equivalent circuit related to the readout circuit of the image sensor 106. The same components as in FIG. 8 will be assigned the same reference numerals and descriptions thereof will be omitted.

  The signal output from each pixel unit 11 in FIG. 11 is read out via the signal line 803. Four signal lines 803 are provided for each column of the pixel unit 11. Each signal line is represented by col_xN (x: column number of the pixel unit 11, N: A to D). The signal line 803 is arranged in the other columns as well as the pixel section 11 in the first column. The point of difference with the circuit in the first embodiment in FIG. 11 is the connection form of the signal line 803 and the MPX circuit 804. Specifically, although four signal lines 803 are provided for each column of the pixel unit 11 in the present embodiment, the present invention is not limited to this. It is preferable to provide more signal lines 803 for faster reading. However, it is preferable that the number of signal lines be a multiple of 2 or 4 or a multiple of the number of signals to be added.

  In FIG. 11, the MPX circuit 804 and the ADC circuit 805 have R color filters, and the signal of the pixel portion 11 located in the odd row among the 1st to 3rd rows and the 1st to 12th columns is It is input. Furthermore, the signal of the pixel unit 11 in the second row and the fourth row, which is provided with the G color filter, and is positioned in the odd numbered column among the 1 to 12 columns is input. In FIG. 11, only the odd columns necessary for the description are illustrated, and the other odd columns and even columns are omitted for simplification.

  FIG. 12 is a diagram showing the addition readout operation of the image sensor 106 in the second embodiment. In the operation in FIG. 12, readout is sequentially performed while adding signals read out from the pixel unit 11 before AD conversion. This addition read operation is mainly used when acquiring a moving image. In FIG. 12, a case where only a signal for imaging is output without outputting a signal for focus detection will be described. The signal lines shown in FIG. 12 are the same as those in FIG. 10, and only the signal input to the MPX circuit 804 is different. Further, the description of the operation common to the operation shown in the first embodiment will be omitted.

  At time t2, the vertical scanning circuit sets the signal PRES output to the pixel unit 11 in the first row and the signal PRES output to the pixel unit 11 in the third row to the low level. As a result, an N signal is output from the pixel unit 11 to the signal line 803 of each column. As a result, N signals corresponding to the pixel units 11 in the first row and the third row among the 1st to 12th columns and corresponding to the odd-numbered columns are input to the MPX circuit 804.

  After time t2, the MPX circuit 804 sequentially connects the signal line 803 corresponding to the pixel section 11 in the odd numbered column among the 1 to 12 columns to the ADC circuit 805 by the signal MPX supplied from the TG 113. Note that, in the addition read operation of the present embodiment, a plurality of signal lines 803 are simultaneously connected to the ADC circuit 805. Specifically, Col_xA corresponding to the pixel unit 11 in the first row and Col_xC corresponding to the pixel unit 11 in the third row are simultaneously connected. By this operation, in the output of the MPX circuit 804, the signals output to the simultaneously connected signal lines 803 are added and averaged, and signal addition can be realized in the row direction. In the present embodiment, in order to add adjacent two lines of the same color as the first and third lines, it is necessary to simultaneously connect the corresponding signal lines 803 to the ADC circuit 805. As a result, a signal corresponding to AD conversion for two rows can be obtained by one AD conversion, and AD conversion can be completed in half the time of the normal read operation.

  Further, at timing when AD conversion is completed after time t2, the signal PSAVE output to each ADC circuit 805 is set to the high level. Thus, the ADC circuit 805 switches to the power saving operation. Then, immediately before time t3, by setting the level to Low, the power saving operation is completed, and AD conversion can be performed to the next signal.

  In the present embodiment, the operation of performing only addition in the row direction has been exemplified, but by combining the addition reading operation in the column direction as described in the first embodiment, addition in both the row direction and the column direction is performed. Can be realized simultaneously.

  Thus, by enabling connection from the pixel portion 11 corresponding to the column or row to be added to the MPX circuit 804 provided in front of the ADC circuit 805, both the normal read operation and the addition read operation can be realized. . Furthermore, power saving operation of the ADC circuit 805 in a time when the AD conversion time is shortened makes it possible to realize power saving of the entire imaging device 106 while maintaining the frame rate. In the present embodiment, although the number of signal additions is two lines, three or more lines may be added. Further, the addition may be combined with the column direction, and in that case, the addition number in the column direction and the addition number in the row direction may not necessarily be the same.

  Further, FIG. 6 shows an example in which one signal processing unit 21 is disposed for a pixel block 12 including a predetermined number of pixel units 11, but the pixel units 11 included in the pixel block 12 are not necessarily adjacent to each other. You do not have to. For example, in consideration of the color gravity center (sampling cycle) after adding the pixels of the same color, a block formed of the pixel unit 11 indicated by a solid line in FIG. The circuit 803 may be connected to one MPX circuit 804. By adopting the pixel block shown in FIG. 13, when signals for three pixels are added in the column direction, it is possible to align the color gravity centers after addition in the column direction. Also, by arranging in the same way in the vertical direction, it is also possible to align the color gravity centers in the vertical direction.

Third Embodiment
In the first and second embodiments, the signal addition is performed in the MPX circuit 804 to shorten the AD conversion time, and the control for causing the ADC circuit 805 to perform power saving operation is described. In the present embodiment, the control of the power saving operation for the ADC circuit 805 not used at the time of the addition reading operation is described in common, in that the signal addition is performed in the MPX circuit 804.

  A read out circuit for reading out a signal from each pixel unit 11 in the image pickup device 106 in the present embodiment will be described with reference to FIG. FIG. 14 corresponds to FIG. 8 in the first embodiment, and shows an equivalent circuit regarding the readout circuit of the imaging device 106. The same components as those in FIG. 8 are denoted by the same reference numerals.

  The signal output from each pixel unit 11 in FIG. 14 is read out via the signal line 803. Four signal lines 803 are provided for each column of the pixel unit 11. Each signal line is represented by col_xN (x: column number of the pixel unit 11, N: A to D). The signal line 803 is arranged in the other columns as well as the pixel section 11 in the first column. The difference between the circuits in the first and second embodiments in FIG. 14 is the MPX circuit 1404 and the PSAVE control unit 1406 added to the configuration of the signal processing unit 21.

  In FIG. 14, to the MPX circuit 804a, the signal of the pixel portion 11 located at the odd-numbered column among the 1st to the 3rd rows and including the R color filter is input. Further, to the MPX circuit 804b, the signal of the pixel portion 11 located in the odd-numbered column among the 1st to 12th columns, which is provided with the G color filter, is input. The output of the MPX circuit 804 a and the output of the MPX circuit 804 b are input to the MPX circuit 1404. The output of the MPX circuit 1404 is controlled based on a signal MPX2 which is a control signal, and performs an operation of switching which of the output of the MPX circuit 804a or the output of the MPX circuit 804b is to be output to the ADC circuit 805a. Specifically, the output of the MPX circuit 804a is output when the signal MPX2 is at the low level, and the output of the MPX circuit 804b is output when the signal is at the high level. By this operation, the output of the MPX circuit 804a and the output of the MPX circuit 804b can be AD converted by one of the ADC circuits 805a.

  The output of the MPX circuit 804b is input to the ADC circuit 805b, and the output of the MPX circuit 804b is AD converted. However, when the output of the MPX circuit 804a and the output of the MPX circuit 804b are AD converted by one of the ADC circuits 805a as described above, there is no need to operate the ADC circuit 805b.

  In addition, the ADC circuits 805 of this embodiment can perform power saving operation individually. In order to control the power saving operation, a PSAVE control unit 1406 is provided in the second substrate 20. In response to the individual control signals (PSAVE1 and PSAVE2) from the PSAVE control unit 1406, the ADC circuit 805a and the ADC circuit 805b each start or end the power saving operation. Therefore, when the AD conversion operation is performed only by the ADC circuit 805a, the power saving operation can be performed using the signal PSAVE2 only for the ADC circuit 805b.

  FIG. 15 is a diagram showing the addition readout operation of the image sensor 106 in the third embodiment. In the operation in FIG. 15, the signal read out from the pixel unit 11 is sequentially read out while adding the signal before AD conversion. This addition read operation is mainly used when acquiring a moving image. In FIG. 15, the case where only the signal for imaging is output without outputting the signal for focus detection will be described. As for the signal lines displayed in FIG. 15, a signal MPX2 for controlling the MPX circuit 1404, a signal PSAVE1 from the PSAVE control unit 1406, and a signal PSAVE2 are added to the signal lines shown in FIG. Furthermore, descriptions of operations common to the operations shown in the first embodiment and the second embodiment will be omitted.

  At time t2, the vertical scanning circuit sets the signal PRES output to the pixel units 11 in the first and second rows to the low level. As a result, an N signal is output from the pixel unit 11 to the signal line 803 of each column. As a result, N signals corresponding to the pixel units 11 in the first and second rows among the 1 to 12 columns and in the odd-numbered columns are input to the MPX circuit 804a and the MPX circuit 804b.

  After time t2, the MPX circuit 804 sequentially connects the signal line 803 corresponding to the pixel section 11 in the odd numbered column among the 1 to 12 columns to the ADC circuit 805a by the signal MPX and the signal MPX2 supplied from the TG 113. Note that, in the addition read operation of the present embodiment, a plurality of signal lines 803 are simultaneously connected to the ADC circuit 805a. Specifically, Col_1A corresponding to the first row pixel portion 11 in the first row and Col_3A corresponding to the third row pixel portion 11 are simultaneously connected to the MPX circuit 804a. By this operation, the output of the MPX circuit 804a becomes a signal in which the signals output to the simultaneously connected signal lines 803 are added and averaged, and signal addition can be realized in the column direction. Then, at the same timing, the signal MPX2 is controlled to the low level, and the output of the MPX circuit 804a is input to the ADC circuit 805a as the output of the MPX circuit 1404.

  Furthermore, at timing when AD conversion of the first and third columns is completed after time t2, Col_1 B corresponding to the pixel section 11 in the second row and the first column corresponds to the pixel section 11 in the third column. Col_3 B is simultaneously connected to the MPX circuit 804b. By this operation, the output of the MPX circuit 804b becomes a signal in which the signals output to the simultaneously connected signal lines 803 are added and averaged, and signal addition can be realized in the column direction. Then, at the same timing, the signal MPX2 is controlled to the high level, and the output of the MPX circuit 804b is input to the ADC circuit 805a as the output of the MPX circuit 1404.

  Then, by performing the addition read operation by repeating the above operation, it becomes possible to complete the AD conversion operation for two lines in the time for one row in the normal read operation. That is, two ADC circuits 805, which are necessary for the normal read operation, are sufficient for reading out the entire pixel block 12 with one ADC circuit 805. Therefore, for the ADC circuit 805b which has become unnecessary, the signal PSAVE2 is controlled to the high level, and the power saving operation can be performed constantly during the addition read operation, and the power consumption can be largely reduced.

  In the present embodiment as well, power saving can be further achieved by setting the signal PSAVE to the high level when the AD conversion operation in the ADC circuit 805a is completed, as in the second embodiment.

  By providing a plurality of MPX circuits in the signal processing unit 21 as described above, it is possible to provide an ADC circuit which does not need to be operated in the addition read operation. Then, power saving operation of the ADC circuit can realize power saving of the entire imaging device 106 while maintaining the frame rate. In the present embodiment, the number of signal additions is two columns, but three or more columns may be added. Further, it may be combined with the addition in the row direction, and in that case, the addition number in the column direction and the addition number in the row direction may not necessarily be the same.

  Although the AD conversion time is shortened by adding the signals of the plurality of signal lines 803 in the present embodiment, the AD conversion time can be similarly shortened by combining the thinning operation. For example, in the embodiment, the signal lines 803 in the third column, the seventh column, and the eleventh column are not connected, and only the signal lines 803 of the signals in the first column, the fifth column, and the ninth column are shown in FIG. It is also possible to read out at each timing.

  Furthermore, when thinning readout is performed, the MPX circuit 1404 can be omitted by devising the connection between the signal line 803 and the MPX circuit 804. As an example, the signal line 803 from the target pixel unit 11 (for example, the pixel unit 11 in the third column, the seventh column, and the eleventh column) to be thinned out is connected to the MPX circuit 804 b. Then, the signal line 803 from the pixel unit 11 to be read (for example, the pixel unit 11 in the first column, the fifth column, and the ninth column) is connected to the MPX circuit 804 a. By performing such connection, power saving of the MPX circuit 804 b and the ADC circuit 805 b can be performed during the thinning-out read operation, and the same effect as that of the third embodiment can be obtained.

  In the first to third embodiments, signals are read out from the pixel unit 11 (for example, the first column) located at the end of the pixel block 12, but the order of signal readout is not limited to this. For example, reading may be performed in the reverse order, or reading may be performed alternately.

Fourth Embodiment
In the first to third embodiments, an example is shown in which the power saving operation of the ADC circuit 805 is controlled at a timing at which the AD conversion operation is not performed in the readout period while performing signal addition or the like in the MPX circuit 804. . However, in the operation of the imaging device 100 using the imaging element 106, there are other timings at which the power saving operation can be set for the ADC circuit 805.

  FIG. 16 shows the timing when the image pickup apparatus 100 picks up one image. The signal VD is a vertical synchronization signal, and is supplied from the TG 113 to the imaging element 106. The signal VD is also supplied to other components such as the DFE 108 and the DSP 109, and plays a role of synchronizing the operation timing of the entire imaging apparatus 100. The cycle of the signal VD corresponds to a frame rate for acquiring a moving image, and is 1/120 second in this embodiment. The internal HD is a horizontal synchronization signal, which is an internal signal generated by a circuit in the imaging device 106 in synchronization with the signal VD supplied from the TG 113. The internal HD defines the timing of the operation of the image sensor 106, and for example, the reset operation and the readout operation of the pixel unit 11 are controlled. The image sensor 106 outputs a signal from the pixel unit 11 corresponding to a predetermined number of rows in one HD period. In the present embodiment, the time (readout period) required for the image sensor 106 to output an image signal for one frame is 1/180 second.

  As shown in FIG. 16, assuming that the readout period required to acquire one image is 1/180 seconds, the surplus time is a blanking period because it is sufficiently fast for the frame rate. During the blanking period, signal readout and AD conversion operation are not performed. Therefore, power saving operation is possible during this period. As shown in FIG. 16, the power saving operation can be achieved by setting the signal PSAVE to the High level during the blanking period.

  In addition, in order to obtain a smooth moving image, the frame rate needs to be constant. When the frame rate is fixed without being changed, the blanking period depends on the amount of signal read from the image sensor 106. For example, as shown in FIG. 17, it is assumed that a still image is acquired while capturing a moving image at a predetermined frame rate (for example, 60 fps). It is assumed that the number of pixels used for a still image is 32 million pixels, which is four times the number of pixels required for a moving image, which is 8 million. Then, the blanking period at the time of still image capturing inevitably becomes short with respect to moving image capturing. In such a case, as shown in FIG. 17, it is preferable to execute the power saving operation only during the blanking period at the time of moving image capturing, and not at the time of still image capturing. Since still images are captured singly for moving images that are continuously captured, it is possible to save power as the entire image pickup device 106 without performing the power saving operation at the time of still image capturing. It is.

  Further, as in the blanking period, there is an accumulation period as a period during which signal readout and AD conversion are not performed. As shown in FIG. 18A, after resetting the pixel section 11, the imaging element 106 is exposed for a predetermined accumulation period, and then the signal is read out in the readout period. The accumulation period is determined by the user or automatically based on the brightness of the subject, and the period is defined by the signal VD or internal HD. The power saving operation of the imaging device 106 according to the present embodiment can be set even during the accumulation period.

  As shown in FIG. 18 (b), when the accumulation period is short (for example, about 1/1000 second), the period in which the power saving operation can be set is short, and the power saving is taken into consideration in consideration of the recovery from the power saving operation. It controls so that the setting of operation is not performed. As one example, when an accumulation period of 1/8 seconds to 1 second or more is set, it is preferable to set the power saving operation during the accumulation period.

Fifth Embodiment
In the fourth embodiment, the timing at which the power saving operation of the ADC circuit 805 is performed in the imaging operation in the imaging device 100 in which the imaging element 106 is used has been described. In the present embodiment, an operation of dividing the area in the circuit array of the imaging element 106 and executing the power saving operation will be described in detail.

  FIG. 19 shows a circuit array formed on the second substrate 20 of the imaging device 106. Each element of the circuit array represents the signal processing unit 21. As a whole, n elements in the horizontal direction and m in the vertical direction The signal processing units 21 are arranged. FIG. 19A shows a normal imaging state, in which all circuit arrays are used to read out a signal in order to acquire an image using the entire screen. Therefore, all the signal processing units 21 are set to the normal operation. On the other hand, FIG. 19B shows a clip imaging state (imaging using only horizontal i to k columns and vertical h to j rows), and in order to acquire an image using only from the central portion of the screen , Peripheral circuit array is not used. Therefore, the signal processing unit 21 in the peripheral portion is set to the power saving operation during the clip imaging state.

  The circuit configuration for performing the power saving operation for each area in the present embodiment will be described using FIGS. 20 and 21. FIG. FIG. 20 is a diagram showing a wiring layout of supply lines of the signal PSAVE. The signal PSAVE of the present embodiment is supplied to each signal processing unit 21 by PSAVE_H (n) (n: column number) for horizontal control and PSAVE_V (m) (m: row number) for vertical control. PSAVE_H (n) and PSAVE_V (m) are connected by a driver circuit (not shown) and controlled by a timing signal from TG 113 and the like.

  A readout circuit for reading out a signal from each pixel unit 11 in the imaging device 106 will be described with reference to FIG. FIG. 21 shows an equivalent circuit of the readout circuit of the image sensor 106 in the fifth embodiment. FIG. 21 corresponds to FIG. 8 in the first embodiment. The same components as those in FIG. 8 are denoted by the same reference numerals.

  The signal output from each pixel unit 11 in FIG. 21 is read out via the signal line 803. Four signal lines 803 are provided for each column of the pixel unit 11. The difference with the circuit in the first embodiment in FIG. 21 is the PSAVE control unit 2106. The PSAVE control unit 2106 receives PSAVE_H (n) and PSAVE_V (m) described with reference to FIG. The PSAVE control unit 2106 includes an AND circuit, and controls the ADC circuit 805 to perform power saving operation when a signal of High level is supplied from either PSAVE_H (n) or PSAVE_V (m). By using PSAVE_H (n) and PSAVE_V (m) in this manner, control of the power saving operation can be performed on an arbitrary signal processing unit 21 in the circuit array. It is preferable that the signal processing unit 21 be provided with a latch circuit (not shown) in order to easily control the power saving operation in an arbitrary area in the circuit array. This enables a high level from both PSAVE_H (n) and PSAVE_V (m) to be stored in the latch to be controlled to the power saving operation, and the state can be held until the latch is reset. As a result, it is not necessary to always supply a high level to PSAVE_H (n) and PSAVE_V (m) corresponding to the signal processing unit 21 that wants to control power saving operation, and region selection can be performed with a higher degree of freedom. As one example, it becomes possible to control power saving operation in a plurality of regions in a pixel array. In the case of controlling the power saving operation with a higher degree of freedom, it can be coped with by increasing the number of wires of PSAVE_H (n) or PSAVE_V (m).

Sixth Embodiment
FIG. 22 is a diagram showing a signal readout operation for focus detection in addition to the normal readout operation of the image sensor 106. In the operation in FIG. 22, readout is sequentially performed without adding signals read out from the pixel unit 11. In FIG. 22, the case of outputting a signal for focus detection and a signal for imaging will be described. That is, the pixel unit 11 outputs the first signal based on the signal of one of the plurality of PDs, and outputs the second signal based on the signals of the plurality of PDs. The signal lines shown in FIG. 22 are the same as in FIG. Further, the description of the operation common to the operation shown in the first embodiment will be omitted.

  At time t3, the vertical scanning circuit sets only the signal PTXA output to the pixel units 11 in the first row to the high level. As a result, the charge accumulated in the PD 401 a is transferred to the FD unit 403 via the transfer transistor 402 a. As a result, the FD unit 403 has a potential corresponding to the PD 401 a. Then, the amplification transistor 404 outputs an A signal based on the potential of the FD unit 403 due to the charge of only the PD 401 a. The A signal of the pixel unit 11 in the first row is output to the signal line 803 of each column. As a result, the A signal corresponding to the pixel section 11 in the odd numbered column among the 1st to 12th columns is input to the MPX circuit 804a during the synchronization. In the present embodiment, the period after time t3 corresponds to the A signal read period.

  After time t4, the MPX circuit 804a sequentially connects the signal line 803 corresponding to the pixel section 11 in the odd numbered column among the 1 to 12 columns to the ADC circuit 805a by the signal MPX supplied from the TG 113.

  The ADC circuit 805a AD-converts the A signal of the signal line 803 in the first column corresponding to the pixel unit 11 in the first row, which is output from the MPX circuit 804a, into a digital signal. Thereafter, the A signal output to the signal line 803 corresponding to the pixel section 11 in the odd numbered column among the 1 to 12 columns is AD converted to a digital signal. Since each A signal is already input to the MPX circuit 804a, high-speed AD conversion becomes possible simply by switching the output of the MPX circuit 804a. In the present embodiment, the period after time t4 corresponds to an A signal AD conversion period.

  At time t4, the vertical scanning circuit sets only the signal PTXA output to the pixel unit 11 in the third row to the high level. As a result, the charge accumulated in the PD 401 a is transferred to the FD unit 403 via the transfer transistor 402 a. As a result, the FD unit 403 has a potential corresponding to the PD 401 a. Then, the amplification transistor 404 outputs an A signal based on the potential of the FD unit 403 due to the charge of only the PD 401 a. The A signal of the pixel unit 11 in the third row is output to the signal line 803 of each column. As a result, the A signal corresponding to the pixel section 11 in the odd numbered column among the 1st to 12th columns is input to the MPX circuit 804a during the synchronization. In the present embodiment, the period after time t4 corresponds to the A signal read period.

  After time t5, the MPX circuit 804a sequentially connects the signal line 803 corresponding to the pixel section 11 in the odd numbered column among the 1 to 12 columns to the ADC circuit 805a by the signal MPX supplied from the TG 113.

  The ADC circuit 805a AD converts an A signal of the signal line 803 in the first column corresponding to the pixel unit 11 in the third row, which is output from the MPX circuit 804a, into a digital signal. Thereafter, the A signal output to the signal line 803 corresponding to the pixel section 11 in the odd numbered column among the 1 to 12 columns is AD converted to a digital signal. In the present embodiment, the period after time t5 corresponds to an A signal AD conversion period.

  Also, at time t5, the vertical scanning circuit sets the signals PTXA and PTXB output to the pixel units 11 in the first row to the high level. As a result, the charge (which is an electron in this embodiment) accumulated in the PDs 401 a and 401 b is transferred to the FD unit 403 via the transfer transistors 402 a and 402 b. The FD unit 403 adds the charges of the PDs 401 a and 401 b. As a result, the FD unit 403 has a potential corresponding to the charge obtained by adding the charge of each of the PDs 401a and 401b at time t5 in addition to the charge of the PD 401a transferred at time t3. The A + B signal of the pixel unit 11 in the first row is output to the signal line 803 of each column. As a result, the A + B signal corresponding to the pixel section 11 in the odd numbered column among the 1st to 12th columns is input to the MPX circuit 804a during the synchronization. In the present embodiment, the period after time t5 corresponds to the A + B signal readout period.

  After time t6, the MPX circuit 804a sequentially connects the signal line 803 corresponding to the pixel section 11 in the odd numbered column among the 1 to 12 columns to the ADC circuit 805a by the signal MPX supplied from the TG 113.

  The ADC circuit 805a AD-converts the A + B signal of the signal line 803 in the first column corresponding to the pixel section 11 in the first row, which is output from the MPX circuit 804a, into a digital signal. Thereafter, the A + B signal output to the signal line 803 corresponding to the pixel section 11 in the odd numbered column among the 1 to 12 columns is AD converted to a digital signal. In the present embodiment, a period after time t6 corresponds to an A + B signal AD conversion period.

  At time t6, the vertical scanning circuit sets the signals PTXA and PTXB to be output to the pixel units 11 in the third row to the high level. As a result, the charge (which is an electron in this embodiment) accumulated in the PDs 401 a and 401 b is transferred to the FD unit 403 via the transfer transistors 402 a and 402 b. The FD unit 403 adds the charges of the PDs 401 a and 401 b. As a result, the FD unit 403 has a potential corresponding to the charge obtained by adding the charge of each of the PDs 401a and 401b at time t6 in addition to the charge of the PD 401a transferred at time t4. The A + B signal of the pixel unit 11 in the third row is output to the signal line 803 of each column. As a result, the A + B signal corresponding to the pixel section 11 in the odd numbered column among the 1st to 12th columns is input to the MPX circuit 804a during the synchronization. In the present embodiment, the period after time t6 corresponds to the A + B signal readout period.

  After time t7, the MPX circuit 804a sequentially connects the signal line 803 corresponding to the pixel section 11 in the odd numbered column among the 1 to 12 columns to the ADC circuit 805a by the signal MPX supplied from the TG 113.

  The ADC circuit 805a AD converts an A + B signal of the signal line 803 in the first column corresponding to the pixel unit 11 in the third row, which is output from the MPX circuit 804a, into a digital signal. Thereafter, the A + B signal output to the signal line 803 corresponding to the pixel section 11 in the odd numbered column among the 1 to 12 columns is AD converted to a digital signal. In the present embodiment, the period after time t7 corresponds to an A + B signal AD conversion period.

  As described above, by reading out the A signal before reading out the A + B signal, it becomes possible to read out both the focus detection signal and the image signal. The B signal used for focus detection is calculated by reading out the A signal and the A + B signal and subtracting the two.

Seventh Embodiment
In the first to third embodiments, the internal configuration of the imaging device 106 is exemplified. However, in order to read out a signal from the pixel unit 11 at high speed, a plurality of circuits are arranged in parallel, and simultaneous readout is performed by each circuit An action will be performed. On the other hand, an imaging element used for an imaging apparatus represented by a single-lens reflex camera has a size of several centimeters in diagonal length. Therefore, in-plane variations such as the reference voltage level inside the imaging device can not be ignored. In addition, due to manufacturing variations or asymmetry of wiring lengths of circuits, output variations may occur in each circuit arranged in parallel. In the present embodiment, a method of correcting the variation will be described. The readout circuit in the image sensor 106 will be described on the premise of the readout circuit of the first embodiment shown in FIG. Note that examples of correction include offset correction and gain correction. As the correction parameter, a value stored in advance in the ROM 119 or the like may be used, or a value generated in real time may be used immediately before or after reading out the signal.

  FIG. 23 shows one signal processing unit 21 and the pixel block 12 corresponding thereto. As shown in FIG. 8, the pixel block 12 includes the first and third rows in which the pixel units 11 having R color filters are disposed, and the second row in which the pixel units 11 having G color filters are disposed. The fourth row is read out via different MPX circuits 804 and ADC circuits 805. Therefore, it is desirable to correct the first and third lines indicated by P in FIG. 23 and the second and fourth lines indicated by Q using different correction values. This is because it is considered that common circuit variations occur in a periodic circuit, and by using the same correction value periodically, the number of parameters used for correction can be reduced, thereby reducing the processing load. And power consumption can be achieved.

  FIG. 24 shows the pixel array on the first substrate 10 and the corresponding correction parameters. As shown in FIG. 24A, n pixel blocks 12 in the horizontal direction and m pixel blocks 12 in the vertical direction are provided in the pixel array. The imaging element 106 of this embodiment is configured to share the MPX circuit and the ADC circuit in the pixel blocks 12 adjacent in the vertical direction. In this configuration, it is preferable to have corresponding correction parameters with two pixel blocks 12 sharing the circuit as one unit. FIG. 24 (b) shows correction parameters corresponding to each unit. One rectangle represents one correction parameter, and each correction parameter includes the correction parameters indicated by P and Q for each row as described in FIG.

  Although FIG. 23 illustrates an example in which different correction parameters are provided in units of rows, the present invention is not limited to this. As shown in FIG. 8, a plurality of (four in FIG. 8) signal lines 803 are provided in one column. Therefore, it is also effective to provide a correction parameter corresponding to each signal line 803. In FIG. 25, four signal lines are denoted by A to D, and correction parameters corresponding to the respective signal lines are shown. As described with reference to FIG. 24, even in the unit in which the ADC circuit is made common, correction parameters are provided, and different parameters are provided in the vertical direction as shown in FIG.

  As described above, an example in which the correction parameter is provided in accordance with the circuit cycle constituting the imaging element 106 has been described, but the correction parameter may be stored in a function form without being stored for each pixel block. Further, when the periodicity of the circuit changes due to the addition read operation or the like, it is preferable to switch the correction parameter according to the operation mode. In addition, it may be changed according to imaging conditions such as ISO sensitivity and exposure time. In addition. In the present embodiment, an example in which the correction parameter is provided and corrected in accordance with the circuit cycle is shown, but a plurality of corrections may be performed individually for each circuit cycle.

Eighth Embodiment
FIG. 26 is an equivalent circuit diagram of the ADC circuit 805 of the imaging device 106. The ADC circuit 805 has an input terminal IN and an output terminal OUT, converts an analog signal Sin (output of the MPX circuit 804) input from the input terminal IN into a digital signal Sout, and outputs the digital signal Sout from the output terminal OUT. This analog signal Sin can be one or both of the N signal and the A + B signal (S signal) described in the first embodiment. The ADC circuit 805 converts the output of the MPX circuit 804 into a digital signal Sout with 5-bit resolution.

  The ADC circuit 805 further includes a generation circuit 810 that generates a comparison signal used for comparison with the analog signal Sin. The generation circuit 810 includes a plurality of capacitive elements cp0 to cp4 each having a binary weight capacitance value, and a plurality of switches sw0 to sw4 connected to the capacitive elements cp0 to cp4. The plurality of switches sw0 to sw4 constitute a switch circuit that selects one or more of the capacitive elements cp0 to cp4. The binary weight is a set of weights (capacitance values) forming a geometric progression of common ratio 2. In the example of FIG. 26, the capacitive elements cp0 to cp4 have capacitance values of 1C, 2C, 4C, 8C, and 16C in order. One electrode of each of the capacitive elements cp0 to cp4 is connected to the supply terminal SPL of the generation circuit 810, and the other electrode is connected to each of the switches sw0 to sw4. One end of each of the switches sw0 to sw4 is connected to the capacitive elements cp0 to cp4, and the other end toggles between the terminal A and the terminal B. The ground potential GND is supplied to the terminal A, and the reference voltage VRF is supplied to the terminal B. The reference voltage VRF is a constant voltage supplied from the outside of the ADC 805, and has a value larger than the ground potential GND. When the switch sw0 toggles to the terminal A, the ground potential GND is supplied to the capacitive element cp0, and when the switch sw0 toggles to the terminal B, the reference voltage VRF is supplied to the capacitive element cp0. The same applies to the other switches sw1 to sw4. By switching the switches sw0 to sw4, the combined capacitance value of the capacitive element connected between the supply terminal SPL and the reference voltage VRF changes, and as a result, the value of the comparison signal Vcmp output from the supply terminal SPL changes Do.

  A ramp signal Vrmp from the outside of the ADC circuit 805 is further supplied to the supply terminal SPL of the generation circuit 810 via the capacitive element cp5. The capacitive element cp5 is a capacitive element for adjusting the magnitude of the ramp signal Vrmp, and has a capacitance value of 1C. That is, the capacitance value of the capacitive element cp5 is equal to the minimum capacitance value of the capacitive element groups cp0 to cp4 having a binary weight capacitance value. When the value of the ramp signal Vrmp changes, the value of the comparison signal Vcmp output from the supply terminal SPL also changes.

  By combining a set of capacitive elements connected between supply terminal SPL and reference voltage VRF, and the value of ramp signal Vrmp, comparison signal Vcmp takes any value higher than ground potential GND and lower than reference voltage VRF. sell.

  The ADC circuit 805 further comprises a comparator 815. The comparator 815 compares the value of the analog signal Sin with the value of the comparison signal Vcmp, and outputs a signal according to the comparison result. The analog signal Sin is supplied to the non-inversion terminal of the comparator 815 via the capacitive element cp6, and the comparison signal Vcmp is supplied to the inversion terminal of the comparator 815 from the supply terminal SPL of the generation circuit 810. Thus, the High level is output when the value of the analog signal Sin is equal to or greater than the value of the comparison signal Vcmp, and the Low level is output when the value of the analog signal Sin is less than the value of the comparison signal Vcmp. In this example, when the value of the analog signal Sin and the value of the comparison signal Vcmp are equal to each other, the High level is output, but the Low level may be output. The capacitive element cp6 adjusts the value of the analog signal Sin to a range where comparison with the comparison signal Vcmp is possible. In the present embodiment, in order to simplify the description, the value of the analog signal Sin is equal to or higher than the ground potential GND and equal to or lower than the reference voltage VRF, and a signal of the same size as the analog signal Sin is supplied to the non-inversion terminal of the comparator 815. Handle the case being

  Although the analog signal Sin is supplied to the non-inversion terminal of the comparator 815 and the comparison signal Vcmp is supplied to the inversion terminal of the comparator 815 in the example of FIG. 26, the magnitude relation between the value of the analog signal Sin and the value of the comparison signal Vcmp If it can be determined, other configurations can be taken. For example, the difference between the analog signal Sin and the comparison signal Vcmp may be supplied to the non-inversion terminal of the comparator 815, and the ground potential GND may be supplied to the inversion terminal of the comparator 815.

  The ADC circuit 805 further includes switches sw5 and sw6. When the switches sw5 and sw6 become conductive, the ground potential GND is supplied to the non-inversion terminal and the inversion terminal of the comparator 815, and the comparator 815 is reset.

  The ADC circuit 805 further includes a control circuit 820. The control circuit 820 is supplied with the comparison result from the comparator 815, and the control circuit 820 generates a digital signal Sout based on the comparison result and outputs it from the output terminal OUT. The control circuit 820 also transmits control signals to the switches sw0 to sw6 to switch their states.

  In FIG. 27, sw0 to sw6 indicate values of control signals supplied from the control circuit 820 to the switches sw0 to sw6. The switches sw0 to sw4 toggle to the terminal B when the supplied control signal is at the high level, and toggle to the terminal A when the control signal is at the low level. The switches sw5 and sw6 become conductive when the supplied control signal is at the high level, and become nonconductive when the control signal is at the low level. The lower side of FIG. 27 shows the analog signal Sin and the comparison signal Vcmp. In FIG. 27, the case where the value of the analog signal Sin corresponds to 00110 in binary notation is treated as an example.

  Subsequently, the AD conversion operation of the ADC circuit 805 will be described in chronological order. In the preparation period, the control circuit 820 sets the control signals supplied to the switches sw0 to sw4 to the low level, and sets the control signals supplied to the switches sw5 and sw6 to the high level. Thereby, the non-inversion terminal and the inversion terminal of the comparator 815 are reset to the ground potential GND, and the value of the comparison signal Vcmp becomes equal to the ground potential GND. Thereafter, the control circuit 820 sets the control signal supplied to the switches sw5 and sw6 to the low level. In the subsequent operation, the analog signal Sin continues to be supplied to the non-inversion terminal of the comparator 815.

  Next, when the successive approximation period starts, the control circuit 820 changes the control signal supplied to the switch sw4 to the high level. As a result, the switch sw4 is toggled to the terminal B, and the reference voltage VRF is applied to the supply terminal SPL of the generation circuit 810 via the capacitor cp4 having the first largest capacitance value in the binary weight. As a result, the comparison signal Vcmp is increased by VRF / 2, and the value of the comparison signal Vcmp becomes equal to VRF / 2. The control circuit 820 determines that the value of the analog signal Sin is smaller than the value (VRF / 2) of the comparison signal Vcmp based on the comparison result from the comparator 815, and sets the control signal supplied to the switch sw4 to low level. Back to. Thereby, the value of the comparison signal Vcmp returns to the ground potential GND. The comparison result means that the MSB (the 5th bit when the LSB is the 1st bit) of the value of the digital signal Sout is 0.

  Next, the control circuit 820 changes the control signal supplied to the switch sw3 to the high level. As a result, the reference voltage VRF is applied to the supply terminal SPL of the generation circuit 810 via the capacitor cp3 having the second largest capacitance value among the binary weights. As a result, the comparison signal Vcmp increases by VRF / 4, and the value of the comparison signal Vcmp becomes equal to VRF / 4. The control circuit 820 determines that the value of the analog signal Sin is smaller than the value (VRF / 4) of the comparison signal Vcmp based on the comparison result from the comparator 815, and sets the control signal supplied to the switch sw3 to low level. Back to. Thereby, the value of the comparison signal Vcmp returns to the ground potential GND. The comparison result means that the fourth bit of the value of the digital signal Sout is 0.

  Next, the control circuit 820 changes the control signal supplied to the switch sw2 to the high level. As a result, the reference voltage VRF is applied to the supply terminal SPL of the generation circuit 810 via the capacitor cp2 having the third largest capacitance value among the binary weights. As a result, the comparison signal Vcmp increases by VRF / 8, and the value of the comparison signal Vcmp becomes equal to VRF / 8. The control circuit 820 determines that the value of the analog signal Sin is larger than the value (VRF / 8) of the comparison signal Vcmp based on the comparison result from the comparator 815, and sets the control signal supplied to the switch sw2 to the high level. Leave. Thereby, the value of the comparison signal Vcmp is maintained at VRF / 8. The comparison result means that the third bit of the value of the digital signal Sout is one.

  Next, the control circuit 820 changes the control signal supplied to the switch sw1 to the high level. As a result, the reference voltage VRF is applied to the supply terminal SPL of the generation circuit 810 via the capacitor cp1 having the fourth largest capacitance value in the binary weight and the capacitor cp2. As a result, the comparison signal Vcmp increases by VRF / 16, and the value of the comparison signal Vcmp becomes equal to VRF * 3/16. As used herein, "*" means multiplication. The control circuit 820 determines that the value of the analog signal Sin is larger than the value (VRF * 3/16) of the comparison signal Vcmp based on the comparison result from the comparator 815, and controls the control signal supplied to the switch sw1. Stay high. Thereby, the value of the comparison signal Vcmp is maintained at VRF * 3/16. The comparison result means that the second bit of the value of the digital signal Sout is one.

  Finally, the control circuit 820 changes the control signal supplied to the switch sw0 to the high level. As a result, the reference voltage VRF is applied to the supply terminal SPL of the generation circuit 810 via the capacitor cp0 having the fifth largest capacitance value among the binary weights, and cp1 and cp2. As a result, the comparison signal Vcmp is increased by VRF / 32, and the value of the comparison signal Vcmp becomes equal to VRF * 7/32. The control circuit 820 determines that the value of the analog signal Sin is smaller than the value (VRF * 7/32) of the comparison signal Vcmp based on the comparison result from the comparator 815, and controls the control signal supplied to the switch sw0. Return to low level. Thereby, the value of the comparison signal Vcmp returns to VRF * 3/16. The comparison result means that the first bit of the value of the digital signal Sout is 0.

  By the above successive approximation, the control circuit 820 determines that the digital signal Sout corresponding to the analog signal is 00110.

  Thus, the ADC circuit 805 can perform AD conversion to generate a digital signal corresponding to the input analog signal.

  An example using a successive approximation ADC circuit as another AD conversion format has been described. The ADC circuit 805 is not limited to this successive approximation ADC circuit. For example, as other ADC circuits, various ADC circuits such as ramp signal comparison type, delta sigma type, pipeline type, and flash type can be used.

Ninth Embodiment
The imaging device 106 and the imaging device 100 described in each embodiment can be applied to various applications. For example, the imaging device 106 can be used to sense light such as infrared light, ultraviolet light, and X-rays as well as visible light. The imaging device 100 is typically represented by a digital camera, but is also applicable to camera-equipped mobile phones such as smartphones, surveillance cameras, game devices, and the like. Furthermore, the present invention can be applied to a medical device for performing an endoscope or blood vessel imaging, a beauty device for observing a skin or a scalp, and a video camera for imaging a sports or action moving image. The present invention is also applicable to traffic purpose cameras such as traffic monitoring and drive recorders, academic purpose cameras such as astronomical observation and sample observation, home appliances with cameras, machine vision and the like. In particular, machine vision is not limited to robots in factories etc., and can be used in agriculture and fishery.

  Further, the configuration of the imaging device shown in the above embodiment is an example, and the imaging device to which the present invention can be applied is not limited to the configuration shown in FIG. Also, the circuit configuration of each part of the imaging device is not limited to the configuration shown in each drawing.

  The present invention supplies a program that implements one or more functions of the above-described embodiments to a system or apparatus via a network or storage medium, and one or more processors in a computer of the system or apparatus read and execute the program. Can also be realized. It can also be implemented by a circuit (eg, an ASIC) that implements one or more functions.

  In addition, the said embodiment only shows the example of embodiment in the case of implementing this invention, and the technical scope of this invention should not be limitedly interpreted by these. That is, the present invention can be implemented in various forms without departing from the technical concept or the main features thereof.

10 first substrate 11 pixel unit 12 pixel block 20 second substrate 21 signal processing unit 100 imaging device 106 imaging device 803 signal line 804 MPX circuit 805 ADC circuit 806 PSAVE control unit

Claims (9)

A first substrate having a pixel array in which a plurality of pixels for performing photoelectric conversion are arranged in a matrix, and a circuit array in which a plurality of signal processing units for processing signals based on the photoelectric conversion are arranged in a matrix An imaging device in which two substrates are stacked,
The pixel array includes a pixel block formed by a plurality of pixels,
The signal processing unit and the corresponding pixel block are connected by a plurality of signal lines,
An image pickup device comprising: an addition circuit that adds the signals input from the plurality of signal lines during a synchronization; and a conversion circuit that converts the signal added by the addition circuit from analog to digital.   The imaging device according to claim 1, comprising a plurality of photoelectric conversion units for each of the pixels.   3. The image pickup device according to claim 1, wherein the signal processing unit further includes a selection unit which selects which signal line is to be connected from the plurality of signal lines to the conversion circuit. . The pixel array includes a plurality of pixels having color filters of different colors,
4. The signal processing apparatus according to claim 1, wherein the adding circuit adds signals corresponding to pixels which are included in the pixel block and which have color filters of the same color adjacent in the row direction or the column direction. An imaging device according to item 1.   The image pickup device according to any one of claims 1 to 4, wherein the addition circuit adds the signals by selecting two or more signal lines by the selection unit.   The image pickup device according to any one of claims 1 to 5, wherein the addition circuit includes a sample and hold circuit for each of the plurality of signal lines. The control circuit further includes a control unit for controlling a power saving operation on the conversion circuit,
The imaging according to any one of claims 1 to 6, wherein the control unit controls the conversion circuit to perform a power saving operation while the conversion circuit is not performing an analog-to-digital conversion operation. element.   8. The image pickup device according to claim 7, wherein the control unit controls a power saving operation of the conversion circuit based on an operation of adding the signals by the addition circuit. An imaging device according to any one of claims 1 to 8.
Acquisition means for acquiring a digital signal output from the conversion circuit from the imaging device;
Drive control means for controlling the drive of the image sensor;
The drive means at least
A first drive mode for acquiring, by the acquisition unit, a digital signal based on the signal added by the addition circuit;
An imaging apparatus comprising: a second drive mode for acquiring a digital signal based on a non-addition signal by the acquisition unit regardless of the addition circuit.

Images