JP2019068096A - Semiconductor device - Google Patents

Abstract

To provide a SiC semiconductor device having improved voltage withstand.SOLUTION: A semiconductor device includes: first depressions and second depressions which are formed away from each other on a surface of a SiC semiconductor layer; gate electrodes each embedded in the first depression via a gate insulation film; body regions each formed in a region along the first depression and the second depression on a surface part of the surface of the semiconductor layer to have parts which lie along lateral faces of the first depressions and are located closer to the surface side of the semiconductor layer than bottoms of the first depressions and have a part which lies under the second depression and is located closer to a rear face of the semiconductor layer than the bottom of the first depression; source regions each formed on the body region so as to contact the lateral face of the first depression; high-concentration regions each of which is formed in the body region in the region along the second depression and has an impurity concentration higher than an impurity concentration of the body region in a region located under the source region; and source electrodes each of which covers an insulation layer, the second depression, the body region and the source region above the surface of the semiconductor layer.SELECTED DRAWING: Figure 17

Description

  The present invention relates to a SiC semiconductor device.

In recent years, SiC semiconductor devices mainly used for systems in various power electronics fields such as motor control systems and power conversion systems have attracted attention.
Patent Document 1 discloses a p-type SiC substrate (collector layer), an n-type drift layer formed on the SiC substrate, a p-type base region formed on the drift layer, and an upper portion of the base region. Discloses a vertical IGBT including an n-type emitter region.

Patent Document 2 is formed in an n ⁺ -type SiC substrate, an n ⁻ -type base layer formed on a SiC substrate, a p-type body region formed in a surface layer portion of the base layer, and a surface layer portion of the body region Trench gate type MOSFET including a buried n ⁺ type source region, a gate trench penetrating from the surface of the base layer to the source region and the body region, and a gate electrode embedded in the gate trench through the gate insulating film It is disclosed.

JP, 2011-49267, A JP 2011-44688 A Unexamined-Japanese-Patent No. 2010-251517 JP, 2010-74051, A

  One embodiment of the present invention provides a SiC semiconductor device capable of improving the withstand voltage.

  One embodiment of the present invention has a semiconductor layer of a first conductivity type made of SiC, having a front surface and a back surface, a first recess formed on the surface of the semiconductor layer, and having a bottom portion and side surfaces, A second recess formed on the surface of the semiconductor layer at a distance from the recess, a gate insulating film formed along the bottom portion and the side surface of the first recess, and the gate insulating film. A gate electrode embedded in a first recess and a surface portion of the surface of the semiconductor layer are formed in a region along the first recess and the second recess, and a portion along the side surface of the first recess is the A portion located on the surface side of the semiconductor layer with respect to the bottom portion of the first recess and a portion located below the second recess is located on the back surface side of the semiconductor layer with respect to the bottom portion of the first recess Body region of second conductivity type A first conductivity type formed on the body region to be in contact with the side surface of the first recess in a region between the first recess and the second recess in the surface portion of the surface of the semiconductor layer Of the second conductivity type having an impurity concentration higher than that of the source region and the region along the second recess in the body region and higher than the impurity concentration of the region located below the source region in the body region A region, an insulating layer covering a portion of the source region and the gate electrode to expose the source region and the second recess above the surface of the semiconductor layer, and an upper surface of the surface of the semiconductor layer A semiconductor device is provided, comprising: the insulating layer; the second recess; and a source electrode covering the body region and the source region.

  According to this semiconductor device, the portion located below the second recess in the body region is located on the back surface side of the semiconductor layer with respect to the bottom of the first recess. Thus, the depletion layer can be spread from the portion located on the back surface side of the semiconductor layer with respect to the bottom of the first recess in the body region. As a result, it is possible to provide a SiC semiconductor device capable of improving the withstand voltage.

FIG. 1 is a schematic cross-sectional view of a SiC semiconductor device according to a first embodiment of the present invention. FIG. 2A illustrates theoretical characteristics of drain voltage (collector voltage) versus drain current (collector current) of a hybrid-MOS structure derived from characteristics of individually manufactured SiC-MOSFET and SiC-IGBT. Is a graph of FIG. 2B is a graph for explaining the actual characteristics of drain voltage (collector voltage) versus drain current (collector current) of the hybrid-MOS structure. FIG. 3 is a graph showing the actual pn junction rise voltage versus the characteristic on-resistance characteristic of the hybrid-MOS structure. FIG. 4 is a diagram for explaining the distribution of potential when the composition ratio of the collector region to the drain region is changed. FIG. 5 is a diagram for explaining the distribution of potential when the composition ratio of the collector region to the drain region is changed. FIG. 6 is a diagram for explaining the distribution of potential when the composition ratio of the collector region to the drain region is changed. FIG. 7 is a graph showing drain voltage (collector voltage) versus drain current (collector current) characteristics when the composition ratio of the collector region to the drain region is changed. FIG. 8 is a graph showing drain voltage (collector voltage) versus drain current (collector current) characteristics when the width of the drain region is changed. FIG. 9 is a graph for explaining the characteristics of the large current region in FIG. FIG. 10 is a schematic cross-sectional view of a SiC semiconductor device according to a second embodiment of the present invention. FIG. 11 is a diagram for illustrating the distribution of the potential of the SiC semiconductor device shown in FIG. FIG. 12 is a graph for illustrating the pn junction rising voltage versus the characteristic on resistance of the SiC semiconductor device shown in FIG. FIG. 13 is a schematic cross-sectional view of a SiC semiconductor device according to a third embodiment of the present invention. FIG. 14 is a diagram for illustrating distribution of potentials of the semiconductor device shown in FIG. FIG. 15 is a schematic cross-sectional view of a SiC semiconductor device according to a fourth embodiment of the present invention. FIG. 16 is a schematic cross-sectional view of a SiC semiconductor device according to a fifth embodiment of the present invention. FIG. 17 is a schematic cross-sectional view of a SiC semiconductor device according to a sixth embodiment of the present invention. FIG. 18 is a plan view for explaining one planar shape of the collector region. FIG. 19 is a plan view for explaining one planar shape of the collector region. FIG. 20 is a plan view for explaining one planar shape of the collector region. FIG. 21 is a plan view for explaining an arrangement example of the collector region and the drain region. FIG. 22 is a plan view for explaining an arrangement example of the collector region and the drain region.

Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings.
FIG. 1 is a schematic cross-sectional view of the SiC semiconductor device 1 according to the first embodiment of the present invention.
As shown in FIG. 1, SiC semiconductor device 1 includes an n ⁻ -type SiC semiconductor layer 10 having a front surface and a rear surface. In the surface portion of SiC semiconductor layer 10 of SiC semiconductor layer 10, a plurality of p-type body regions 12 constituting unit cell 11 are formed.

The p-type body region 12 is formed on the SiC semiconductor layer 10 at an interval, and an n-type source region 13 and ap ⁺ -type contact region 14 are formed in the inward region thereof. The n-type source region 13 is formed at a position spaced from the peripheral edge of the p-type body region 12. A region between the peripheral portion of the n-type source region 13 and the peripheral portion of the p-type body region 12 is a p-type channel region 15. The p ⁺ -type contact region 14 is formed in the inner region of the n-type source region 13 so as to penetrate the n-type source region 13. The p ⁺ -type contact region 14 has an impurity concentration higher than that of the p-type body region 12. The n-type source region 13 and the p ⁺ -type contact region 14 are both formed shallower than the p-type body region 12.

The back surface of the SiC semiconductor layer 10, an ^{n +} -type drain region 16 and ^{p +} -type collector region 17 are adjacent to each other, the ^{n +} -type drain region 16 and ^{p +} -type across the collector region 17 ^{n +} -type FS (Field A Stop (field stop) region 18 is formed. The back surface of the SiC semiconductor layer 10 is flush with the boundary of the n ⁺ -type drain region 16 and the p ⁺ -type collector region 17.

FS region 18 is formed with a uniform thickness so as to contact the upper end of n ⁺ -type drain region 16 and the upper end of p ⁺ -type collector region 17 with respect to the X-axis along the surface of SiC semiconductor layer 10. A region between the FS region 18 and the unit cell 11 (p-type body region 12) is an n ⁻ -type drift region 19. The Y-axis thickness Td of the n ⁻ -type drift region 19 is, for example, 10 μm to 100 μm (46 μm in the present embodiment) with respect to the Y-axis along the thickness direction of the SiC semiconductor layer 10.

The n ⁺ -type drain regions 16 are formed in regions immediately below the unit cells 11 (p-type body regions 12) adjacent to each other. The X-axis width Wd of the n ⁺ -type drain region 16 is, for example, 10 μm to 100 μm with respect to the X-axis along the surface of the SiC semiconductor layer 10. In the present embodiment, the upper end of the n ⁺ -type drain region 16 is located at the same depth as the upper end of the p ⁺ -type collector region 17 with respect to the Y-axis along the thickness direction of the SiC semiconductor layer 10.

The p ⁺ -type collector region 17 forms a pn junction with the SiC semiconductor layer 10. That is, a parasitic diode D is formed at the pn junction. The p ⁺ -type collector region 17 is formed to have a larger area than the n ⁺ -type drain region 16 in the X-axis along the surface of the SiC semiconductor layer 10. More specifically, in the X axis, the p ⁺ -type collector region 17 is formed to cover a region including at least two unit cells 11. The X-axis width Wc of the p ⁺ -type collector region 17 is, for example, 50 μm to 100 μm with respect to the X-axis along the surface of the SiC semiconductor layer 10. The X-axis width Wc of the p ⁺ -type collector region 17 is formed so as to satisfy X-axis width Wc> Y-axis thickness Td × 2 with respect to the Y-axis thickness Td of the n ⁻ -type drift region 19 Is preferred.

Such n ⁺ -type drain region 16 and p ⁺ -type collector region 17 can be formed by the following method. First, an n ⁺ -type SiC substrate is prepared. Next, SiC is epitaxially grown while implanting n-type impurities to form an n ⁻ -type SiC semiconductor layer 10 on the SiC substrate. Next, after forming the MOS structure which consists of p type body field 12, n type source field 13, gate insulating film 20 mentioned below, gate electrode 21, and source electrode 24 grade in SiC semiconductor layer 10, a SiC substrate becomes a SiC semiconductor Grind until layer 10 is exposed. Note that the SiC substrate may be removed by dry etching instead of grinding the SiC substrate.

Next, n-type impurities are selectively implanted on the back surface side of SiC semiconductor layer 10 to form FS region 18.
Next, an ion implantation mask having an opening selectively in a region where n ⁺ -type drain region 16 is to be formed on the back surface side of SiC semiconductor layer 10 is formed. An n-type impurity is implanted through the ion implantation mask. After the impurities are implanted, the ion implantation mask is removed.

Next, an ion implantation mask having an opening selectively in a region where p ⁺ -type collector region 17 is to be formed on the back surface side of SiC semiconductor layer 10 is formed. P-type impurities are implanted through the ion implantation mask. After the impurities are implanted, the ion implantation mask is removed.
Next, a laser annealing process is selectively performed on the region into which the n-type impurity and the p-type impurity are implanted. Thereby, the n-type impurity and the p-type impurity are activated to form the n ⁺ -type drain region 16 and the p ⁺ -type collector region 17.

Since the SiC semiconductor layer 10 has a density higher than that of the semiconductor layer made of Si, it has the characteristic that the impurity is difficult to diffuse. Therefore, the thickness of the n-type impurity and the p-type impurity can be easily controlled by adjusting the impurity implantation condition and the annealing treatment condition by utilizing this characteristic. Thereby, the n ⁺ -type drain region 16 and the p ⁺ -type collector region 17 can be accurately formed.

  Referring again to FIG. 1, a plurality of gate electrodes 21 facing p-type channel region 15 with gate insulating film 20 interposed therebetween are formed on SiC semiconductor layer 10. The gate insulating film 20 may be made of, for example, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a hafnium oxide film, an alumina film, a tantalum oxide film, or the like. Also, the gate electrode 21 may be made of, for example, polysilicon in which an impurity is injected to reduce resistance.

  Each gate electrode 21 faces a region across the SiC semiconductor layer 10 outside the p-type body region 12, the p-type body region 12, and the n-type source region 13. In addition, gate electrode 21 includes an overlap portion protruding from the boundary between n-type source region 13 and p-type body region 12 toward n-type source region 13. An insulating film 22 is formed on the SiC semiconductor layer 10 so as to cover the gate electrode 21.

In the insulating film 22, a contact hole 23 for selectively exposing a part of the n-type source region 13 and the p ⁺ -type contact region 14 is formed. The source electrode 24 is formed on the insulating film 22.
The source electrode 24 enters the contact hole 23 from the surface of the insulating film 22, and forms an ohmic contact between the n-type source region 13 and the p ⁺ -type contact region 14 in the contact hole 23. On the other hand, a drain electrode 25 is formed on the back surface side of the SiC semiconductor layer 10. The drain electrode 25 forms an ohmic contact between the n ⁺ -type drain region 16 and the p ⁺ -type collector region 17.

According to this configuration, the SiC semiconductor device 1 is a hybrid-MOS (Hybrid (Hybrid) in which a SiC-MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and a SiC-IGBT (Insulated Gate Bipolar Semiconductor) are integrated in the same SiC semiconductor layer 10. -It has a Metal Oxide Semiconductor) structure and a planar gate structure.
More specifically, the SiC-MOSFET is formed of the n-type source region 13, the n ⁺ -type drain region 16, and the gate electrode 21, and the SiC-IGBT is formed of the n-type source region 13, the p ⁺ -type collector region 17 and the gate electrode 21. That is, the SiC-MOSFET and the SiC-IGBT are connected in parallel via the SiC semiconductor layer 10. When operating as a SiC-IGBT, the n-type source region 13 (source electrode 24) functions as an n-type emitter region (emitter electrode), and the n ^-- type drift region 19 functions as an n ^-- type base region.

Next, theoretical electrical characteristics and actual electrical characteristics of the hybrid-MOS structure will be described in light of the electrical characteristics when the SiC-MOSFET and the SiC-IGBT are separately manufactured.
FIG. 2A illustrates theoretical characteristics of drain voltage (collector voltage) versus drain current (collector current) of a hybrid-MOS structure derived from characteristics of individually manufactured SiC-MOSFET and SiC-IGBT. Is a graph of The drain voltage (collector voltage) means a voltage applied to the drain electrode 25 with the source electrode 24 as a reference voltage (for example, 0 V).

  The SiC-MOSFET is effective as an element mainly used in a low withstand voltage region (for example, 5 kV or less). In the case of the SiC-MOSFET, as can be understood from the straight line A1 indicated by the broken line in FIG. 2A, the drain current rises from the drain voltage of 0 V and then linearly increases with the increase of the drain voltage. Therefore, in the SiC-MOSFET, it is possible to exhibit the characteristics of a good small current region. On the other hand, since the drain current increases linearly with the increase of the drain voltage, when using the SiC-MOSFET in a large current region, the area of the SiC semiconductor layer 10 is expanded according to the increase of the applied drain voltage. Must.

  On the other hand, SiC-IGBT is effective as an element used mainly in a high breakdown voltage region (for example, 10 kV or more). That is, in the case of the SiC-IGBT, since it has the conductivity modulation characteristics of the bipolar transistor, large current control is possible with high withstand voltage. As understood from the curve A2 indicated by the broken line in FIG. 2A, in the case of the SiC-IGBT, the collector current exhibits a sharp rise characteristic when the collector voltage exceeds about 2.7V. Therefore, in the SiC-IGBT, good large current region characteristics can be exhibited without expanding the area of the SiC semiconductor layer 10.

On the other hand, since SiC is a wide gap semiconductor, it has a higher pn barrier than Si. Therefore, when using a SiC-IGBT in a small current region, a high pn junction rise voltage (about 2.7 V) is required. That is, to turn on the parasitic diode D (see FIG. 1) formed between the p ⁺ -type collector region 17 and the SiC semiconductor layer 10, a pn junction rise voltage of about 2.7 V is required.

  From these, it is understood that, by integrating the SiC-MOSFET and the SiC-IGBT in the same SiC semiconductor layer 10, in theory, a wide operation range can be realized from the low breakdown voltage region to the high breakdown voltage region. That is, it can be seen that it is possible to provide a semiconductor device capable of realizing MOSFET (unipolar) operation in a small current region and IGBT (bipolar) operation in a large current region while being usable as a high voltage element. This theoretical characteristic is the curve A3 indicated by the solid line in FIG. 2A.

  Referring to the theoretical curve A3, it can be seen that, at 0 V to about 3 V, the SiC-MOSFET is turned on and good low current region characteristics are obtained. Then, the voltage applied to the pn junction is set to a voltage (about 3 V or more) required to raise the pn junction or more (about 3 V or more), whereby the SiC-IGBT is turned on and the characteristics of a good large current region It can be seen that

  FIG. 2B is a graph for explaining the actual characteristics of drain voltage (collector voltage) versus drain current (collector current) of the hybrid-MOS structure. The drain voltage (collector voltage) means a voltage applied to the drain electrode 25 with the source electrode 24 as a reference voltage (for example, 0 V). In FIG. 2B, the straight line A1 and the curve A2 are continuously indicated by broken lines.

In the curve A4 and the curve A5 indicated by the solid line in FIG. 2B, the X-axis width Wd of the n ⁺ -type drain region 16 and the X-axis width Wc of the p ⁺ -type collector region 17 are X-axis width Wd + X-axis width Wc < The characteristic of the SiC semiconductor device formed so that a relational expression of <12 μm is satisfied is shown.
If curve A4 is referred to, good small current characteristics (good on-resistance value) are shown, but a very high pn junction rise voltage (about 19 V) is required for transition from the small current region to the large current region. I know that there is. On the other hand, referring to curve A5, it can be seen that although the pn junction rise voltage required for transition from the small current region to the large current region is improved, the small current characteristics are degraded compared to curve A4. .

As understood from FIG. 2B, the characteristics of the SiC semiconductor device fluctuate with the respective X-axis widths Wd and Wc of the n ⁺ -type drain region 16 and the p ⁺ -type collector region 17. Therefore, it is understood that it is necessary to devise the formation of the n ⁺ -type drain region 16 and the p ⁺ -type collector region 17 in order to make the curves A4 and A5 approach the theoretical curve A3 shown in FIG. 2A. In this regard, the inventors have found that the characteristics of the small current region and the characteristics of the large current region are in a trade-off relationship, as shown in FIG.

FIG. 3 is a graph showing the actual pn junction rise voltage versus the characteristic on-resistance characteristic of the hybrid-MOS structure. The characteristic on-resistance is defined by the slope of the drain current-drain voltage curve when the drain voltage is 0V.
As described in FIG. 2B, the n ⁺ -type drain region 16 and the p ⁺ -type collector region 17 satisfy the relational expression of X-axis width Wd + X-axis width Wc << 12 μm with respect to each X-axis width Wd and Wc. That is, the X-axis width Wc of the p ⁺ -type collector region 17 satisfies the relational expression of X-axis width Wc << 2 × Y-axis thickness Td with respect to the Y-axis thickness Td of the n ⁻ -type drift region 19 Is formed. A curve A6 indicated by a solid line in FIG. 3 is an actual characteristic in the case where the relational expression of X axis width Wc << 2 × Y axis thickness Td is satisfied.

Referring to the curve A6, it can be seen that when the composition ratio of the n ⁺ -type drain region 16 to the p ⁺ -type collector region 17 is set to be extremely large, the characteristics thereof approach the SiC-MOSFET. That is, although it is possible to obtain a good characteristic on-resistance (a good small current region characteristic), a very high voltage is required at the time of transition to a large current region.
On the other hand, when the composition ratio of the p ⁺ -type collector region 17 to the n ⁺ -type drain region 16 is set to be extremely large, it can be seen that the characteristics approach SiC-IGBT. That is, although the pn junction can be raised at a relatively low drain voltage, the characteristic on-resistance is significantly increased (small current characteristics are reduced).

The point P1 in the curve A6 corresponds to the curve A4 in the graph of FIG. 2B, the value of the characteristic on resistance is about 20 mΩ · cm ² , and the drain voltage required for the rising voltage of the pn junction is about 19V. On the other hand, a point P2 in the curve A6 corresponds to the curve A5 in the graph of FIG. 2B, the drain voltage at the rise of the pn junction is about 5 V, and the value of the characteristic on resistance is about 40 mΩ · cm ² .

As understood from the curve A6, the characteristics of the small current region and the characteristics of the large current region are in a trade-off relationship. Even if the composition ratio of the p ⁺ -type collector region 17 to the n ⁺ -type drain region 16 is changed within the range satisfying the relational expression of X-axis width Wc << 2 × Y-axis thickness Td, the characteristic is Varying in the direction of the point P1 on the curve A6 or in the direction of the point P2 does not lead to the improvement of the substantial trade-off relationship.

A curve A7 indicated by a broken line in FIG. 3 is an actual characteristic when the X-axis width Wc of the p ⁺ -type collector region 17 satisfies the relational expression of X-axis width Wc> 2 × Y-axis thickness Td. Referring to the curve A7, it can be seen that the tradeoff relationship is substantially improved with respect to the curve A6. That is, the curve A7 is a straight line A8 indicating the lower limit (= about 2.7 V) of the pn junction rise voltage (SiC-IGBT) and the lower limit (= SiC-MOSFET) of the characteristic on resistance (SiC-MOSFET) as compared to the curve A6. It approaches to the straight line A9 which shows about 18 mΩ · cm ² ).

If the value of pn junction rising voltage and the value of characteristic ON resistance can be brought close to the point P3 at which the straight line A8 and the straight line A9 cross on this curve A7, excellent low current region characteristics and high current region characteristics are achieved. I know what I can do.
The inventors conducted simulations on each SiC semiconductor device by preparing a plurality of SiC semiconductor devices in which the composition ratio of the p ⁺ -type collector region 17 to the n ⁺ -type drain region 16 is sequentially increased, paying attention to this point .

FIGS. 4 to 6 are diagrams for explaining the distribution of potential when the composition ratio of the p ⁺ -type collector region 17 to the n ⁺ -type drain region 16 is changed. 4 to 6 omit the configuration other than the main configuration for the convenience of description.
The X-axis width Wc of the p ⁺ -type collector region 17 in FIG. 4 is 10 μm. The X-axis width Wc of the p ⁺ -type collector region 17 in FIG. 5 is 50 μm. The X-axis width Wc of the p ⁺ -type collector region 17 in FIG. 6 is 100 μm. The X-axis width Wd of each of the n ⁺ -type drain regions 16 in FIGS. 4 to 6 is 10 μm, and the Y-axis thickness Td of each of the n ⁻ -type drift regions 19 is 46 μm.

4 to 6 show distributions of potentials when a voltage of about 3 V is applied to the drain electrode 25 with the source electrode 24 as a reference (= 0 V). As shown in FIGS. 4 to 6, the potential equipotential planes are distributed so as to be gradually higher from the source electrode 24 to the drain electrode 25. Then, equipotential surfaces of relatively high potential are distributed concentrically around the n ⁺ -type drain region 16.

In FIG. 4, an equipotential surface of about 2.5 V is distributed at the upper end of the p ⁺ -type collector region 17. On the other hand, in FIG. 5, equipotential surfaces of about 1 V to 2 V are widely distributed at the upper end of the p ⁺ -type collector region 17. Therefore, in FIG. 5, it can be seen that the potential difference between the p ⁺ -type collector region 17 and the equipotential surface is large. Furthermore, in FIG. 6, equipotential surfaces of about 0.5 V to 2 V are more widely distributed at the upper end of the p ⁺ -type collector region 17. Therefore, it can be seen in FIG. 6 that the potential difference between the p ⁺ -type collector region 17 and the equipotential surface is larger compared to FIGS. 4 and 5.

A graph reflecting the results of these simulations is shown in FIG. FIG. 7 is a graph showing drain voltage (collector voltage) versus drain current (collector current) characteristics when the composition ratio of the p ⁺ -type collector region 17 to the n ⁺ -type drain region 16 is changed.
A curve L1 is a curve when the X-axis width Wc of the p ⁺ -type collector region 17 is 10 μm (see FIG. 4), and a curve L2 is a curve when the X-axis width Wc of the p ⁺ -type collector region 17 is 20 μm The curve L3 is the curve when the X axis width Wc of the p ⁺ type collector region 17 is 50 μm (see FIG. 5), and the curve L4 is the one when the X axis width Wc of the p ⁺ type collector region 17 is 100 μm (FIG. Curve).

As shown in the graph of FIG. 7, as the X-axis width Wc of the p ⁺ -type collector region 17 is increased, the drain voltage necessary for transition to the large current region is decreased.
In the structure shown in FIG. 4, an equipotential surface is distributed at the upper end of the p ⁺ -type collector region 17 with almost no difference from the drain voltage applied to the n ⁺ -type drain region 16. In this case, since the n ⁺ -type drain region 16 and the p ⁺ -type collector region 17 have the same potential, the pn junction rise voltage between the p ⁺ -type collector region 17 and the equipotential surface is obtained even if the drain voltage is increased. A potential difference of about 2.7 V or more is unlikely to occur.

Therefore, the drain voltage has to be increased until the potential difference between the p ⁺ -type collector region 17 and the equipotential surface becomes equal to or higher than the pn junction rise voltage, and the transition from the small current region to the large current region is very A high voltage is required. As shown in FIG. 7, in the structure of FIG. 4, when not to increase the drain voltage to approximately 19V, the potential difference pn junction rise between the p ⁺ -type collector region 17 and the p ⁺ -type collector region 17 covering equipotential surface It turns out that it does not become more than voltage.

On the other hand, with the structure shown in FIG. 6, a relatively low equipotential surface can be widely distributed at the upper end of the p ⁺ -type collector region 17. In this case, since the potential difference between the p ⁺ -type collector region 17 and the equipotential surface can be brought close to the pn junction rising voltage, the pn junction can be generated by a relatively small drain voltage (3.0 V to 3.5 V). Part (parasitic diode D) can be turned on. Therefore, it is rapidly transitioning from the small current region to the large current region.

Drain voltage (collector voltage) vs. drain current (collector) when X-axis width Wd of n ⁺ -type drain region 16 is changed from 10 μm to 100 μm while maintaining X-axis width Wc of p ⁺ -type collector region 17 at 100 μm It is the graphs shown in FIGS. 8 and 9 that the current characteristics were examined.
FIG. 8 is a graph showing drain voltage (collector voltage) versus drain current (collector current) characteristics when the X-axis width Wd of the n ⁺ -type drain region 16 is changed. FIG. 9 is a graph for explaining the characteristics of the large current region in FIG.

A curved line L5 indicated by a solid line in each graph of FIGS. 8 and 9 is a curve when the X axis width Wc of the p ⁺ -type collector region 17 is 100 μm and the X axis width Wd of the n ⁺ -type drain region 16 is 100 μm. In each of the graphs of FIGS. 8 and 9, the curves L1 and L4 shown by the graph of FIG. 7 are indicated by broken lines.
From the graph of FIG. 8, the drain current in the small current region is obtained by widening the X-axis width Wd of the n ⁺ -type drain region 16 and relatively reducing the X-axis width Wc of the p ⁺ -type collector region 17. It has been confirmed that the (collector current) increases. In other words, by relatively increasing the composition ratio of the X-axis width Wd of the n ⁺ -type drain region 16, the value of the characteristic on-resistance decreases, so the drain current (collector current) in the small current region increases. That was confirmed. Further, as shown in FIG. 9, it was confirmed that the characteristics of the large current region hardly change.

From this result, it is possible to relatively reduce the component ratio of the X-axis width Wc of the p ⁺ -type collector region 17 to maintain a good pn junction rise voltage (3.0 V to 3.5 V) while maintaining a small current region. It has been confirmed that the characteristics of can be improved. Therefore, it can be seen that the characteristics of the small current region can be improved by forming the X-axis width Wd of the n ⁺ -type drain region 16 to be equal to or larger than the X-axis width Wc of the p ⁺ -type collector region 17.

As described above, according to SiC semiconductor device 1, p ⁺ type collector region 17 is formed to cover the region including at least two unit cells 11 along the X axis along the surface of SiC semiconductor layer 10. A relatively low equipotential surface can be widely distributed at the upper end of the p ⁺ -type collector region 17.
From another viewpoint, the X-axis width Wc along the surface of the SiC semiconductor layer 10 of the p ⁺ -type collector region 17 and the Y-axis thickness Td along the thickness direction of the SiC semiconductor layer 10 of the n ⁻ -type drift region 19 By making the value more than twice as large, a relatively low equipotential surface can be widely distributed at the upper end of the p ⁺ -type collector region 17.

In this case, since the potential difference between the p ⁺ -type collector region 17 and the equipotential surface can be brought close to the pn junction rising voltage, as shown in FIG. 7, the pn junction is increased by a relatively small increase in drain voltage. Part (parasitic diode D) can be turned on. As a result, the transition from the small current region to the large current region can be made by the relatively small drain voltage, and the trade-off relationship between the characteristics of the small current region and the characteristics of the large current region can be improved. As a result, it is possible to provide the SiC semiconductor device 1 excellent in any of the characteristics of the small current region and the characteristics of the large current region.

Further, as shown in FIGS. 8 and 9, a large current region is formed by forming the n ⁺ -type drain region 16 with an X-axis width Wd equal to or greater than the X-axis width Wc of the p ⁺ -type collector region 17. The characteristics of the small current region can be improved while maintaining the characteristics of
Further, as shown in FIG. 1, the FS region 18 is formed so as to straddle the n ⁺ -type drain region 16 and the p ⁺ -type collector region 17. As a result, it is possible to provide the FS (Field Stop: field stop) type SiC semiconductor device 1. A non-punch through (NPT) type SiC semiconductor device not having the FS region 18 is known as to the FS type SiC semiconductor device 1.

In the case of an NPT-type SiC semiconductor device, the SiC semiconductor layer prevents the depletion layer generated from the interface between p-type body region 12 and n ⁻ -type drift region 19 from reaching the lower surface of SiC semiconductor layer 10 and punching through. 10 should be made relatively thick. On the other hand, in the case of the FS type SiC semiconductor device 1, since the spread of the depletion layer can be blocked by the FS region 18, the occurrence of punch through can be suppressed. Therefore, according to FS type SiC semiconductor device 1, compared with NPT type SiC semiconductor device, SiC semiconductor layer 10 can be made thin.

FIG. 10 is a schematic cross-sectional view of the SiC semiconductor device 2 according to the second embodiment of the present invention.
The SiC semiconductor device 2 differs from the above-described SiC semiconductor device 1 in that a p ⁺ -type collector region 31 is formed instead of the p ⁺ -type collector region 17. The other configuration is the same as that of the above-described SiC semiconductor device 1. In FIG. 10, parts corresponding to the parts shown in FIG. 1 described above are given the same reference numerals, and descriptions thereof will be omitted.

As shown in FIG. 10, a plurality of p ⁺ -type collector regions 31 and n ⁺ -type drain regions 16 are formed adjacent to each other on the back surface side of the SiC semiconductor layer 10. Each p ⁺ -type collector region 31 is formed in a region directly below each unit cell 11 (p-type body region 12), and has a one-to-one correspondence with each unit cell 11 with the n ⁻ -type drift region 19 interposed therebetween. Are facing each other. With respect to the X axis along the surface of SiC semiconductor layer 10, the X axis width Wc of p ⁺ -type collector region 31 is, for example, 10 μm.

FIG. 10 shows an example in which the X-axis width Wc of the p ⁺ -type collector region 31 is formed narrower than the width of the p-type body region 12. p ⁺ -type collector region 31 of the X-axis width Wc ^{(n +} -type drain constituent ratio of ^{p +} -type collector region 31 to the area 16), n ^- can be changed according to the Y JikuAtsu of Td type drift region 19. Therefore, when the Y-axis thickness Td of the n ⁻ -type drift region 19 is formed thick, the p ⁺ -type collector region 31 may be formed wider than the width of the p-type body region 12.

The upper end of the p ⁺ -type collector region 31 is located closer to the surface side of the SiC semiconductor layer 10 than the upper end of the n ⁺ -type drain region 16 with respect to the Y-axis along the thickness direction of the SiC semiconductor layer 10. The Y-axis thickness Dp from the upper end of the n ⁺ -type drain region 16 to the upper end of the p ⁺ -type collector region 31 is, for example, 0 μm to 10 μm (0 μm <Y-axis thickness Dp ≦ 10 μm). The FS region 18 in the present embodiment is formed along the upper end and the side portion of the p ⁺ -type collector region 31 and the upper end of the n ⁺ -type drain region 16.

Such p ⁺ -type collector region 31 can be formed by the same method as that described in the first embodiment described above. That is, the p ⁺ -type collector region 31 is formed by adjusting the implantation conditions (eg, doping energy, dose amount, etc.) and annealing conditions (eg, annealing temperature, time, etc.) when implanting the p-type impurity. it can.
When the distribution of the potential of the SiC semiconductor device 2 was examined by the same method as in FIGS. 4 to 6 described above, the result shown in FIG. 11 was obtained. FIG. 11 is a diagram for explaining the distribution of the potential of SiC semiconductor device 2 shown in FIG. Note that FIG. 11 shows an example in which the Y-axis thickness Dp from the upper end of the n ⁺ -type drain region 16 to the upper end of the p ⁺ -type collector region 31 is 10 μm.

As shown in FIG. 11, the upper end of p ⁺ -type collector region 31 is located closer to the surface of SiC semiconductor layer 10 than the upper end of n ⁺ -type drain region 16, so it is relatively expanded from n ⁺ -type drain region 16. Can be suppressed from reaching the upper end of the p ⁺ -type collector region 31.
Then, at the upper end of the p ⁺ -type collector region 31, a relatively low equipotential surface is distributed. More specifically, an equipotential surface of 1.5 V to 2 V is distributed at the upper end of the p ⁺ -type collector region 31. Therefore, as compared with the structure of FIG. 4 described above, it can be seen the potential difference between the equipotential surface over the p ⁺ -type collector region 17 and the p ⁺ -type collector region 17 is large.

When the relationship between the pn junction rise voltage and the characteristic on resistance in the case of changing the Y-axis thickness Dp from the upper end of the n ⁺ -type drain region 16 to the upper end of the p ⁺ -type collector region 31 is examined, FIG. The results shown are obtained. FIG. 12 is a graph for illustrating the pn junction rising voltage versus the characteristic on resistance of the SiC semiconductor device 2 shown in FIG.
The graph of FIG. 12 shows the results of sequentially changing the Y-axis thickness Dp from the upper end of the n ⁺ -type drain region 16 to the upper end of the p ⁺ -type collector region 31 to 0 μm, 2 μm, 4 μm, 6 μm, 8 μm, 10 μm. ing.

As shown in the graph of FIG. 12, regarding the SiC-IGBT, the lower limit value of the pn junction rise voltage does not change, but as the Y-axis thickness Dp becomes thicker, the lower limit value of the characteristic on resistance of the SiC-MOSFET becomes It could be confirmed that it would go down.
As described above, according to the SiC semiconductor device 2, since the upper end of the p ⁺ -type collector region 31 is positioned on the surface side of the semiconductor layer than the upper end of the n ⁺ -type drain region 16, n ⁺ -type drain It is possible to prevent the equipotential surface extending from the region 16 from reaching the upper end of the p ⁺ -type collector region 31. Thus, p ⁺ -type simultaneously relatively high equipotential surfaces to the collector region 31 can be prevented from being distributed, it is possible to distribute the relatively low equipotential surface to the p ⁺ -type collector region 31. In this case, since the potential difference between the p ⁺ -type collector region 31 and the equipotential surface can be brought close to the pn junction rising voltage, the pn junction (parasitic diode D) can be It can be turned on.

Furthermore, by forming the thickness from the upper end of n ⁺ -type drain region 16 to the upper end of p ⁺ -type collector region 31 thick, n ⁺ -type drain region 16 and p ⁺ -type collector region 31 are formed with the same thickness. The on-resistance characteristic can be improved more than in the case.
Here, the n ⁻ -type drift region 19 functions as a breakdown voltage maintaining layer for maintaining the device breakdown voltage (that is, the breakdown voltage of the SiC semiconductor device 2). Therefore, when the Y-axis thickness Dp is formed large, the Y-axis thickness Td of the n ⁻ -type drift region 19 is reduced, which may make it difficult to exhibit the device breakdown voltage which is originally possessed. Then, the inventors found out the SiC semiconductor device 3 shown in FIG.

FIG. 13 is a schematic cross-sectional view of a SiC semiconductor device 3 according to a third embodiment of the present invention.
The point where SiC semiconductor device 3 differs from SiC semiconductor device 1 described above is that p ⁺ type collector region 32 is formed instead of p ⁺ type collector region 17, and the present invention is applied to the back surface portion of SiC semiconductor layer 10. Insulating film 33 is formed as an example of the insulating layer. The other configuration is the same as that of the above-described SiC semiconductor device 1. In FIG. 13, parts corresponding to the parts shown in FIG. 1 described above are given the same reference numerals, and descriptions thereof will be omitted.

As shown in FIG. 13, p ⁺ -type collector regions 32 and n ⁺ -type drain regions 16 are alternately formed spaced apart from each other on the back surface portion of SiC semiconductor layer 10.
The p ⁺ -type collector region 32 is formed in the region directly below the unit cell 11 (p-type body region 12), and is opposed to each unit cell 11 in a one-to-one correspondence relationship with the n ⁻ -type drift region 19 interposed therebetween. doing. The X-axis width Wc of the p ⁺ -type collector region 32 in the present embodiment is, for example, 10 μm.

FIG. 13 shows an example in which the X-axis width Wc of the p ⁺ -type collector region 32 is narrower than the width of the p-type body region 12. p ⁺ -type collector region 32 of the X-axis width Wc (composition ratio of the ^{n +} -type drain region 16 ^{p +} -type collector region 32 against) is, n ^- can be changed according to the Y JikuAtsu of Td type drift region 19. Therefore, when Y-axis thickness Td of n ⁻ -type drift region 19 is formed thick, p ⁺ -type collector region 32 may be formed wider than the width of p-type body region 12.

On the other hand, the respective n ⁺ -type drain regions 16 are formed in regions immediately below the unit cells 11 (p-type body regions 12) adjacent to each other. The X-axis width Wd of the n ⁺ -type drain region 16 in the present embodiment is, for example, 10 μm. Further, the upper end of the n ⁺ -type drain region 16 is located at the same depth as the upper end of the p ⁺ -type collector region 32. An FS region 18 is formed to cover the upper ends of the n ⁺ -type drain region 16 and the p ⁺ -type collector region 32.

An insulating film 33 buried in the isolation trench 34 is formed between the n ⁺ -type drain region 16 and the p ⁺ -type collector region 32 with respect to the Y-axis along the thickness direction of the SiC semiconductor layer 10. The isolation trench 34 is formed to dig the SiC semiconductor layer 10 from the back surface side toward the front surface side with respect to the Y axis. The isolation trench 34 is formed deeper than the n ⁺ -type drain region 16 and the p ⁺ -type collector region 32. The Y-axis depth Dt between the upper end of the n ⁺ -type drain region 16 and the upper end of the isolation trench 34 is, for example, 0 μm to 15 μm (0 μm <Y-axis depth Dt ≦ 15 μm. In this embodiment, 5 μm). On the other hand, isolation trench 34 is formed narrower than X-axis width Wc of p ⁺ -type collector region 32 and X-axis width Wd of n ⁺ -type drain region 16 with respect to the X-axis along the surface of SiC semiconductor layer 10. ing.

The insulating film 33 is preferably made of an insulating material having a relative dielectric constant lower than that of SiC, and SiO ₂ can be exemplified as the insulating material. The insulating film 33 is formed to have the same thickness as the depth of the isolation trench 34.
Such an insulating film 33 can be formed by the following method. That is, after the n ⁺ -type drain region 16 and the p ⁺ -type collector region 32 are formed by the method described in the first embodiment, the hard mask having an opening selectively in the region where the insulating film 33 is to be formed is SiC. It is formed on the back surface of the semiconductor layer 10.

  Next, by etching through the hard mask, the isolation trench 34 is formed by digging the SiC semiconductor layer 10 from the back surface side toward the front surface side. Next, insulating film 33 is formed to backfill isolation trench 34 and cover the back surface of SiC semiconductor layer 10, for example, by the CVD method. Next, unnecessary portions of the insulating film 33 are removed by etch back. Thereby, the insulating film 33 embedded in the isolation trench 34 is obtained. Instead of such an insulating film 33, a high resistance layer may be employed.

  In a semiconductor layer using SiC, it is known that due to the presence of point defects (lattice defects) having a predetermined density, a level which does not originally exist in the forbidden band between the conduction band and the valence band is known. Such levels are generally referred to as "deep levels". A deep level functions as a capture center (carrier trap) for capturing carriers, and therefore, a region where the point defect (lattice defect) density is relatively high becomes high in resistance.

The high resistance layer is a high resistance region by the introduction of such deep levels. In the high resistance layer, point defects (lattice defects) of a predetermined density are formed in the high resistance layer by implantation of ions or the like described later, whereby deep levels are formed. The deep level in the high resistance layer is the mid gap (that is, the energy between the minimum energy of the conduction band and the maximum energy of the valence band) than the level formed by the dopant in the n ⁻ -type drift region 19 It is a level close to The density of deep levels (the density of point defects) in the high resistance layer is preferably equal to (similar to) or higher than the impurity (donor) density in the n ⁻ -type drift region 19.

Such a high resistance layer can be formed by the following method. That is, after the n ⁺ -type drain region 16 and the p ⁺ -type collector region 32 are formed by the method described in the first embodiment, the mask having an opening selectively in the region where the high resistance layer is to be formed is SiC. It is formed on the back surface of the semiconductor layer 10. Next, ion irradiation or electron beam irradiation is performed.
In the case of ion irradiation, light element ions are implanted into the SiC semiconductor layer 10 through the mask. Examples of light element ions include hydrogen ions (protons), helium ions, and boron ions. Light element ions can be implanted at a deeper position than the n ⁺ -type drain region 16 or the like into the SiC semiconductor layer 10 having a density higher than that of the Si semiconductor layer. Thus, a high resistance layer having a predetermined Y-axis depth Dt (0 μm <Y-axis depth Dt ≦ 15 μm, in this embodiment 5 μm) can be easily formed.

On the other hand, when forming a high resistance layer by electron beam irradiation, the electron beam is irradiated to the SiC semiconductor layer 10 through a mask. The conditions of the electron beam irradiation vary depending on the depth of the high resistance layer to be formed. For example, the irradiation energy is 100 keV to 600 keV, and the electron beam irradiation dose is 1 × 10 ¹⁵ cm ⁻² to 1 × it may be 10 ¹⁸ cm ^-2. The irradiation of the electron beam may be one-step irradiation which is performed only once, or may be multi-step irradiation which is performed plural times.

  Of course, if the high resistance layer can be formed to the Y-axis depth Dt, p-type impurities (boron, aluminum, etc.) or n-type impurities (phosphorus, arsenic, etc.) instead of ion irradiation or electron beam irradiation. May be implanted into the SiC semiconductor layer 10. In this case, the annealing process is performed to such an extent that it is not activated (for example, the activation rate is less than 1%). When the impurity is not activated, the region of the SiC semiconductor layer 10 into which the impurity is implanted becomes high-resistance SiC.

When the potential of the SiC semiconductor device 3 was examined in the same manner as in FIGS. 4 to 6 described above, the result shown in FIG. 14 was obtained. FIG. 14 is a diagram for illustrating the distribution of the potential of SiC semiconductor device 3 shown in FIG.
As shown in FIG. 14, by forming the insulating film 33 (high resistance layer) between the n ⁺ -type drain region 16 and the p ⁺ -type collector region 32, it spreads concentrically from the n ⁺ -type drain region 16. It has been confirmed that a relatively high equipotential surface can be blocked by the insulating film 33 (high resistance layer).

Further, since the equipotential surface extending from the n ⁺ type drain region 16 can be blocked by the insulating film 33 (high resistance layer), a relatively low equipotential surface is distributed at the upper end of the p ⁺ type collector region 32 I know that. More specifically, an equipotential surface of 1.5 V to 2 V is distributed at the upper end of the p ⁺ -type collector region 32. Therefore, as compared with the structure of FIG. 4 described above, it can be seen the potential difference between the equipotential surface over the p ⁺ -type collector region 17 and the p ⁺ -type collector region 17 is large. From this experimental result, it has been confirmed that the SiC semiconductor device 3 can achieve the same electrical characteristics as the above-described SiC semiconductor device 2.

As described above, according to SiC semiconductor device 3, since insulating film 33 (high resistance layer) is formed between n ⁺ -type drain region 16 and p ⁺ -type collector region 32, n ⁺ -type drain region A relatively high equipotential surface extending from 16 can be blocked by the insulating film 33 (high resistance layer). Thus, p ⁺ -type simultaneously relatively high equipotential surfaces to the collector region 32 can be prevented from being distributed, it is possible to distribute the relatively low equipotential surface to the p ⁺ -type collector region 32.

In this case, since the potential difference between the p ⁺ -type collector region 32 and the equipotential surface can be brought close to the pn junction rising voltage, the pn junction (parasitic diode D) can be formed by a relatively small increase in drain voltage. It can be turned on. As a result, since it is possible to shift from the small current region to the large current region, the trade-off relation between the characteristics of the small current region and the characteristics of the large current region can be improved. As a result, it is possible to provide the SiC semiconductor device 3 excellent in any of the characteristics of the small current region and the characteristics of the large current region.

Furthermore, unlike the above-described SiC semiconductor device 2, Y-axis thickness Td of n ⁻ type drift region 19 between p ⁺ type collector region 32 and p type body region 12 is equal to n ⁺ type drain region 16 and p type body region. Since the thickness does not become smaller than the thickness of the n ⁻ -type drift region 19 between 12, it is possible to effectively suppress the decrease in the device withstand voltage.
FIG. 15 is a schematic cross-sectional view of a SiC semiconductor device 4 according to a fourth embodiment of the present invention.

SiC semiconductor device 4 differs from SiC semiconductor device 1 described above in that p ⁺ -type contact region 14 is not formed and p-type column region 35 is formed below p-type body region 12. It is. The other configuration is the same as that of the above-described SiC semiconductor device 1. In FIG. 15, the parts corresponding to the parts shown in FIG. 1 are given the same reference numerals, and the description will be omitted.

The p-type column region 35 is formed in the inner region of the p-type body region 12 so as to be continuous with the p-type body region 12. More specifically, p-type column region 35 is formed to extend from the bottom of p-type body region 12 toward n ⁻ -type drift region 19 with respect to the Y axis along the thickness direction of SiC semiconductor layer 10. The pn junction is formed between the n ⁻ drift region 19 and the n ⁻ drift region 19. The bottom of the p-type column region 35 is located between the p-type body region 12 and the FS region 18.

As described above, according to the SiC semiconductor device 4, in addition to the Hybrid-MOS structure, the SJ (Super Junction) structure is formed. With this SJ structure, the depletion layer can be spread over the entire interface in the direction along the interface between the p-type column region 35 and the n ⁻ -type drift region 19 (that is, the thickness direction of the n ⁻ -type drift region 19). As a result, local electric field concentration in the n ⁻ -type drift region 19 can be prevented, so that the on-resistance value can be reduced and the withstand voltage can be improved.

By the reduction effect of the on resistance and the improvement effect of the breakdown voltage, the characteristics of the pn junction rising voltage versus the characteristic on resistance shown in FIG. 3 can be further improved. Furthermore, since the characteristic can be improved, the impurity concentration of the n ⁻ -type drift region 19 can be formed thinner. In addition, the Y-axis thickness Td of the n ⁻ -type drift region 19 can be formed thinner. Therefore, it is possible to provide the SiC semiconductor device 4 excellent in any of the characteristics in the small current region and the characteristics in the large current region while enhancing the degree of freedom in design.

FIG. 16 is a schematic cross-sectional view of a SiC semiconductor device 5 according to a fifth embodiment of the present invention.
The SiC semiconductor device 5 differs from the above-described SiC semiconductor device 1 in that a trench gate structure is formed in which a gate electrode 37 is embedded in the gate trench 36 instead of the gate electrode 21. The other configuration is the same as that of the above-described SiC semiconductor device 1. In FIG. 16, parts corresponding to the parts shown in FIG. 1 described above are given the same reference numerals, and descriptions thereof will be omitted.

As shown in FIG. 16, with respect to the Y-axis along the thickness direction of SiC semiconductor layer 10, a plurality of gate trenches 36 are formed from the front surface side to the rear surface side of SiC semiconductor layer 10. The bottom of each gate trench 36 is located midway in the thickness direction of the SiC semiconductor layer 10 (n ⁻ -type drift region 19). The edge where the side and bottom of each gate trench 36 meet is formed in a shape curving outward of each gate trench 36, and each gate trench 36 is formed in a U-shape in cross section. If the edge of each gate trench 36 is curved, the electric field concentrated on the edge can be relaxed.

  A gate electrode 37 is embedded in each gate trench 36 via the gate insulating film 38. Gate electrode 37 has a surface flush with the surface of SiC semiconductor layer 10. The materials of the gate insulating film 38 and the gate electrode 37 are the same as those of the first embodiment described above. In regions between the gate trenches 36 adjacent to each other, p-type body regions 40 constituting the unit cell 11 are formed. A p-type region 39 is formed in a region between the bottom of each gate trench 36 and the upper end of the FS region 18.

A p-type region 39 is formed along the bottom of each gate trench 36. The p-type region 39 covers the edge portion of each gate trench 36, and the p-type region 39 can alleviate the electric field concentration at the edge portion of each gate trench 36. The p-type region 39 may be formed at a position spaced apart from the bottom of each gate trench 36.
The bottom of p-type body region 40 is located between the surface of SiC semiconductor layer 10 and the bottom of gate trench 36 with respect to the Y-axis along the thickness direction of SiC semiconductor layer 10. In the X-axis along the surface of SiC semiconductor layer 10, the end of p type body region 40 forms a part of gate trench 36. That is, the p-type body region 40 is electrically connected to the gate electrode 37 with the gate insulating film 38 interposed therebetween. In the present embodiment, the region between the p-type body region 40 and the FS region 18 is the n ⁻ -type drift region 19. An n-type source region 41 is formed in an inner region of the p-type body region 40.

The n-type source region 41 is formed shallower than the p-type body region 40 with respect to the Y-axis along the thickness direction of the SiC semiconductor layer 10. In the X-axis along the surface of SiC semiconductor layer 10, the end of n-type source region 41 forms a part of gate trench 36. That is, the n-type source region 41 is electrically connected to the gate electrode 37 with the gate insulating film 38 interposed therebetween. A region between the lower end of the n-type source region 41 and the lower end of the p-type body region 40 along the gate trench 36 is the p-type channel region 42 with respect to the Y-axis along the thickness direction of the SiC semiconductor layer 10. P ⁺ -type contact region 43 is formed to penetrate n-type source region 41.

The p ⁺ -type contact region 43 is formed to penetrate the n-type source region 41 and to cross the boundary between the n-type source region 41 and the p-type body region 40. The p ⁺ -type contact region 43 has a higher impurity concentration than the p-type body region 40.
An insulating film 44 covering the gate electrode 37 is formed on the SiC semiconductor layer 10. In the insulating film 44, a contact hole 45 which selectively exposes a part of the n-type source region 41 and the p ⁺ -type contact region 43 is formed. Source electrode 24 is electrically connected to p type body region 40, a part of n type source region 41, and p ⁺ type contact region 43 in contact hole 45.

As described above, according to the SiC semiconductor device 5, in addition to the hybrid-MOS structure, the trench gate structure is formed. According to such a configuration, the same effects as the effects described in the first embodiment can be obtained.
FIG. 17 is a schematic cross-sectional view of a SiC semiconductor device 6 according to a sixth embodiment of the present invention.
SiC semiconductor device 6 differs from SiC semiconductor device 5 described above in that a double trench structure including source trench 46 is formed in addition to gate trench 36, and p type region 39 is formed at the bottom of gate trench 36. that is not, and, in place of the p-type body region 40, n-type source region 41 and ^{p +} -type contact region 43,, p-type body region 47, n-type source region 48 and ^{p +} -type contact region 50, is It is a point that is formed. The other configuration is the same as that of the above-described SiC semiconductor device 6. In FIG. 17, portions corresponding to the respective portions shown in FIG. 16 described above are denoted by the same reference numerals, and description thereof is omitted.

  As shown in FIG. 17, a source trench 46 is formed at the center of each unit cell 11. A plurality of source trenches 46 are formed from the front surface side to the rear surface side of SiC semiconductor layer 10 with respect to the Y-axis along the thickness direction of SiC semiconductor layer 10. The source trench 46 is formed at the same depth as the gate trench 36. The edge where the side portion and the bottom portion of the source trench 46 meet is formed in a shape curving outward of the source trench 46, and the source trench 46 is formed in a U-shape in cross section. If the edge of the source trench 46 is curved, the electric field concentrated on the edge can be relaxed.

  P-type body region 47 is formed along the surface of SiC semiconductor layer 10 and the side and bottom of source trench 46. The p-type body region 47 formed along the side and bottom of the source trench 46 forms a part of the side and bottom of the source trench 46. In FIG. 17, the p-type body region 47 formed along the side of the source trench 46 is thinner than the p-type body region 47 formed along the bottom of the source trench 46. Although shown, it may be formed with the same thickness.

  An n-type source region 48 is formed on the surface portion of SiC semiconductor layer 10 between gate trench 36 and source trench 46. In the X-axis along the surface of SiC semiconductor layer 10, the end of n-type source region 48 forms a part of gate trench 36 and a part of source trench 46. The n-type source region 48 is formed shallower than the p-type body region 47 with respect to the Y-axis along the thickness direction of the SiC semiconductor layer 10. A region between the lower end of the n-type source region 48 and the lower end of the p-type body region 47 along the gate trench 36 with respect to the Y axis is a p-type channel region 49.

The p ⁺ -type contact region 50 is formed at the bottom of the source trench 46. That is, the p ⁺ -type contact region 50 forms a part of the bottom of the source trench 46. The bottom of the p ⁺ -type contact region 50 is located between the bottom of the source trench 46 and the bottom of the p-type body region 47 formed along the bottom of the source trench 46.
The source electrode 24 enters the contact hole 45 from the surface of the insulating film 44, and further enters the source trench 46 from the contact hole 45. Source electrode 24 is electrically connected to p type body region 47, n type source region 48 and p ⁺ type contact region 50 in contact hole 45 and source trench 46.

As described above, according to SiC semiconductor device 6, in addition to the Hybrid-MOS structure, a double trench structure including gate trench 36 and source trench 46 is formed. According to such a configuration, the same effects as the effects described in the first embodiment can be obtained.
In the present embodiment, an example in which the p-type region 39 is not formed at the bottom of the gate trench 36 has been described, but the p-type region 39 is at the bottom of each gate trench 36 as in the SiC semiconductor device 5 described above. It may be formed. In this case, the p-type region 39 and the p ⁺ -type contact region 50 may be formed with the same concentration and the same depth. With this configuration, the p-type region 39 and the p ⁺ -type contact region 50 can be formed in the same step.

<Planar shape of p ⁺ -type collector region>
The p ⁺ -type collector regions 17, 31, 32 of the above-described SiC semiconductor devices 1 to 6 may have planar shapes shown in FIGS. 18 to 20. FIG. 18 to FIG. 20 are plan views for explaining one planar shape of the p ⁺ -type collector regions 17 31 and 32 according to the first to sixth embodiments described above. The term “planar shape” refers to the shape of the p ⁺ -type collector regions 17 31 and 32 in a plan view when the SiC semiconductor layer 10 is viewed in the normal direction.

As shown in FIG. 18, the p ⁺ -type collector regions 17, 31 and 32 may be rectangular (striped). FIG. 18 shows an example of the p ⁺ -type collector regions 17, 31, 32 formed in a rectangular shape. In this case, the X-axis width Wc of the p ⁺ -type collector regions 17 31 and 32 is defined by the width in the short direction in the rectangular shape.
Further, as shown in FIG. 19, the p ⁺ -type collector regions 17, 31, 32 may be polygonal. FIG. 19 shows an example of the p ⁺ -type collector regions 17, 31, 32 formed in a hexagonal shape. In this case, the X-axis width Wc of the p ⁺ -type collector regions 17, 31, 32 is defined by the width of a perpendicular connecting two sides. If a straight line connecting two sides can not be drawn vertically as in a pentagon, the X-axis width Wc of the p ⁺ -type collector regions 17, 31, 32 may be defined by the width of the diagonal.

Further, as shown in FIG. 20, the p ⁺ -type collector regions 17, 31, 32 may be circular. In this case, the X-axis width Wc of the p ⁺ -type collector regions 17, 31, 32 is defined by the diameter of the circle. Of course, the p ⁺ -type collector regions 17 31 and 32 may have an elliptical shape. In the case of an elliptical shape, the X-axis width Wc of the p ⁺ -type collector regions 17 31 and 32 is defined by the width of the minor axis.
In the above-described SiC semiconductor devices 1 to 6, such p ⁺ -type collector regions 17, 31 and 32 are selectively formed in the back surface portion of the SiC semiconductor layer 10.

<Example of arrangement of p ⁺ -type collector region and n ⁺ -type drain region>
The p ⁺ -type collector regions 17, 31 and 32 and the n ⁺ -type drain region 16 of the above-described SiC semiconductor devices 1 to 6 may be arranged as shown in FIGS. 21 and 22. 21 and 22 are plan views for illustrating arrangement examples 51 and 52 of the p ⁺ -type collector regions 17 31 and 32 and the n ⁺ -type drain region 16.

As shown in the arrangement example 51 of FIG. 21, a plurality of p ⁺ -type collector regions 17, 31, 32 are formed in stripes at intervals. Further, n ⁺ -type drain regions 16 are formed in a stripe shape between the p ⁺ -type collector regions 17, 31 and 32 adjacent to each other. The plurality of p ⁺ -type collector regions 17, 31 and 32 selectively include a relatively wide region and a narrow region with respect to the wide region. In the arrangement example 51, X-axis width Wc of the ^{p +} -type collector region 17,31,32 is in the direction perpendicular to the stripe direction, among the widths of the plurality of ^{p +} -type collector region 17,31,32, widest It is defined by the width of the formed region.

In the arrangement example 52 of FIG. 22, a plurality of p ⁺ -type collector regions 17, 31, 32 having a rectangular shape in a plan view are formed in a matrix. Around of the square shape of the ^{p +} -type collector region 17,31,32, along the square shape of the ^{p +} -type collector region 17,31,32, in plan view a quadrangular ring ^{n +} -type drain region 16 / p ^{The +} type collector regions 17, 31, and 32 / n ⁺ type drain regions 16 are formed in this order. Then, grid-like p ⁺ -type collector regions 17 31 and 32 are formed so as to partition n ⁺ -type drain region 16 formed at the outermost periphery with respect to square-like p ⁺ -type collector regions 17 31 and 32. Is formed. In the arrangement example 51, X-axis width Wc of the ^{p +} -type collector region 17,31,32 is defined by the width of the rectangular ^{p +} -type collector region 17,31,32.

According to arrangement examples 51 and 52, when a predetermined pn junction rise voltage is applied to drain electrode 25 with source electrode 24 as a reference, first, p ⁺ -type collector regions 17 and 31 formed relatively wide. , 32 are turned on. Then, the transition of the wide p ⁺ -type collector regions 17 31 and 32 to the on state triggers the relatively narrow p ⁺ -type collector regions 17 31 and 32 to be sequentially turned on. Transition.

Therefore, the wide p ⁺ -type collector regions 17 31 and 32 are turned on even when the pn junction rise voltage that can not be normally turned on is applied to the narrow p ⁺ -type collector regions 17 31 and 32. By being in the state, the narrow p ⁺ -type collector regions 17, 31, 32 can be shifted to the on state. As a result, the characteristics at the rise of the pn junction can be improved.

As mentioned above, although embodiment of this invention was described, this invention can also be implemented with another form.
For example, the structures of SiC semiconductor devices 1 to 6 in the above-described embodiments may be selectively combined. Therefore, for example, p ⁺ type collector region 17 or insulating film 33 (high resistance layer) of SiC semiconductor devices 2 and 3 may be combined with SiC semiconductor devices 1 and 4.

In each of the above embodiments, the n ⁺ -type drain region 16 is formed in the region immediately below the unit cells 11 adjacent to each other, but the region other than the region directly below the unit cells 11 ( For example, an example in which the region immediately below the unit cell 11 is formed may be adopted.
In the above-described third embodiment, the example in which the isolation trench 34 having the side portion perpendicular to the back surface of the SiC semiconductor layer 10 is formed has been described. However, the isolation trench 34 is formed from the opening to the bottom. You may form in the cross sectional view trapezoid shape (tapered shape) which the opening width becomes narrow toward it. Similarly, the isolation trench 34 may be formed in a trapezoidal shape (tapered shape) in cross section in which the opening width widens from the opening to the bottom. Furthermore, the isolation trench 34 may be formed to be inclined toward the inward region side of the n ⁺ -type drain region 16 in a cross-sectional view. In addition, the isolation trench 34 is formed wider than the X-axis width Wc of the p ⁺ -type collector region 32 and / or the X-axis width Wd of the n ⁺ -type drain region 16 with respect to the X-axis along the surface of the SiC semiconductor layer 10 It may be done.

In the third embodiment described above, the high resistance layer may be formed to be inclined toward the inward region side of the n ⁺ -type drain region 16 in a cross sectional view. The high resistance layer is formed wider than the X axis width Wc of the p ⁺ -type collector region 32 and / or the X axis width Wd of the n ⁺ -type drain region 16 with respect to the X axis along the surface of the SiC semiconductor layer 10. It may be
Also, in the fifth and sixth embodiments described above, the example in which the gate trench 36 and / or the source trench 46 having the side perpendicular to the surface of the SiC semiconductor layer 10 is formed has been described. 36 and / or the source trench 46 may be formed in a trapezoidal shape (tapered shape) in cross section in which the opening width narrows from the opening to the bottom.

Further, in each of the embodiments described above, a configuration in which the conductivity type of each semiconductor portion is reversed may be employed. That is, in each of the embodiments described above, the p-type portion may be n-type, and the n-type portion may be p-type.
The SiC semiconductor devices 1 to 6 of the present invention are, for example, inverter circuits that constitute a drive circuit for driving an electric motor used as a power source of an electric car (including a hybrid car), a train, an industrial robot, etc. It can be incorporated into the power module used. It can also be incorporated into a power module used in an inverter circuit that converts power generated by solar cells, wind power generators and other power generation devices (especially private power generation devices) to match the power of a commercial power source.

  In addition, various design changes can be made within the scope of matters described in the claims. Examples of features extracted from this specification and drawings are shown below.

  [Item 1] A semiconductor layer made of SiC of a first conductivity type, a plurality of body regions of a second conductivity type formed in a surface portion of the semiconductor layer, each of which constitutes a unit cell, and inward of the body region A source region of the first conductivity type formed, a gate electrode facing the body region via the gate insulating film, a drain region of the first conductivity type formed adjacent to the back surface of the semiconductor layer, and The collector region includes a collector region of two conductivity types and a drift region between the body region and the drain region, and the collector region includes at least two unit cells in an X-axis along the surface of the semiconductor layer. A semiconductor device formed to cover an area.

  According to this configuration, the semiconductor device is a hybrid-MOS (Hybrid-Metal Oxide Semiconductor) in which a SiC-MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and a SiC-IGBT (Insulated Gate Bipolar Semiconductor) are integrated in the same semiconductor layer. ) Has a structure. More specifically, the SiC-MOSFET is formed of a source region, a drain region, and a gate electrode, and the SiC-IGBT is formed of a source region, a collector region, and a gate electrode. The SiC-MOSFET and the SiC-IGBT are connected in parallel via the semiconductor layer. When operating as a SiC-IGBT, the source region functions as an emitter region and the drift region functions as a base region.

  The SiC-MOSFET is effective as an element mainly used in a low withstand voltage region (for example, 5 kV or less). That is, in the case of the SiC-MOSFET, when turned on, the drain current rises from when the drain voltage is 0 V, and then linearly increases according to the increase of the drain voltage. Therefore, in the SiC-MOSFET, it is possible to exhibit the characteristics of a good small current region. On the other hand, since the drain current linearly increases with the increase of the drain voltage, when using a SiC-MOSFET in a large current region, the area of the semiconductor layer is expanded according to the increase of the applied drain voltage. There must be.

  On the other hand, SiC-IGBT is effective as an element used mainly in a high breakdown voltage region (for example, 10 kV or more). That is, in the case of the SiC-IGBT, since it has the conductivity modulation characteristics of the bipolar transistor, large current control is possible with high withstand voltage. Therefore, in the SiC-IGBT, good large current region characteristics can be exhibited without expanding the area of the semiconductor layer. On the other hand, since SiC is a wide gap semiconductor, it has a higher pn barrier than Si. Therefore, when using a SiC-IGBT in a small current region, a parasitic diode is formed at the pn junction, so a relatively high pn junction rise voltage (for example, 2.7 V or more) is required.

  From these, by integrating the SiC-MOSFET and the SiC-IGBT in the same semiconductor layer, it is theoretically possible to realize a wide operation range from the low breakdown voltage region to the high breakdown voltage region. That is, it is possible to provide a semiconductor device capable of realizing MOSFET (unipolar) operation in a small current region, and IGBT (bipolar) operation in a large current region, even though it can be used as a high voltage element.

However, simply connecting the collector region and the drain region in SiC-MOSFET and SiC-IGBT requires a very high voltage at the transition from a small current region to a large current region, and increases the on-resistance. You may
Here, in the semiconductor layer in which the SiC-MOSFET and the SiC-IGBT are formed, equipotential surfaces are distributed such that the potential becomes higher from the surface side to the back side of the semiconductor layer. In particular, in the semiconductor layer, relatively high equipotential surfaces are distributed so as to expand concentrically around the drain region. Therefore, when a relatively narrow collector region is formed, an equipotential surface having almost no difference from the drain voltage applied to the drain region is distributed to cover the collector region.

  In this case, since the drain region and the collector region are at the same potential, even if the drain voltage is increased, the pn junction rising voltage (that is, 2.7 V) or more is generated between the collector region and the equipotential surface covering the collector region. It is difficult for the potential difference of Therefore, the drain voltage must be increased until the potential difference between the collector region and the equipotential surface becomes equal to or higher than the pn junction rise voltage. Therefore, a very high voltage is required at the time of transition from the small current region to the large current region.

  Therefore, as in the SiC semiconductor device according to the item 1, by forming a collector region to cover a region including at least two unit cells along the X-axis along the surface of the semiconductor layer, it is relatively low, etc. The potential surface can be widely distributed at the top of the collector region. In this case, since the potential difference between the collector region and the equipotential surface can be brought close to the pn junction rising voltage, the pn junction (parasitic diode) can be turned on by a relatively small increase in drain voltage. . As a result, the transition from the small current region to the large current region can be made by the relatively small drain voltage, so that the trade-off relationship between the characteristics of the small current region and the characteristics of the large current region can be improved. As a result, it is possible to provide a SiC semiconductor device excellent in both the characteristics in the small current region and the characteristics in the large current region.

[Item 2] A semiconductor layer made of SiC of a first conductivity type, a body region of a second conductivity type formed on the surface portion of the semiconductor layer, and a first conductivity type of an inside of the body region A source region, a gate electrode facing the body region through a gate insulating film, a drain region of a first conductivity type formed adjacent to the back surface of the semiconductor layer, and a collector region of a second conductivity type; The X axis width Wc along the surface of the semiconductor layer of the collector region including the drift region between the body region and the drain region is the Y axis thickness along the thickness direction of the semiconductor layer of the drift region The semiconductor device which is twice or more of Td.
Even with such a configuration, the same effects as the effects described in Item 1 can be obtained.
[Item 3] The semiconductor device according to Item 1 or 2, wherein the drain region has an X-axis width Wd equal to or larger than that of the collector region. According to this configuration, the characteristics of the small current region can be improved while maintaining the characteristics of the large current region.

  [Item 4] A semiconductor layer made of SiC of a first conductivity type, a body region of a second conductivity type formed on the surface portion of the semiconductor layer, and a first conductivity type of an inside of the body region A source region, a gate electrode facing the body region through a gate insulating film, a drain region of a first conductivity type formed adjacent to the back surface of the semiconductor layer, and a collector region of a second conductivity type; The drift region between the body region and the drain region, and the Y-axis along the thickness direction of the semiconductor layer is disposed between the drain region and the collector region with respect to the back surface of the semiconductor layer A semiconductor device comprising: a drain region; and an insulating layer formed deeper than the collector region.

  According to this configuration, since the insulating layer is formed between the drain region and the collector region, the relatively high equipotential surface spreading from the drain region can be blocked by the insulating film. As a result, distribution of relatively high equipotential surfaces in the collector region can be suppressed, and at the same time, relatively low equipotential surfaces can be distributed in the collector region. In this case, since the potential difference between the equipotential surface and the collector region can be brought close to the pn junction rising voltage, the pn junction (parasitic diode) can be turned on by a relatively small increase in drain voltage. . As a result, the transition from the small current region to the large current region can be made by the relatively small increase in drain voltage, so that the trade-off relationship between the characteristics of the small current region and the characteristics of the large current region can be improved. As a result, it is possible to provide a SiC semiconductor device excellent in both the characteristics in the small current region and the characteristics in the large current region.

[Item 5] The semiconductor device according to Item 4, wherein the insulating layer is formed of an insulating film or a high resistance layer.
[Item 6] The semiconductor device according to Item 4 or 5, wherein the insulating layer is made of an insulating material having a relative dielectric constant lower than that of SiC.
[Item 7] The semiconductor device according to Item 6, wherein the insulating layer is made of SiO ₂ .

  [Item 8] A semiconductor layer made of SiC of a first conductivity type, a body region of a second conductivity type formed on the surface portion of the semiconductor layer, and a first conductivity type of an inside of the body region A source region, a gate electrode facing the body region through a gate insulating film, a drain region of a first conductivity type formed adjacent to the back surface of the semiconductor layer, and a collector region of a second conductivity type; The upper end of the collector region is closer to the surface side of the semiconductor layer than the upper end of the drain region in the Y-axis along the thickness direction of the semiconductor layer, including the drift region between the body region and the drain region. A semiconductor device located in

According to this configuration, since the upper end of the collector region is located closer to the surface of the semiconductor layer than the upper end of the drain region, it is possible to suppress the equipotential surface extending from the drain region reaching the upper end of the collector region. As a result, distribution of relatively high equipotential surfaces in the collector region can be suppressed, and at the same time, relatively low equipotential surfaces can be distributed in the collector region. In this case, since the potential difference between the equipotential surface and the collector region can be brought close to the pn junction rising voltage, the pn junction (parasitic diode) can be turned on by a relatively small increase in drain voltage. .
Furthermore, by forming the thickness from the upper end of the drain region to the upper end of the collector region to be thick, the characteristics of the on-resistance can be improved as compared to the case where the drain region and the collector region are formed to have the same thickness.

[Item 9] The semiconductor device according to Item 8, wherein the back surface of the semiconductor layer is flush with the boundary between the drain region and the collector region.
[Item 10] A field stop region formed across the drain region and the collector region along the X-axis along the surface of the semiconductor layer, and disposed between the drift region and the drain region and the collector region 10. The semiconductor device according to any one of items 1 to 9, further comprising

  According to this configuration, it is possible to provide a FS (Field Stop) type semiconductor device. A non-punch through (NPT) type semiconductor device is known as an FS type semiconductor device. In the case of the NPT type semiconductor device, the semiconductor layer must be formed relatively thick so that the depletion layer generated from the interface between the body region and the drift region does not reach the lower surface of the semiconductor layer and punch through. On the other hand, in the case of the FS type semiconductor device, since the expansion of the depletion layer can be blocked in the field stop region, punch-through can be suppressed. Therefore, in the FS type semiconductor device, the semiconductor layer can be thinner than in the NPT type semiconductor device.

[Item 11] The semiconductor device according to any one of Items 1 to 10, wherein the semiconductor device includes a planar gate structure in which the gate electrode is disposed on the semiconductor layer.
[Item 12] The semiconductor device according to any one of Items 1 to 10, wherein the semiconductor device includes a trench gate structure in which the gate electrode is embedded in a trench formed in the semiconductor layer.

Reference Signs List 1 SiC semiconductor device 2 SiC semiconductor device 3 SiC semiconductor device 4 SiC semiconductor device 5 SiC semiconductor device 6 SiC semiconductor device 10 SiC semiconductor layer 11 unit cell 12 p-type body region 13 n-type source region 16 n ⁺ -type drain region 17 p ⁺ Collector region 18 FS (field stop) region 19 n ⁻ type drift region 20 gate insulating film 21 gate electrode 31 p ⁺ type collector region 32 p ⁺ type collector region 33 insulating film 36 gate trench 37 gate electrode 38 gate insulating film 40 p Type body area 41 n type source area 47 p type body area 48 n type source area Td Y axis thickness Wc X axis width Wd X axis width

Claims (15)

A semiconductor layer of a first conductivity type comprising SiC and having a front surface and a back surface;
A first recess formed on the surface of the semiconductor layer and having a bottom and side surfaces;
A second recess formed on the surface of the semiconductor layer at a distance from the first recess;
A gate insulating film formed along the bottom and the side surface of the first recess;
A gate electrode embedded in the first recess via the gate insulating film;
The semiconductor layer is formed in a region along the first recess and the second recess in the surface portion of the surface of the semiconductor layer, and a portion along the side surface of the first recess is the semiconductor layer with respect to the bottom portion of the first recess. A body region of a second conductivity type located on the front surface side of the semiconductor layer, and a portion located below the second recess is located on the back surface side of the semiconductor layer with respect to the bottom portion of the first recess;
A first conductivity type of a first conductivity type formed on the body region to be in contact with the side surface of the first recess in a region between the first recess and the second recess in a surface portion of the surface of the semiconductor layer With the source area,
A second conductivity type high concentration region formed in a region along the second recess in the body region and having an impurity concentration higher than the impurity concentration of a region located below the source region in the body region;
An insulating layer covering a portion of the source region and the gate electrode so as to expose the source region and the second recess on the surface of the semiconductor layer;
A semiconductor device comprising: the insulating layer, the second recess, the body region, and a source electrode covering the source region on the surface of the semiconductor layer. The plurality of body regions are formed at intervals in a surface portion of the surface of the semiconductor layer,
The semiconductor device according to claim 1, wherein the source region is formed on each of a plurality of the body regions. A plurality of the first depressions are formed at intervals in cross section,
The semiconductor device according to claim 1, wherein the second recess is formed between two first recesses adjacent to each other in a cross sectional view.   The semiconductor device according to any one of claims 1 to 3, further comprising a drain region of the first conductivity type formed on the back surface of the semiconductor layer.   The semiconductor device according to claim 4, wherein the drain region faces the first recess in a thickness direction of the semiconductor layer.   The semiconductor device according to claim 4, further comprising a drift region located between the body region and the drain region in the semiconductor layer.   The semiconductor device according to claim 6, wherein the thickness of the drift region is 100 μm or less in the thickness direction of the semiconductor layer.   The semiconductor device according to any one of claims 1 to 7, wherein the first recess connects the bottom portion and the side surface and has an edge portion which curves outward from the inner side.   The low concentration region of the second conductivity type, further comprising a part of the body region below the high concentration region, and having an impurity concentration lower than the impurity concentration of the high concentration region. The semiconductor device according to claim 1.   The semiconductor device according to any one of claims 1 to 9, further comprising a second conductivity type region formed in a region along the bottom of the first recess in the semiconductor layer.   The semiconductor device according to any one of claims 1 to 10, wherein the gate insulating film is made of a silicon oxide film.   The said source electrode is electrically connected with the said high concentration area | region in the area | region by the side of the said back surface of the said semiconductor layer with respect to the said surface of the said semiconductor layer. Semiconductor device.   The semiconductor device according to any one of claims 1 to 12, which operates at 5 kV or less.   The semiconductor device according to any one of claims 1 to 13, which is used in an inverter circuit.   The semiconductor device according to any one of claims 1 to 14, which is a non-punch through type.

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