JP2009218306A - Dislocation detecting method in silicon carbide semiconductor wafer, and manufacturing method of silicon carbide semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To detect a dislocation in a silicon carbide semiconductor wafer by a little work increase during a device process. <P>SOLUTION: The silicon carbide semiconductor wafer 3 whose principal plane is (0001) Si surface in general is used for depositing a polycrystalline silicon 12 after forming a thermal oxidation film 11. On a front surface thereof, a hillock 20 is produced corresponding to a dislocation 64 in the wafer. The dislocation 64 is detected by carrying out an image processing of a scattered light of a laser for this hillock 20. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a dislocation detection method in a silicon carbide semiconductor (hereinafter, abbreviated as SiC) wafer during a wafer process of a silicon carbide semiconductor device.

When a high voltage power semiconductor device is manufactured using SiC, there is a possibility that the on-resistance can be greatly reduced. An on-resistance of 5 mΩcm ² or less has already been obtained by a SiC MOSFET having a breakdown voltage of 1 to 1.2 kV. This on-resistance value has an on-resistance less than half that of a silicon (hereinafter abbreviated as Si) IGBT having the same breakdown voltage class. If cost development and performance improvement proceed in the future, it is possible that most Si IGBTs will be replaced as inverter parts.
By the way, many dislocations are usually present in SiC bulk substrates that are currently available on the market. These dislocations are known to degrade the characteristics of SiC semiconductor devices. For example, when an oxide film is formed on a portion where these dislocations appear on the surface of the SiC wafer, the reliability of the oxide film is significantly lowered. In addition, when these dislocations penetrate a pn junction formed in a SiC wafer that has undergone a wafer process, the breakdown voltage due to the pn junction is reduced (hereinafter, before the SiC epitaxial layer is grown on the surface). The highly doped SiC substrate is referred to as a bulk substrate, and the grown SiC substrate is referred to as a SiC wafer). Similarly, even when dislocations are in contact with the Schottky junction, it is suspected to increase the leakage current and consequently reduce the applicable breakdown voltage. Research on dislocations in SiC wafers has been actively conducted from such a viewpoint.

For power semiconductor devices, breakdown voltage characteristics and reliability characteristics are extremely important performances. Therefore, such dislocations that degrade the performance are easily detected at the earliest possible process stage in the SiC wafer process, and semiconductor devices including dislocations are screened in advance so that they can be excluded as defective products, for example, by marking. This is important in a wafer process line for actually manufacturing a semiconductor device.
In the past, dislocations in SiC wafers were sometimes huge, several microns or more. Such huge dislocations can usually be observed with an optical microscope. However, as the wafer manufacturing technology improved, there were very few such huge dislocations. These days, most of them are very small dislocations that can only be grasped by observing in detail with an electron microscope after specifying the position in advance. However, it has become clear that even such a small dislocation affects the reliability of semiconductor characteristics.
As a conventional method for detecting dislocations, a method of forming an etch pit by immersing a SiC wafer having a (0001) _Si surface in molten alkali hydroxide (potassium hydroxide or the like) has been performed for a long time. . However, since this inspection is a kind of destructive test that causes surface irregularities in normal portions due to excessive etching, the SiC wafer subjected to this inspection cannot be directly returned to the wafer process line. In addition, the phrase “substantially (0001) _Si surface” means that the main surface in the case of a commercially available SiC wafer usually has an off angle of 4 to 8 degrees in order to obtain a good epitaxial growth layer. This is because it is not the (0001) _Si surface itself. Here, the epitaxial growth having an off angle is a method for producing a SiC epitaxial film on an off substrate in which a Si surface having Si atoms on the outermost surface is inclined several degrees with respect to the crystal axis of SiC (referred to as an off angle). To tell. In addition, the (0001) _Si plane in the claims includes those provided with an off angle of 4 to 8 degrees.

In SiC, as in the Si wafer process, since a technique for suitably controlling doping suitable for manufacturing a power semiconductor wafer has not been established, at present, epitaxial growth is essential for manufacturing an SiC wafer. Technology. If regrinding and epitaxial growth are performed, surface irregularities are repaired. However, a phenomenon is known in which the dislocation position appearing on the epitaxial growth surface is different from the dislocation position in the original bulk substrate during SiC epitaxial growth, or a new dislocation is generated by SiC epitaxial growth. Therefore, the precise position of dislocations appearing on the surface of the SiC wafer can be known only after SiC epitaxial growth is performed.
Also in the prior art, the following methods are known as methods for detecting dislocations on the surface of a SiC wafer that can be applied after SiC epitaxial growth. That is, an oxide film is formed on the SiC wafer surface, an ohmic contact electrode is provided on the back surface, and an inspection gate electrode is provided on the surface. Next, a high electric field is applied to the oxide film by applying a voltage between the inspection gate electrode and the ohmic contact back electrode. At this time, the position of the dislocation is detected by observing the emission emission by the electron-hole pair generated by the leak current flowing through the weak part of the oxide film such as the dislocation. Finally, there is a dislocation detection method for removing an inspection gate electrode, an ohmic contact electrode on the back surface, and an oxide film on the wafer surface (Patent Document 1).

In addition, the position and type of dislocations and stacking faults in the SiC wafer plane are specified by light emission mapping data, and a silicon carbide semiconductor element that does not affect the element characteristics due to crystal defects is manufactured by screening based on the mapping data. The technology is also disclosed (Patent Document 2).
JP 2000-003946 A JP 2007-318031 A (summary)

However, although the dislocation detection method described in Patent Document 1 is necessary for inspection, it is originally an unnecessary and unnecessary step from the viewpoint of wafer process technology for manufacturing a semiconductor device. It is not preferable from the viewpoint of reducing the manufacturing cost of the semiconductor device. Further, in this dislocation detection method, if there is a location where a large leak current is generated even at one location in the inspection electrode, the current tends to concentrate on that location. It becomes difficult to detect existing small dislocations that cause relatively small leaks. However, in order to avoid such small dislocations from being overlooked, even if the entire wafer surface is not formed as one electrode, and a large number of small electrodes are formed, this time, dislocations present in the gaps between the small electrodes are detected. Can not do. Moreover, since the emission emission due to the leakage current of the oxide film is very weak, the current technology often requires time for measurement and repeated local observation. Furthermore, this method has a problem that a defect caused by a process in the inspection process is erroneously determined as a defect.
The present invention has been made in view of the foregoing points, and an object of the present invention is to reduce the number of work steps that are substantially increased by the addition of the wafer dislocation detection step added during the silicon carbide semiconductor wafer process. At the same time, it is an object to provide a method for detecting dislocations in a silicon carbide semiconductor wafer and a method for manufacturing a silicon carbide semiconductor device in which a semiconductor device including a detected dislocation location is eliminated as a defect or relieved as a non-defective product.

According to the first aspect of the present invention, after the silicon carbide semiconductor wafer whose main surface is the (0001) _Si surface is thermally oxidized, polycrystalline silicon is deposited, and hillocks appearing on the surface of the polycrystalline silicon. The above-described object of the present invention is achieved by adopting a method for detecting dislocations in a silicon carbide semiconductor wafer in which the presence of dislocations is detected and the detection position in the case of dislocations is specified.
According to the invention described in claim 2, when the surface of the polycrystalline silicon is irradiated with laser light and the scattered light image is image-processed, the presence / absence of the dislocation and the presence of the dislocation are detected. A dislocation detection method in a silicon carbide semiconductor wafer according to claim 1, wherein the detection position is specified.
According to the third aspect of the present invention, after the silicon carbide semiconductor wafer whose main surface is the (0001) _Si surface is thermally oxidized, polycrystalline silicon is deposited, and hillocks appearing on the surface of the polycrystalline silicon. Is regarded as a dislocation, and a method for manufacturing a silicon carbide semiconductor device according to the claims is provided for detecting the presence or absence of a dislocation and specifying the detection position when the dislocation is present.
According to the invention of claim 4, when the surface of the polycrystalline silicon is irradiated with a laser beam and the scattered light image is image-processed, the presence / absence of the dislocation and the presence of the dislocation A method for manufacturing a silicon carbide semiconductor device according to claim 3, further comprising a step of specifying a detection position of the silicon carbide semiconductor device.

According to the invention of claim 5, the silicon carbide semiconductor device in which at least a part of the polycrystalline silicon deposited for observing the surface is formed on the basis of the silicon carbide semiconductor wafer. A method of manufacturing a silicon carbide semiconductor device according to claim 3 or 4 as a constituent element.
According to the invention of claim 6, at least a part of the insulating film obtained by thermally oxidizing or nitriding the polycrystalline silicon deposited for observing the surface is the silicon carbide semiconductor wafer. A method for manufacturing a silicon carbide semiconductor device according to claim 3 or 4, wherein the silicon carbide semiconductor device is formed as a constituent element of the silicon carbide semiconductor device.
According to the seventh aspect of the present invention, a constituent element of a silicon carbide semiconductor device in which at least a part of the silicon oxide film formed by the thermal oxidation is formed based on the silicon carbide semiconductor wafer. A method for manufacturing a silicon carbide semiconductor device according to claim 6 of the claims.
According to the invention of claim 8, the first conductivity type withstand voltage layer and the second conductivity type selectively provided on one main surface of the withstand voltage layer are formed on the silicon carbide semiconductor wafer. A body region, a source region of a first conductivity type selectively provided on the surface layer of the body region, and a surface of the body region sandwiched between the source region surface layer and the surface layer of the breakdown voltage layer via an insulating film And a back surface electrode that is in ohmic contact with the other main surface of the pressure-resistant layer. A method for manufacturing a silicon carbide semiconductor device according to any one of claims 5 to 7, wherein the method is a gate-type semiconductor device.

According to the invention of claim 9, the first conductivity type withstand voltage layer adjacent to the detection position of the dislocation after the step of detecting the presence or absence of the dislocation and specifying the detection position when the dislocation is present 9. The method for manufacturing a silicon carbide semiconductor device according to claim 8, wherein the step of converting the surface layer of the first to the second conductivity type and the step of removing the gate electrode on the surface of the body region in the vicinity of the dislocation detection position are performed. The method.
According to the invention of claim 10, after the step of converting the surface layer of the first conductivity type withstand voltage layer to the second conductivity type and the step of removing the gate electrode on the surface of the body region, A method for manufacturing a silicon carbide semiconductor device according to claim 9, wherein a step of detecting again the dislocations generated in the substrate is performed.
According to the invention described in claim 11, the silicon carbide semiconductor device is a trench type, and the detection position is specified after the step of detecting the presence / absence of the dislocation and specifying the detection position when the dislocation is present. The method for manufacturing a silicon carbide semiconductor device according to claim 8, wherein a step of providing a trench gate structure with a trench pattern not including a trench is provided in the vicinity of the dislocation.
According to the twelfth aspect of the present invention, the newly generated dislocation is detected again after the step of providing the trench gate structure with the trench pattern not including the trench in the vicinity of the dislocation whose detection position is specified. A method for manufacturing a silicon carbide semiconductor device according to claim 11 having the step of:

According to the invention of claim 13, the planar shape of the trench formed on the surface of the silicon carbide wafer is a shape parallel to the off direction of the silicon carbide semiconductor wafer. Item 11. A method for manufacturing a silicon carbide semiconductor device according to Item 11.
According to the invention of claim 14, the silicon carbide semiconductor device having a planar trench parallel to the off direction of the silicon carbide semiconductor wafer is parallel to the off direction of the silicon carbide semiconductor wafer. The method of manufacturing a silicon carbide semiconductor device according to claim 13, wherein the length of the silicon carbide semiconductor wafer in the direction perpendicular to the off direction is longer than the length of the silicon carbide semiconductor wafer.
When a SiC wafer having a (0001) _Si surface is thermally oxidized and the thermal oxide film is removed, shallow pits having a diameter of about 0.5 microns or less and a depth of about submicron or less are formed on the SiC wafer corresponding to dislocations. Is produced. Since this pit is small and too shallow, detection by macroscopic means is impossible as it is. However, if polycrystalline silicon is deposited on the thermal oxide film without removing the thermal oxide film, a hillock having a detectable size is formed due to abnormal growth, and corresponds to both the number of dislocations and the position in the wafer. I found out. The size of this hillock is about 0.5 microns in diameter, but the height can also be about 0.2 to 0.5 microns, and if this size, it is macroscopic such as a kind of particle inspection device. It can be detected by means. For example, when scattered light of laser light is detected, scattered light is seen over a size of several microns due to diffuse scattering by the hillock, so that hillock can be detected even at a low resolution. With this method, hillocks are detected by macroscopic means, so that the possibility of overlooking is low as in the case of inspection by emission emission. Furthermore, the process of forming a thermal oxide film and forming polycrystalline silicon thereon often appears in the process of manufacturing a semiconductor device. In such a process, since the position of dislocation can be specified by simply detecting hillocks with a particle inspection apparatus after forming polycrystalline silicon, it can be realized easily. The thermal oxide film and the polycrystalline silicon may function as a component of the semiconductor device to be manufactured, or may be used to form a component of the semiconductor device. . In any case, it is not necessary to add an additional thermal oxidation step and a polycrystalline silicon deposition step and its removal step only to detect the position of dislocations. Thus, if a hillock is detected, for example, a semiconductor device including the hillock can be screened and rejected as a defective product. Furthermore, as described above, the present invention not only screens and eliminates hillock-containing semiconductor devices as defective products, but also makes defective portions non-functional areas to reduce adverse effects on semiconductor characteristics, thereby reducing defective products. Relieving those that are excluded as good products is also included. Note that hillocks may also occur when particles or the like are present on the wafer before thermal oxidation and before deposition of polycrystalline silicon. In the current semiconductor manufacturing process, the density of such particles is very small compared to the dislocation density in SiC wafers currently on the market. And since such a place is a defective place anyway, it may be screened like a dislocation.

  According to the present invention, in the wafer dislocation detection step added during the silicon carbide semiconductor wafer process, the work man-hour that is substantially increased by the addition is reduced, and the semiconductor device including the detected dislocation location is simplified and It is possible to provide a method for detecting dislocations in a silicon carbide semiconductor wafer and a method for manufacturing a silicon carbide semiconductor device, which are excluded as defectives with high accuracy or relieved as good products.

Hereinafter, a vertical / trench insulated gate MOS semiconductor device of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the description of the examples described below unless it exceeds the gist.
FIG. 1 is a cross-sectional view of the DMOSFET according to the first and second embodiments. FIG. 2 is a plan view showing a state in which part of the JFET region 9 is converted to p-type in the second embodiment. FIG. 3 is a plan view showing a state in which a part of the gate electrode 12 is removed in the second embodiment. FIG. 4 is a cross-sectional view of the main part of the pressure-resistant structure according to the third embodiment. FIG. 5 is a cross-sectional view of the main part immediately after finishing the ion implantation for the guard ring region 28a in the third embodiment. FIG. 6 is a cross-sectional view of the main part immediately after finishing the ion implantation for the guard ring regions 28a and 28b in the third embodiment. FIG. 7 shows the propagation direction of dislocations in the epitaxial growth layer of the SiC wafer, (a) is a plan view of the SiC wafer viewed from above with the dislocations projected onto the surface, and (b) is a state in which the dislocations are projected on the cross section. It is sectional drawing of a SiC wafer. FIG. 8 is a cross-sectional view of the principal part of the trench MOSFET according to the fourth embodiment. FIG. 9 is a cross-sectional view of main parts of different trench MOSFETs according to the fourth embodiment. FIG. 10 is a cross-sectional view of main parts of still another trench MOSFET according to the fourth embodiment. FIG. 11 is an enlarged cross-sectional view of a hillock portion of a SiC wafer having dislocations having a thermal oxide film and polycrystalline silicon formed on the surface.

FIG. 1 according to the first embodiment is a cross-sectional view of a unit cell (hereinafter sometimes simply referred to as a cell) of a DMOSFET. High de - approximately (0001) of 4H-SiC is a flop n-type _Si surface on bulk substrate 1 whose principal plane (called front surface), n-type field stopping layer 2, a low de - flop n-type The drift layer 3 is sequentially stacked by, for example, epitaxial growth. The doping of the field stopping layer 2 is, for example, a doping density of 1 × 10 ¹⁸ cm ⁻³ and the film thickness is, for example, 1 μm.
The doping and film thickness of the drift layer 3 are design matters to be determined depending on the desired breakdown voltage. For example, when the design breakdown voltage is 1.2 kV, the doping density is 1 × 10 ¹⁶ cm ⁻³ and the film thickness is 13 μm. It is. A p-type body region 5 is formed in a part of the surface layer of the drift layer 3.
The doping profile of the p-type body region 5 should be designed as appropriate according to the desired performance and characteristics (breakdown voltage, threshold voltage, etc.). For example, the doping density is 10 ¹⁹ cm ⁻³ at the deepest part and the doping at the outermost surface. The inclination profile has a density of about 2 × 10 ¹⁷ cm ⁻³ and the total depth is, for example, 1 μm. A high-doping n-type source contact region 6 and a high-doping p-type body contact region 7 are formed in part of the surface layer of the p-type body region 5.

The surface layer portion of the body region 5 sandwiched between the source contact region 6 and the surface layer region (referred to as JFET region 9) sandwiched between the adjacent body regions 5 in the drift layer 3 is a channel forming portion 13 in which a channel is formed. It becomes. On the surface of the channel forming portion 13 and the surface in the vicinity thereof, a gate electrode 12 made of conductive polycrystalline silicon doped with phosphorus in a high dose is placed by deposition via a gate insulating film 11. The gate electrode 12 is further insulated from the source electrode 23 covering the upper portion by an interlayer insulating film 21 covering the gate electrode 12. The source electrode 23 is in ohmic contact with the surfaces of the source contact region 6 and the body contact region 7 in common.
The drain electrode 22 is in ohmic contact with the opposite main surface (referred to as the back surface) of the bulk substrate 1. Of the drain electrode 22 and the source electrode 23, the metal film interface that is in direct contact with the SiC wafer surface is reacted with, for example, a metal film in which nickel and titanium are sequentially laminated by heat treatment to obtain good ohmic contact. To a predetermined alloy state. Other film portions of the drain electrode 22 and the source electrode 23 (film portions formed on the nickel and titanium layers) are made of, for example, an aluminum film.
Since FIG. 1 is a cross-sectional view of a unit cell in a DMOSFET as described above, only one gate electrode is shown. However, in an actual DMOSFET, an active region in which a main current flows is located in a unit cell. (Unit structure) is repeated many times. In FIG. 1, for the sake of explanation, a portion that becomes a thin line in the drawing is enlarged and drawn, which is different from the actual dimensional ratio. The same applies to the subsequent figures. Moreover, the same number is attached | subjected with respect to the same component, and description is abbreviate | omitted about the overlapping element.

Further, in FIG. 1, since the channel forming portion 13 is also a part of the body region, its conductivity type is p-type, but this portion or a part thereof is a so-called storage type in which an n-type region is provided in advance. It may be a MOSFET. In FIG. 1, a structure in which the n-type and the p-type are interchanged is also possible. However, in a SiC wafer, the mobility of electrons is several times higher than that of holes. Since better characteristics are obtained when the carrier is an electron, it is preferable to use a conductive laminated structure as shown in FIG. In an actual power semiconductor device, in order to obtain a desired breakdown voltage, some kind of electric field relaxation structure is required in the periphery of the semiconductor device (chip). This is described in the electric field relaxation described in Example 3 and later. The structure can also be applied to the first embodiment.
A method for manufacturing this DMOSFET will be briefly described. First, a SiC wafer is formed by laminating the field stopping layer 2 and the drift layer 3 in this order on the SiC bulk substrate 1 by SiC epitaxial growth by SiC epitaxial growth. Thereafter, a SiO ₂ film serving as a mask material is formed on the surface of the epitaxial growth layer, and a SiO ₂ film mask pattern is appropriately formed. The SiC wafer is etched by about 1 μm to form a mask alignment marker (not shown in FIG. 1).

Subsequently, using the SiO ₂ film mask pattern, with the SiC wafer heated to, for example, 500 ° C., aluminum is applied to the p-type region and phosphorus is applied to the n-type region so as to have a predetermined profile. Ion implantation (not excluding ion implantation at room temperature). Next, the SiC wafer is heated to, for example, 1700 ° C. in a mixed atmosphere of Ar and SiH ₄ to activate the ion-implanted aluminum and phosphorus (called activation annealing). This activation annealing may be performed individually after ion implantation for forming each p, n-type region and each profile, or may be performed collectively at the end, but is performed in a Si wafer process. As described above, when screen oxidation is performed immediately before ion implantation, the ion implantation layer disappears due to accelerated oxidation. Therefore, in order to avoid this phenomenon, it is preferably performed individually after each ion implantation.
Next, an appropriate atmosphere, in N ₂ O atmosphere N ₂ dilution of for example 1300 ° C., a predetermined time, the SiC wafer is thermally oxidized, the gate insulating film 11 (in this case a predetermined thickness, an oxide film (Also called a gate oxide film). Although this film thickness depends on the gate drive voltage and the drive electric field strength, it can be set to, for example, 50 nanometers. Subsequently, similarly to the Si wafer process, phosphorus-doped polycrystalline silicon 12 is deposited to a thickness of about 0.4 μm by low pressure CVD. As shown in the enlarged sectional view of FIG. 11, at this time, due to the dislocations 64 appearing on the surface of the SiC wafer 3, abnormal protrusions 24 are generated on the corresponding surface of the gate oxide film 11. Hillocks (protrusions) 20 are also formed on the crystalline silicon surface due to abnormal growth. The size is, for example, about 0.5 μm in diameter and about 0.3 μm in height on the polycrystalline silicon film 12. The hillock 20 appears on the surface of the polycrystalline silicon almost corresponding to the dislocation 64 in a one-to-one correspondence, although there is a slight positional deviation accompanying the inclination angle at which the dislocation runs. Hereinafter, the grounds or reason for the phenomenon in which hillocks 20 appear on the surface of the polycrystalline silicon 12 corresponding to the dislocations 64 on the surface of the SiC wafer will be described with speculation.

When the surface of the SiC wafer is thermally oxidized, the oxidation rate is increased by stress on the surface of the dislocation portion with respect to the flat normal SiC wafer surface. Therefore, on the surface of the oxide film 11, the dislocation 64 is located at a position corresponding to the vicinity. The oxide film 11 becomes thicker and can rise (as in the case of Si, when SiC becomes SiO ₂ , the volume expands). Subsequently, the polycrystalline silicon 12 is formed under the same deposition conditions as in the Si wafer process. When the polycrystalline silicon 12 is deposited, the (111) plane is usually oriented along the surface of the flat oxide film 11. However, in the vicinity of the dislocation 64, the oxide film 11 is locally thick (slightly raised) as described above, so that a crystal plane other than the (111) plane appears. According to the general theory of Si crystal growth, since the (111) plane has the slowest growth rate, the growth rate of polycrystalline silicon increases and rises only near the dislocations. Therefore, it is considered that a hillock can be formed at a position corresponding to the dislocation 64 on the surface of the polycrystalline silicon 12.
Thereafter, the position of the hillock is detected and recorded by a particle inspection apparatus (commercially available) that detects the scattered light of the laser beam. It is not always necessary to record an accurate position, and it is sufficient to know which semiconductor device exists, so that the resolution can be lowered so as to be suitable for image processing. A hillock of the aforementioned size can be detected relatively easily. By the image processing, a predetermined number of semiconductor devices (chips) having, for example, one or more hillocks are determined as defective products. If a desired yield rate cannot be obtained in the wafer, the processing may be stopped at this point.

Next, as in the Si wafer process, after activation of phosphorus by activation annealing, the polycrystalline silicon is patterned. Subsequently, PSG (Phospho Silicate Glass) and the like are deposited and reflowed to provide a contact hole for the source electrode in the PSG. Thereafter, nickel and titanium are deposited on the front surface and patterned. Subsequently, the front surface is protected with a resist, and the back surface deposits are removed after removing the back surface deposits in the same manner as in the Si wafer process (although the order is significantly different), and the back surface oxide film is then immersed in buffered hydrofluoric acid. Remove. Nickel and titanium are deposited and patterned as needed.
After removing the resist on the front surface, for example, heat treatment is performed at 1000 ° C., for example, in an Ar atmosphere to obtain ohmic contact between the SiC wafer and nickel / titanium. Similar to the Si wafer process, a contact hole for a gate pad (not shown in FIG. 1) is provided in PSG, and Al is sputtered on the front surface, followed by patterning. If necessary, an additional heat treatment is performed to complete the semiconductor device in the SiC wafer.
In the completed semiconductor device, even if hillocks were detected to some extent, many devices were operable within a short time. However, when an accelerated test is performed to check the reliability, in many semiconductor devices that detect hillocks, the gate insulating film 11 is clearly destroyed in a shorter time than a semiconductor device that does not detect any hillocks. Results were obtained. From this result, it was found that the semiconductor device at the position where the hillock was detected has a problem in reliability.

  Regarding the wafer process step according to the first embodiment described above, the work that is substantially increased in the dislocation detection step added to the conventional DMOSFET manufacturing step is to use the particle inspection apparatus after depositing polycrystalline silicon. Only the work to detect the position of hillocks using. That is, according to the first embodiment, dislocations in the SiC wafer can be easily detected (in the form of hillocks) during the wafer process, and the detection data and position data recorded in the particle inspection apparatus. A screening process for removing defective products based on the above can be used to facilitate incorporation into the wafer process by marking the wafer or the like.

Screening as in the first embodiment is effective when the semiconductor device (chip) size is small, but when the semiconductor device (chip) size is large, the current normal dislocation density level is accordingly high. It is often seen that no yield can be obtained. For example, in the case of a SiC DMOSFET having an active region of about 100 μm square, the yield when screening a semiconductor device that has been determined to be defective by detecting dislocations as in Example 1 may vary depending on the wafer. It is about 30 to 40%. In contrast, in the case of a SiC DMOSFET having an active region of about 300 μm square, the yield is almost 0% even with a SiC wafer having a dislocation density level quality similar to that described above.
Therefore, in the second embodiment, not only the semiconductor device (chip) in which dislocation is detected in the form of hillock as in the first embodiment is screened as a defect, but also the semiconductor device (chip) in which the dislocation is detected. A remedy process to make the product good. A specific example of applying this relief process will be described below. The cross-sectional view of the main part of the SiC DMOSFET according to the second embodiment is the same as FIG. The feature of the second embodiment is that the cell gate electrode 12 is processed so that an electric field that should originally be applied in the same way as other places is not applied to the gate insulating film 11 of the unit cell in the vicinity of the dislocation. It is to be. Specifically, it is a process of partially removing only the gate electrode of a cell in the vicinity where dislocation exists. If the gate electrode 12 is simply removed, the channel forming portion 13 is inverted due to the high voltage applied in the off state, and there is a problem that the channel forming portion 13 becomes conductive at a low applied voltage. Therefore, as shown in FIG. 2, which is a plan view of six unit cells, the n-type JFET region 9 is converted to the p-type JFET region 5-1 in a cell in the vicinity where dislocations are detected by detecting the hillock 19. Therefore, it is necessary to prevent the high voltage from reaching the channel forming portion 13. However, such a conversion to the p-type is accompanied by a demerit that the number of effective cells contributing to the current is reduced and the current capacity is reduced accordingly. Therefore, even when dislocations are detected in several cells, a design is made so that a large current capacity is obtained in the design stage of the semiconductor device so that a predetermined current capacity can be obtained in a desired yield in advance. It is preferable.

As described above, by removing the gate electrode of the dislocation detection cell and making the JFET region of the cell p-type, the semiconductor device (chip) is made non-functional by killing only that portion of the cell even if it includes dislocation. In this case, the current capacity is reduced by that amount, but adverse effects on the characteristics can be avoided and a good semiconductor device (chip) can be obtained. In addition, if the number of detected hillocks that perform the conversion to the p-type as described above is determined in advance, if the number of hillocks is smaller than that number, a part of normal cells that have not detected hillocks In addition, by performing the same treatment, the number of cells that actually operate in the semiconductor device to be manufactured can be made uniform, leading to a reduction in characteristic variation.
The method of the second embodiment is particularly effective in the case of a semiconductor device having a large current capacity and a large semiconductor device area. By the way, if a part of the gate electrode 12 is removed, the gate electrode 12 may be broken in the semiconductor device. Therefore, the cell arrangement is preferably such that the gate electrode 12 has a mesh shape. For example, the grid-like gate electrode 12 is used.
The manufacturing process of the DMOSFET in the second embodiment is the same as that in the first embodiment until the middle, but the steps before and after depositing polycrystalline silicon and detecting hillocks by the particle inspection apparatus are different. In Example 2, the thickness of the polycrystalline silicon is increased to about 1 μm in advance. This film thickness should be, for example, about half of the film thickness required for subsequent thermal oxidation and diversion to an ion implantation mask. The hillock detection position accuracy is a level necessary to determine a region to be subjected to the relief process, and may be about 2 to 5 μm, for example. In practice, a little more measurement accuracy will be required for image processing. For the wafer in which hillocks have been detected, polycrystalline silicon is thermally oxidized (or oxynitrided or nitrided) and converted to a SiO ₂ (or SiON, SiN) film. Thereafter, the converted SiO ₂ film is patterned in the JFET region 9 in the vicinity where the hillock is detected so that ion implantation for p-type conversion can be performed, and ion implantation is performed in the same manner as the body region 5. Although the use of polycrystalline silicon as a mask is not excluded, it is possible to increase the mask effect against implanted ions by converting to a SiO ₂ film, so the thickness of polycrystalline silicon should be reduced. There is an advantage that can be. By doing so, the JFET region 9 in the vicinity where the hillock is detected becomes a part of the p-type body region 5, and a high voltage does not reach the channel forming portion 13. FIG. 2 is a plan view of the SiO ₂ film removed thereafter. In FIG. 2, a hillock detection position 19 indicated by a circle is a portion (channel forming portion 13) of the body region 5 that is scheduled to face the gate electrode 12 in the future. At the hillock detection position 19, the adjacent JFET region 9 is converted to a p-type to form a part of the body region (5-1 in the figure). After removing the SiO ₂ film, activation annealing is performed to re-form the gate oxide film 11 and polycrystalline silicon, thereby completing the relief process.

Since dislocation may occur again by ion implantation and activation annealing during the relief process, the hillock inspection is performed again. If hillocks are generated again, screening is performed as in Example 1 or the hillock is again performed. It is preferable to perform a relief process as in the second embodiment. Subsequent steps are the same as those in the first embodiment except that, in patterning the polycrystalline silicon, the portion of the polycrystalline silicon to be the gate electrode 12 is removed in the vicinity where the hillock is first detected. FIG. 3 shows a plan view of the same position as in FIG. 2 in a state after patterning the gate electrode 12. Since the gate oxide film 11 is present below the gate electrode 12, the components positioned below the gate electrode 12 are outlined by broken lines. As shown in FIG. 3, the gate electrode 12 is originally formed so as to straddle the upper and lower cells in the drawing of FIG. A portion of the gate electrode 12 extending over the cell is removed.
By the way, in the above-mentioned relief process, it is necessary to perform photolithography corresponding to each wafer process twice (each patterning for ion implantation into the JFET region 9 and for the gate electrode 12). In stepper exposure, photolithography that requires a mask pattern that is not determined by changing the mask pattern for each wafer as described above seems unrealistic. For example, if electron beam direct exposure or laser light direct exposure is used, Since the pattern can be changed for each wafer, it can be realized relatively easily. Even in the case of stepper exposure, if several patterns of fields can be prepared on the reticle, they can be used for each wafer or shot. In this case, there is a drawback that the relief efficiency is lowered and the capacitance between the source and the drain is increased for the current capacity, but the equipment is not as expensive as the electron beam direct exposure, and the throughput is also higher than that of the electron beam direct exposure. There is also an advantage of high. In a semiconductor device (chip) having an active region of about 300 μm square, when the relief process as described above was performed for up to five hillock detection units per semiconductor device (chip), the yield was improved to about 10%. Similarly, when the relief process as described above was performed for up to 10 hillock detection units per semiconductor device (chip), the yield was improved to about 70%. It may seem that there are 10 places per semiconductor device, but when the cell pitch is 12 μm, there are 625 cells in one semiconductor device (chip), so the relief process is actually applied. The number of cells is only about 1.6% of the total.

  As described above, according to the second embodiment, since a relief process is performed on cells existing in the vicinity of dislocations detected in the form of hillocks, a semiconductor device (chip) having a large area can be obtained even when the dislocation density is high. It can be obtained with a high yield. Further, when there is a possibility that a new dislocation is generated during the relief process, the newly generated dislocation can be detected, and the above-described relief process can be added.

Example 3 uses polycrystalline silicon that has been subjected to the hillock detection process in order to form a breakdown voltage structure portion located in the central portion of the power semiconductor device and surrounding the active region through which the main current flows. Features a manufacturing method. In general, in a power semiconductor device, it is necessary to form an appropriate breakdown voltage structure in order to obtain a desired breakdown voltage. A cross-sectional view of this pressure-resistant structure is shown in FIG. Constituent elements similar to those in the first and second embodiments are denoted by the same reference numerals and redundant description is omitted. In FIG. 4, the left side is the end of the semiconductor device (chip) and the right side is the central direction with the active region which is an aggregate of cells. A plurality of p-type guard ring regions 28 a and 28 b having different doping amounts are provided on a part of the surface of the n-type drift layer 3.
In the third embodiment, two-stage p-type guard ring regions 28a and 28b in which the doping amount is decreased in order from the cell side are provided. The doping amount (dose amount) and the width of each region (the width in the direction from the cell side toward the end of the semiconductor device in the plane of the semiconductor device) are based on a desired breakdown voltage and an allowable manufacturing margin. This is a so-called design matter that should be changed. For example, in the case of 1.2 kV breakdown voltage, for example, the guard ring region 28a has a width of 25 μm and a dose amount of 4.8 × 10 ¹³ cm ⁻² , and the guard ring region 28b has a width of 25 μm and a dose amount, for example. 1.6 × 10 ¹³ cm ⁻² . The guard ring region is not limited to two stages, and may be further multi-staged.

Outside the guard ring regions 28a and 28b (on the chip end side), an n-type channel cut region 27 is provided to prevent the depletion layer from extending too far and reaching the end of the semiconductor device to deteriorate the breakdown voltage. The surface of the breakdown voltage structure is covered with a protective insulating film 29. The cell portion may have any structure, but for the sake of simplicity, the description will be continued by taking the DMOSFET shown in the first and second embodiments as an example.
A method for manufacturing the pressure resistant structure will be described. First, an n-type field stopping layer 2, a low-doping n-type drift layer 3 and the like are stacked on the bulk substrate 1 by, for example, epitaxial growth to form a SiC wafer. A mask pattern alignment marker (not shown in FIG. 4), an ion implantation region and a channel cut for forming a body region 5, a source contact region 6, a body contact region 7 and the like constituting each cell portion on the wafer. Region 27 is formed.
Next, the SiC wafer is thermally oxidized in an appropriate condition, for example, in a wet atmosphere at 1200 ° C. for 2 hours to form a thermal oxide film 29-1 having a thickness of about 50 nm on the entire front surface of the wafer. In the same manner as in the first or second embodiment, after depositing polycrystalline silicon 18 on the formed thermal oxide film, hillocks are detected, and the above-described screening or relief process is performed on the portion where hillocks are detected. .

However, when screening is performed as in Example 1, the thickness of the polycrystalline silicon 18 is increased to, for example, about 1 μm. This thickness needs to have a sufficient mask effect in the next ion implantation. The polycrystalline silicon 18 is selectively etched using an opening mask for forming the guard ring region 28a. Using the remaining polycrystalline silicon 18 as a mask, ion implantation for forming the guard ring region 28a is performed. The dose amount at this time is a dose amount obtained by subtracting a dose amount necessary for the guard ring region 28b from a dose amount necessary for the guard ring region 28a. For example, in the above-described example, the dose amount is (the dose amount of the guard ring region 28a 4.8 × 10 ¹³ cm ⁻² ) − (the dose amount of the guard ring region 28b 1.6 × 10 ¹³ cm ⁻² ) = 3. 2 × 10 ¹³ cm ⁻² . The state where this step is completed is shown in the cross-sectional view of the pressure-resistant structure portion in FIG.
Similarly, the polycrystalline silicon 18 is further selectively etched using an opening mask for forming the guard ring region 28b. Using the remaining polycrystalline silicon 18 as a mask, ion implantation for forming the guard ring region 28a and the guard ring region 28b is performed. The state where this step is completed is shown in the cross-sectional view of the pressure-resistant structure portion in FIG. If the guard ring has more stages, the same process may be repeated.

When ion implantation for forming the guard ring region is completed, the polycrystalline silicon 18 and the thermal oxide film 29-1 are removed, and activation annealing is performed on the ion implanted region. Since this activation annealing requires a high temperature of 1500 to 1800 ° C., the SiO ₂ film and polycrystalline silicon must be removed in advance. Thereafter, similar to the first and second embodiments, a gate insulating film, a gate electrode, and other structures necessary for the MOSFET are formed.
As described above, according to the third embodiment, in order to detect dislocations in the form of hillocks in the process of depositing and removing polycrystalline silicon, which is a mask material for forming each guard ring region, and in the wafer process. By making the polycrystalline silicon deposition and removal steps common, even when a dislocation detection step is added to the conventional normal wafer process, a substantial increase in work can be reduced.

The trench type MOSFET shown in the cross-sectional view of the main part of FIG. 8 showing the trench type SiC MOSFET according to the example 4 has an advantage that the conduction loss, that is, the on-resistance can be reduced correspondingly because there is no JFET region in the DMOSFET. The trench-type SiC MOSFET shown in FIG. 8 is a high-dope formed on each bulk substrate 1 having a high-doping n-type 4H-SiC (0001) _Si surface as a main surface (front surface) by epitaxial growth. A n-type field stopping layer 2, a low-doping n-type drift layer 3, an n-type current spreading layer 4, a p-type body region 5 and the like.
A part of the surface of the body region 5 has a source extension region 6-1 that is a high-dope n-type and a source contact region 6 that is a high-dope n-type. A trench 10 is provided that reaches the drift layer 3 from the surface of the source contact region 6 through the source extension region 6-1, the body region 5, and the current spreading layer 4. Of the wall surface of the trench 10, a gate electrode 12 is provided via a gate oxide film 11 on the body region 5, a portion of the source extension region 6-1 adjacent to the body region 5 and a portion in contact with the current spreading layer 4. ing.
In the trench 10, an interlayer insulating film 21 that is in contact with a part of the surface of the source extension region 6-1 and the source contact region 6 is formed above the gate electrode 12. The source electrode 23 is in ohmic contact with the main surface side of the source contact region 6, and the source electrode 23 covers the interlayer insulating film 21 and contacts the main surface of the source contact region 6 of the adjacent cell. Ohmic contact. A part of the source electrode 23 is in ohmic contact with the body contact region 7 which is formed on the surface of the body region 5 and has a high dopant p-type. A drain electrode 22 is provided on the back surface of the bulk substrate 1.

In FIG. 8, the thickness of the body contact region 7 is drawn to the same extent as the thickness of the source contact region 6. However, when the source extension region 6-1 is formed by ion implantation, the adjacent source extension region 6-1 is formed. In some cases, the resistance of the body region 5 sandwiched between increases, and the potential of the body region 5 becomes unstable. Therefore, if possible, it is preferable to reduce the resistance by ion-implanting aluminum or boron under the body contact region 7 to the same depth as the source extension region 6-1 (not shown). ).
The thickness and doping of each region are design items that should be appropriately determined according to the desired performance. For example, when the breakdown voltage is 1.2 kV, for example, the field stopping layer 2 has a donor density of 0.5 to 10 × 10 ¹⁷ cm ⁻³ and a film thickness of about 2 μm, and the drift layer 3 has a donor density of 1 × 10 ¹⁶ cm. ^-3 for a film thickness of about 13 μm, the current spreading layer 4 for a donor density of 1 × 10 ¹⁷ cm ⁻³ and a film thickness of about 0.4 μm, and the p-type body region 5 for an acceptor density of 2 × 10 ¹⁷ cm ⁻³ for a film thickness of about 2 .3 μm (depth from the surface to the lower end of the body region 5).
The cell pitch and the width of the trench depend on the accuracy of various processes in the wafer process. For example, the cell pitch is 8 μm and the trench width is 1 μm. The field stopping layer 2 and the current spreading layer 4 are not necessarily present. Since the quality of the SiC bulk substrate 1 is not necessarily sufficient, if the field stopping layer 2 exists, even if the depletion layer spreads over the entire drift layer 3 when a reverse voltage is applied, a high electric field at the end of the bulk substrate Therefore, it is preferable that the dielectric breakdown can be suppressed due to the low quality of the bulk substrate.

When the field stopping layer 2 does not exist, the field stopping layer 2 in the following description may be read as the upper end portion of the bulk substrate 1. Since the drift layer 3 has a relatively high resistance, in the ON state, the current flowing through the interface between the body region 5 and the gate insulating film 11, which is the side wall surface of the trench 10, flows only in the vicinity of the trench 10 in the drift layer 3. The flow may increase the on-resistance due to current concentration. However, the presence of the current spreading layer 4 is preferable because the current spreads over a wide region of the drift layer 3 and can suppress an increase in on-resistance due to current concentration. If the current spreading layer 4 does not exist, the current spreading layer 4 in the following description may be read as the upper end portion of the drift layer 3.
Although only one gate electrode is shown in FIG. 8, in the active region of a practical semiconductor device, many unit cells are repeated as in the first embodiment. Further, in the trench type MOSFET described below, the description of the present invention is omitted because the breakdown voltage structure is not particularly relevant. Of course, as illustrated in the third embodiment, the present invention may be applied before and after the pressure-resistant structure is formed.
By the way, it is known that an epitaxial growth layer formed on the bulk substrate 1 with a SiC wafer has a certain tendency in the propagation direction of dislocations as shown in FIG. In the SiC epitaxial growth layer 61, the threading screw dislocations, the threading edge dislocations 62, and the basal plane dislocations 63 easily propagate in parallel to the off direction and easily propagate in directions opposite to each other. Therefore, when the trench 10 is arranged so that the planar shape is a straight line, the longitudinal direction is parallel to the off direction (in FIG. 8, the off direction is the direction perpendicular to the paper surface), the trench 10 is formed on the gate insulating film 11. The possibility of dislocation contact is minimized. Incidentally, the angle θ formed by the surface of the SiC epitaxial growth layer 61 and the basal plane dislocation 63 is equal to the off angle.

According to the above explanation, it seems that there is no problem of deterioration of the reliability of the insulating film due to dislocation in the trench MOSFET. However, in practice, there is a possibility that a problem occurs in a place other than the gate insulating film 11. For example, with FIG. 8 as it is, there is a known problem that an excessive electric field is applied to the insulating film at the bottom of the trench 10 to cause destruction.
Therefore, it is necessary to appropriately protect the bottom of the trench 10. As is well known, as shown in FIG. 9, a buried p-type region 8 is provided at the bottom of the trench 10, and in this case, the DMOSFET JFET region and the buried p-type region 8 are arranged around the buried p-type region 8. Since a similar portion occurs, there is a problem that the conduction loss (ON resistance) increases as the cell pitch is reduced to increase the cell density.
As a countermeasure, as shown in FIG. 10, a structure is known in which the trench 10 has a depth reaching at least the field stopping layer 2 and a buried insulating film 15 is buried below the gate electrode 12. With this structure, a JFET region does not occur, and since only an electric field of the same level as that of the drift layer 3 is applied to the buried insulating film 15 according to electromagnetic laws, the buried insulating film 15 is destroyed by an excessive electric field. Don't worry.
However, in any of the trench gate structures of FIGS. 9 and 10, the drift layer 3 is provided on the insulating film 11 (corresponding to the buried insulating film 15 in the case of FIG. 10) immediately below the gate electrode 12 at the bottom of the trench 10. It is inevitable that an electric field of approximately the same level as is applied. When SiC is used, the electric field is about 2.5 MV / cm, which is substantially equal to the electric field applied to the gate insulating film 11 in the on state. Therefore, when the dislocation contacts the insulating film 11 or 15 immediately below the gate electrode 12, the reliability becomes a problem as with the gate insulating film 11. Therefore, even in the case of a trench MOSFET, it is meaningful to apply the present invention, and the effects of the present invention can be obtained.

A manufacturing method of this trench MOSFET will be described in detail below with reference to FIGS. 9 and 10 focusing on FIG. First, as shown in FIG. 8, a field stopping layer 2, a drift layer 3, a current spreading layer 4, and a body region 5 are sequentially formed on the bulk substrate 1 by epitaxial growth. Thereafter, using an appropriately patterned mask material, for example, a SiO ₂ film as a mask, the SiC wafer is etched by about 1 μm to form a mask alignment marker (not shown in FIGS. 8 to 10).
Subsequently, the SiC wafer is thermally oxidized in an appropriate condition, for example, in a wet atmosphere at 1200 ° C. for 2 hours to form a thermal oxide film having a thickness of about 50 nm on the entire surface of the SiC wafer. As in the first to third embodiments, after depositing polycrystalline silicon on the formed thermal oxide film, hillocks are detected. In this case, it is preferable that the thickness of the polycrystalline silicon is, for example, about half of the film thickness required for subsequent thermal oxidation and diversion to an ion implantation mask. The reason why the hillock needs to be detected at this point is that the trench 10 is formed through the source contact region 6, and high dose ion implantation and activation annealing are performed to form the source contact region 6. As a result, new high-density dislocations often occur, so that dislocations that contact the bottom surface of the trench 10 (and both ends in the longitudinal direction) may not be normally detected.

In the fourth embodiment, when a hillock is detected in a portion where the linear trench 10 is to be formed and an extension of the portion where the dislocation is likely to be propagated, screening is performed, or relief is performed as will be described later. The target of the process. As is apparent from FIG. 7 showing the propagation direction of dislocations in the epitaxially grown layer of the SiC wafer, when a commercially available 4 to 8 degree off substrate is used as the bulk substrate 1, the SiC formed on the bulk substrate 1 is used. In the epitaxial layer, basal plane dislocations have a wider propagation range than threading screw dislocations and threading edge dislocations. As a guide, a range of the depth of the trench 10 / tan θ (where θ is an off angle) may be detected on both sides of the trench 10 in the longitudinal direction.
Next, the polycrystalline silicon is thermally oxidized to SiO ₂ (SiON by oxynitridation, SiN by nitridation may be used, as in the relief process of Example 2, or the use of polycrystalline silicon as it is is not excluded. ) Convert to membrane. This SiO ₂ film is appropriately patterned and used as a mask for forming the body contact region 7. The implantation and activation annealing conditions are the same as those in the first embodiment. Subsequently, the source contact region 6 and the source extension region 6-1 are formed by ion implantation using an appropriately patterned mask material, for example, an SiO ₂ film as a mask. At this time, in the source contact region 6, phosphorus is ion-implanted so as to have a high ^doping (for example, 10 ²⁰ cm ^{−3 level} ) in order to obtain a good ohmic contact.

On the other hand, the source extension region 6-1 only needs to be functionally a low-resistance n-type, but the doping is controlled from the viewpoint of preventing new dislocations by ion implantation as described above. There must be. For this reason, it is preferable to use nitrogen with a small mass and small implantation damage, but phosphorus may be used. In other words, it is preferable to reduce the implantation speed and to implant the wafer in a heated state (for example, 500 ° C.) if possible, from the viewpoint of increasing the dose as much as possible within a dose range that does not cause dislocation. It is desirable to make the source extension region 6-1 thick so that the upper end of the gate electrode 12 will not be higher than the lower end of the source contact region 6 later. For example, when nitrogen is implanted at a maximum of 700 keV (divalent ions may be used in a general 400 keV implantation apparatus), the implantation depth can be slightly over 0.8 μm. The safe dose that does not substantially cause dislocation is, for example, about 2.5 × 10 ¹⁴ cm ⁻² (doping density is about 5 × 10 ¹⁸ cm ⁻³ ), depending on the implantation speed and the heating temperature. .
Thereafter, the mask is removed and activation annealing is performed. Next, a SiO ₂ film is deposited on the front surface of the wafer. Thereafter, a resist mask for forming a SiO ₂ film mask pattern for forming the trench 10 is formed by photolithography. If a hillock is detected and is to be relieved, it is only necessary not to provide a trench at that location. As the method, for example, in the case of electron beam direct exposure or laser beam direct exposure, it is only necessary to draw a corresponding pattern.

Incidentally, since the trench 10 has a straight planar shape on the surface of the SiC wafer, if a hillock is detected even at one location in the linear region, the entire trench is not formed. Therefore, in the case of a semiconductor device having the same area, it is preferable that the length of the trench is short and that a larger number of trenches are provided because the proportion of trenches that are not formed as a relief treatment can be reduced. Furthermore, since the trench 10 is along the off direction of the SiC wafer, according to this design guideline, the semiconductor device is preferably a semiconductor device whose outer shape is longer in the direction perpendicular to the direction parallel to the off direction of the SiC wafer. It turns out that.
In the fourth embodiment, if even one hillock is detected in the vicinity of a region where one trench 10 is to be formed, that trench will not be formed, so the resolution when detecting the hillock position is appropriate. Need to be high. For example, the resolution is 2 μm. At this time, since the trench may extend over adjacent pixels, a region having an area of about {(2 × pixel width) × (trench length + 2 × trench depth ÷ tan θ)} is actually applied to each trench. It becomes a hillock detection target. Instead of simply providing a trench, from the gate pad (not shown in FIGS. 8 to 10) to the vicinity of the first hillock detection position (similar to the above, up to trench depth ÷ tan θ). The trench 10 may be provided.

In forming the trench 10, in the case shown in FIG. 9, the depth of the trench 10 must be appropriately controlled in order to obtain a desired breakdown voltage. In the case as shown in FIG. 10, if the trench 10 reaches the field stopping layer 2, the theoretical breakdown voltage can be obtained, but if the trench 10 reaches the bulk substrate 1, basal plane dislocations are random in the bulk substrate 1. Since it is propagating in any direction, it cannot be screened or relieved by the method of the fourth embodiment, and must be avoided. Therefore, it is preferable to make the field stopping layer 2 thick to secure a manufacturing margin, but at the same time, it is preferable that the controllability of the depth of the trench 10 is also high.
The trench 10 is generally formed by dry etching. However, in order to improve the controllability of the depth at that time, it is necessary to improve the controllability of the width of the trench 10 as in the trench formation process in silicon. A commercially available SiC bulk substrate has large and non-uniform warping, and the unevenness in the substrate surface reaches a maximum of 10 to 30 μm or more. Even within one shot of the stepper, unevenness of several μm exists. Therefore, an exposure method with a shallow depth of focus such as a stepper cannot form a very fine width, for example, 1 μm or less with good controllability. From this viewpoint, electron beam direct exposure with a deep focal depth is suitable as an exposure apparatus for forming a trench forming resist pattern. The SiO ₂ film is patterned using the formed resist mask, and then the SiC wafer is dry-etched using the patterned SiO ₂ film as a mask to form the trench 10.

If the buried p-type region 8 is provided as shown in FIG. 9, ion implantation and activation annealing are performed after appropriately protecting the trench sidewall. At this time, it is preferable to perform a heat treatment for improving the surface properties in the trench, since there is no cusp-shaped portion on the inner surface of the trench and activation annealing is also performed. Instead of this process, when forming the trench 10 reaching the field stopping layer 2 as shown in FIG. 10, for example, a buried insulating film 15 is formed. Also in this case, before the buried insulating film 15 is formed, it is preferable to perform the heat treatment for improving the surface property in the trench in order to remove irregularities on the side wall of the trench 10 mainly caused by the photolithography process.
Subsequently, as in the silicon process, a gate insulating film 11 and a gate electrode 12 are formed as shown in FIG. Here, as described above, in order to avoid the occurrence of new dislocations by ion implantation, the upper end of the gate electrode 12 should not be higher than the lower end of the source contact region 6 as shown in FIG. Should. Thereafter, as in the first and second embodiments, the interlayer insulating film 21, the source electrode 23, the drain electrode 22, and a gate pad (not shown) are formed to complete the semiconductor device.
In any of the trench gate structures of FIG. 9 or FIG. 10, the completed semiconductor device can operate even if it is detected for a short time and is left without being repaired. Many were seen. However, when an acceleration test is performed to check reliability, many of the non-relieving semiconductor devices that detect hillocks are clearly shorter in the bottom of the trench 10 than the semiconductor devices that do not detect any hillocks. The insulating film (in the case of FIG. 10, the buried insulating film 15) was destroyed and was not put into practical use.

In the case of the structure of FIG. 10, the yield of the semiconductor device subjected to the relief process will be described. In a trench MOSFET semiconductor device having an active area having an effective area of 1 mm ² , for example, the length of the trench (that is, the size of the semiconductor device in the off direction) can be 1000 μm, and the length in the vertical direction can be 1000 μm. . However, in such a design of the outer shape of the semiconductor device, even if a maximum of 20% of all the trenches in one semiconductor device is relieved, at the current SiC wafer quality (dislocation density quality) level, the hillock detection frequency is called The yield in terms of meaning (non-defective product rate) was almost 0%. On the other hand, when the length of the trench is 400 μm and the length perpendicular to the trench is 2500 μm, the yield is improved to about 15%. Furthermore, when the length of the trench is 250 μm and the length in the vertical direction is 4000 μm, the yield is improved to about 90%. Thus, a semiconductor device design having a trench length, that is, a length perpendicular to the off-direction semiconductor device size, is more advantageous in terms of yield.
Of the above steps, the difference from the conventional trench MOSFET manufacturing step is that the step of forming the SiO ₂ film mask for ion implantation for the body contact 7 is not simply depositing the SiO ₂ film, but a polycrystal. After the silicon is deposited, it is inspected using a particle inspection apparatus, the position of hillocks is detected, and the process of thermal oxidation is merely replaced. That is, according to the fourth embodiment, dislocations in the SiC wafer can be easily detected (in the form of hillocks) during the wafer process, and can be used for screening. Also, if photolithography at the time of trench formation is performed by electron beam exposure instead of a stepper, a relief process can be performed without significantly increasing the number of processes instead of screening, so that the dislocation density is high. Even in this case, a semiconductor device having a large area can be obtained with a high yield.

  The embodiments described above are merely examples, and the scope of application of the present invention is not limited to the embodiments described above. In particular, in each of the first to fourth embodiments described above, a semiconductor device in which the reliability of the gate insulating film becomes a problem mainly due to dislocation is taken up. It will be apparent to those skilled in the art that, when it becomes clear, it is possible to screen a defective withstand voltage by applying the present invention. Although the pn diode and the Schottky diode do not have polycrystalline silicon as a constituent element, as described in Examples 3 and 4 above, the hillock-inspected polycrystalline silicon is directly or, for example, oxidized, For example, since it can be used as a mask material, the advantage of the present invention can be enjoyed without significantly increasing the number of steps.

Sectional drawing of the principal part of DMOSFET concerning Example 1 and Example 2 is shown. In Example 2, it is a top view which shows the state which converted a part of JFET area | region 9 into the p-type. In Example 2, it is a top view which shows the state which removed a part of gate electrode 12. FIG. Sectional drawing of the principal part of the example of the pressure | voltage resistant structure part concerning Example 3 is shown. In Example 3, the principal part sectional drawing immediately after finishing the ion implantation for the guard ring area | region 28a is shown. In Example 3, the principal part sectional drawing immediately after finishing the ion implantation for the guard ring area | regions 28a and 28b is shown. It is the top view and sectional drawing which show the propagation direction of the dislocation in the epitaxial growth layer of a SiC wafer. FIG. 10 is a sectional view of the main part of a trench MOSFET according to Example 4; FIG. 10 is a cross-sectional view of a main part of a modification of a trench type MOSFET according to Example 4; FIG. 10 is a cross-sectional view of a main part of another modification of the trench MOSFET according to the fourth embodiment. It is an expanded sectional view of the hillock part of the SiC wafer which has a thermal oxide film and polycrystalline silicon formed in the surface, and has a dislocation.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Bulk substrate 2 Field stopping layer 3 Drift layer 4 Current spreading layer 5 Body region 5-1 JFET region converted into p-type 6 Source contact region 6-1 Source extension region 7 Body contact region 8 Buried p-type region 9 JFET Region 10 Trench 11 Gate insulating film, gate oxide film, oxide film 12 Gate electrode 13 Channel forming part 15 Embedded insulating film 18 Polycrystalline silicon 19 Hillock detection position 21 Interlayer insulating film 22 Drain electrode 23 Source electrode 24 Abnormal convex part 27 Channel Cut region 28a Guard ring region 28b Guard ring region 29 Protective insulating film 29-1 Thermal oxide film 61 Epitaxial growth layer 62 Through screw dislocation, through edge dislocation 63 Basal plane dislocation

Claims (14)

After the silicon carbide semiconductor wafer whose principal surface is a (0001) _Si surface is thermally oxidized, polycrystalline silicon is deposited, hillocks appearing on the surface of the polycrystalline silicon are regarded as dislocations, and the presence or absence of dislocations is detected. A method for detecting dislocations in a silicon carbide semiconductor wafer, characterized by specifying a detection position in the case. 2. The detection of the presence / absence of dislocations and the detection position in the presence of dislocations are specified by irradiating the surface of the polycrystalline silicon with laser light and image-processing the scattered light image. Dislocation detection method in silicon carbide semiconductor wafer. After the silicon carbide semiconductor wafer whose principal surface is a (0001) _Si surface is thermally oxidized, polycrystalline silicon is deposited, hillocks appearing on the surface of the polycrystalline silicon are regarded as dislocations, and the presence or absence of dislocations is detected. A method of manufacturing a silicon carbide semiconductor device, comprising a dislocation detection step of specifying a detection position in the case. 4. The laser light is irradiated on the surface of the polycrystalline silicon, and the scattered light image is subjected to image processing, thereby detecting the presence / absence of the dislocation and specifying the detection position when the dislocation is present. A method for manufacturing a silicon carbide semiconductor device. 5. The silicon carbide semiconductor device formed on the basis of the silicon carbide semiconductor wafer, at least a part of the polycrystalline silicon deposited for observing the surface is a constituent element of the silicon carbide semiconductor device. The manufacturing method of the silicon carbide semiconductor device of description. A component of a silicon carbide semiconductor device in which at least a part of an insulating film obtained by thermally oxidizing or nitriding the polycrystalline silicon deposited for observing the surface is formed based on the silicon carbide semiconductor wafer; 5. The method for manufacturing a silicon carbide semiconductor device according to claim 3, wherein the silicon carbide semiconductor device is manufactured. 7. The silicon carbide semiconductor according to claim 6, wherein at least a part of the silicon oxide film formed by the thermal oxidation is a component of a silicon carbide semiconductor device formed on the basis of the silicon carbide semiconductor wafer. Device manufacturing method. The silicon carbide semiconductor wafer is selectively provided on a first conductivity type withstand voltage layer, a second conductivity type body region selectively provided on one main surface of the withstand voltage layer, and a surface layer of the body region. A source region of the first conductivity type, a gate electrode placed on the surface of the body region sandwiched between the surface layer of the source region and the surface layer of the breakdown voltage layer via an insulating film, the surface of the body region, 6. An insulated gate semiconductor device comprising: a surface electrode that is in ohmic contact with the surface of the source region in common; and a back electrode that is in ohmic contact with the other main surface of the breakdown voltage layer. The silicon carbide semiconductor device according to claim 7. After the step of detecting the presence or absence of dislocations and specifying the detection position in the presence of dislocations, the step of converting the surface layer of the first conductivity type withstand voltage layer adjacent to the detection position of the dislocations to the second conductivity type, and The method for manufacturing a silicon carbide semiconductor device according to claim 8, further comprising: removing a gate electrode on the surface of the body region in the vicinity of a dislocation detection position. A step of re-detecting newly generated dislocations after the step of converting the surface layer of the first conductivity type withstand voltage layer to the second conductivity type and the step of removing the gate electrode on the surface of the body region; A method for manufacturing a silicon carbide semiconductor device according to claim 9. After the step of detecting the presence / absence of dislocations and specifying the detection position when dislocations are present, the silicon carbide semiconductor device is a trench type, and the trench gate has a trench pattern that does not include a trench in the vicinity of the dislocations specifying the detection position. The method for manufacturing a silicon carbide semiconductor device according to claim 8, wherein a step of providing a structure is performed. 12. The carbonization according to claim 11, further comprising the step of detecting again a newly generated dislocation after the step of providing a trench gate structure with a trench pattern not including a trench in the vicinity of the dislocation whose detection position is specified. A method for manufacturing a silicon semiconductor device. The method for manufacturing a silicon carbide semiconductor device according to claim 11, wherein a planar shape of the trench formed on the surface of the silicon carbide wafer is a shape parallel to an off direction of the silicon carbide semiconductor wafer. The silicon carbide semiconductor device having a planar trench parallel to the off direction of the silicon carbide semiconductor wafer is perpendicular to the off direction of the silicon carbide semiconductor wafer than the length of the silicon carbide semiconductor wafer in the direction parallel to the off direction. 14. The method for manufacturing a silicon carbide semiconductor device according to claim 13, wherein the length in the direction is made longer.

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