[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

JP2018056304A - Switching device and manufacturing method - Google Patents

Switching device and manufacturing method Download PDF

Info

Publication number
JP2018056304A
JP2018056304A JP2016190035A JP2016190035A JP2018056304A JP 2018056304 A JP2018056304 A JP 2018056304A JP 2016190035 A JP2016190035 A JP 2016190035A JP 2016190035 A JP2016190035 A JP 2016190035A JP 2018056304 A JP2018056304 A JP 2018056304A
Authority
JP
Japan
Prior art keywords
trench
region
semiconductor region
insulating layer
contact
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2016190035A
Other languages
Japanese (ja)
Inventor
広和 藤原
Hirokazu Fujiwara
広和 藤原
竹内　有一
Yuichi Takeuchi
有一 竹内
成雅 副島
Shigemasa Soejima
成雅 副島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Denso Corp
Toyota Motor Corp
Toyota Central R&D Labs Inc
Original Assignee
Denso Corp
Toyota Motor Corp
Toyota Central R&D Labs Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Denso Corp, Toyota Motor Corp, Toyota Central R&D Labs Inc filed Critical Denso Corp
Priority to JP2016190035A priority Critical patent/JP2018056304A/en
Priority to US15/664,379 priority patent/US9954096B2/en
Publication of JP2018056304A publication Critical patent/JP2018056304A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H01L29/0623—Buried supplementary region, e.g. buried guard ring
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/66704—Lateral DMOS transistors, i.e. LDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/7825—Lateral DMOS transistors, i.e. LDMOS transistors with trench gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

PROBLEM TO BE SOLVED: To reduce loss when a switching device is turned on.SOLUTION: A switching device includes: a semiconductor substrate; a trench provided on an upper surface of the semiconductor substrate; a conductive layer extended along a longitudinal direction so as to contact with a bottom surface of the trench; a bottom insulation layer covering the upper surface of the conductive layer; a gate insulation layer covering a side surface of the trench; and a gate electrode that is arranged in an inner part of the trench and is insulated from the semiconductor substrate and the conductive layer. The semiconductor substrate includes: a first semiconductor region of a first conductive type contacting to the gate insulation layer; a body region of a second conductive type contacting to the gate insulation layer on a lower side of a first conductive region; a second semiconductor region of the first conductive type contacting to the gate insulation layer on the lower side of the body region; a bottom semiconductor region of the second conductive type extended along the longitudinal direction of the trench so as to contact with the conductive layer; a connection semiconductor region of the second conductive type connected to the body region and the bottom semiconductor region.SELECTED DRAWING: Figure 3

Description

本明細書に開示の技術は、スイッチング装置とその製造方法に関する。   The technology disclosed in the present specification relates to a switching device and a manufacturing method thereof.

特許文献１に、トレンチ内に配置されたゲート電極を備えるスイッチング装置が開示されている。このスイッチング装置は、ｎ型のソース領域とｐ型のボディ領域とｎ型のドリフト領域を有する。ソース領域、ボディ領域及びドリフト領域は、トレンチの側面においてゲート絶縁層に接している。また、このスイッチング装置は、トレンチの底面に接するｐ型の底部半導体領域を有している。底部半導体領域は、トレンチの長手方向に沿って伸びている。さらに、このスイッチング装置は、トレンチの側面の一部に沿って伸びるｐ型の接続半導体領域を有している。接続半導体領域は、ボディ領域と底部半導体領域に接続されている。   Patent Document 1 discloses a switching device including a gate electrode disposed in a trench. This switching device has an n-type source region, a p-type body region, and an n-type drift region. The source region, the body region, and the drift region are in contact with the gate insulating layer on the side surface of the trench. The switching device also has a p-type bottom semiconductor region in contact with the bottom surface of the trench. The bottom semiconductor region extends along the longitudinal direction of the trench. Further, this switching device has a p-type connection semiconductor region extending along a part of the side surface of the trench. The connection semiconductor region is connected to the body region and the bottom semiconductor region.

このスイッチング装置がオフするときには、底部半導体領域からドリフト領域に空乏層が伸びる。この空乏層によって、底部半導体領域の近傍（すなわち、トレンチの底部近傍）における電界集中が抑制される。   When the switching device is turned off, a depletion layer extends from the bottom semiconductor region to the drift region. This depletion layer suppresses electric field concentration in the vicinity of the bottom semiconductor region (that is, in the vicinity of the bottom of the trench).

ゲート電極に所定の電位が印加されると、ゲート絶縁層近傍のボディ領域にチャネルが形成される。これによって、ドリフト領域からソース領域に主電流が流れる。つまり、スイッチング装置がオンする。また、スイッチング装置がオンするときには、接続半導体領域を介してボディ領域から底部半導体領域に電荷が供給される。底部半導体領域に電荷が供給されると、底部半導体領域からドリフト領域に広がっていた空乏層が底部半導体領域に向かって収縮する。このため、スイッチング装置がオンするときにドリフト領域の抵抗が低下する。したがって、主電流が低損失でドリフト領域を流れることができる。   When a predetermined potential is applied to the gate electrode, a channel is formed in the body region near the gate insulating layer. As a result, a main current flows from the drift region to the source region. That is, the switching device is turned on. Further, when the switching device is turned on, charges are supplied from the body region to the bottom semiconductor region via the connection semiconductor region. When charge is supplied to the bottom semiconductor region, the depletion layer that has spread from the bottom semiconductor region to the drift region contracts toward the bottom semiconductor region. For this reason, the resistance of the drift region decreases when the switching device is turned on. Therefore, the main current can flow through the drift region with low loss.

スイッチング装置がオンしているときに、接続半導体領域が設けられている範囲には主電流が流れない。したがって、主電流の経路を広く確保するために、接続半導体領域は、トレンチの側面の一部にのみ形成される。   When the switching device is on, the main current does not flow in the range where the connection semiconductor region is provided. Therefore, in order to ensure a wide path for the main current, the connection semiconductor region is formed only on a part of the side surface of the trench.

特開２０１３−２５８３６９号公報JP 2013-258369 A

底部半導体領域は、トレンチの長手方向に沿って伸びている。また、接続半導体領域は、トレンチの側面の一部のみに設けられている。したがって、底部半導体領域の一部（以下、特定部分という）は、接続半導体領域から長距離離れた位置に配置されている。このため、底部半導体領域の特定部分と接続半導体領域の間に比較的高い抵抗が存在する。したがって、スイッチング装置がオンするときに、接続半導体領域から底部半導体領域に供給された電荷が特定部分にまで到達するのに時間がかかり、特定部分の周囲の空乏層の収縮が遅くなる。その結果、特定部分の周囲のドリフト領域の抵抗が低下し難く、この部分で損失が高くなる。したがって、本明細書では、オンするときの損失をより低減することが可能なスイッチング装置を提供する。   The bottom semiconductor region extends along the longitudinal direction of the trench. Further, the connection semiconductor region is provided only in a part of the side surface of the trench. Therefore, a part of the bottom semiconductor region (hereinafter referred to as a specific portion) is arranged at a position that is separated from the connection semiconductor region by a long distance. For this reason, a relatively high resistance exists between a specific portion of the bottom semiconductor region and the connection semiconductor region. Therefore, when the switching device is turned on, it takes time for the charge supplied from the connection semiconductor region to the bottom semiconductor region to reach the specific portion, and the contraction of the depletion layer around the specific portion is delayed. As a result, the resistance of the drift region around the specific portion is difficult to decrease, and the loss increases in this portion. Therefore, the present specification provides a switching device that can further reduce loss when turned on.

本明細書が開示するスイッチング装置は、半導体基板と、前記半導体基板の上面に設けられたトレンチと、前記トレンチの底面に接するように前記トレンチの長手方向に沿って伸びる導体層と、前記導体層の上面を覆う底部絶縁層と、前記底部絶縁層よりも上側の前記トレンチの側面を覆うゲート絶縁層と、前記トレンチの内部に配置されており、前記底部絶縁層及び前記ゲート絶縁層によって前記半導体基板及び前記導体層から絶縁されているゲート電極を有する。前記半導体基板が、前記ゲート絶縁層に接する第１導電型の第１半導体領域と、前記第１半導体領域の下側で前記ゲート絶縁層に接する第２導電型のボディ領域と、前記ボディ領域の下側で前記ゲート絶縁層に接するとともに前記ボディ領域によって前記第１半導体領域から分離されている第１導電型の第２半導体領域と、前記導体層に接するように前記トレンチの長手方向に沿って伸びるとともに前記第２半導体領域に接する第２導電型の底部半導体領域と、前記トレンチの側面の一部に沿って伸びるとともに前記ボディ領域と前記底部半導体領域に接続されている第２導電型の接続半導体領域を有する。   The switching device disclosed in this specification includes a semiconductor substrate, a trench provided on an upper surface of the semiconductor substrate, a conductor layer extending along a longitudinal direction of the trench so as to be in contact with a bottom surface of the trench, and the conductor layer A bottom insulating layer covering the upper surface of the semiconductor substrate, a gate insulating layer covering a side surface of the trench above the bottom insulating layer, and an inside of the trench, and the semiconductor is formed by the bottom insulating layer and the gate insulating layer. A gate electrode insulated from the substrate and the conductor layer; A first conductive type first semiconductor region in contact with the gate insulating layer; a second conductive type body region in contact with the gate insulating layer below the first semiconductor region; and A second semiconductor region of a first conductivity type that is in contact with the gate insulating layer on the lower side and is separated from the first semiconductor region by the body region, and along a longitudinal direction of the trench so as to be in contact with the conductor layer A second conductivity type bottom semiconductor region extending and in contact with the second semiconductor region; and a second conductivity type connection extending along a part of a side surface of the trench and connected to the body region and the bottom semiconductor region It has a semiconductor region.

なお、第１導電型と第２導電型の一方がｎ型であり、他方がｐ型である。   One of the first conductivity type and the second conductivity type is n-type, and the other is p-type.

このスイッチング装置は、トレンチの底部に接するようにトレンチの長手方向に沿って伸びる導体層を有している。また、底部半導体領域が、導体層に接するようにトレンチの長手方向に沿って伸びている。導体層の抵抗が低いので、スイッチング素子がオンするときに接続半導体領域から供給される電荷が、導体層を介してトレンチの長手方向に高速で移動することができる。このため、接続半導体領域から供給される電荷が、上述した特定部分（すなわち、接続半導体領域から長距離離れた部分の底部半導体領域）へ短時間で到達することができる。つまり、接続半導体領域の全体に短時間で電荷が供給される。したがって、接続半導体領域の全体の周囲で空乏層が高速で収縮し、接続半導体領域の全体の周囲のドリフト領域の抵抗が短時間で低下する。このため、ターンオン時の損失が抑制される。   This switching device has a conductor layer extending along the longitudinal direction of the trench so as to be in contact with the bottom of the trench. The bottom semiconductor region extends along the longitudinal direction of the trench so as to contact the conductor layer. Since the resistance of the conductor layer is low, the charge supplied from the connection semiconductor region when the switching element is turned on can move at high speed in the longitudinal direction of the trench through the conductor layer. For this reason, the electric charge supplied from the connection semiconductor region can reach the above-described specific portion (that is, the bottom semiconductor region at a long distance from the connection semiconductor region) in a short time. That is, charge is supplied to the entire connection semiconductor region in a short time. Therefore, the depletion layer contracts at high speed around the entire connection semiconductor region, and the resistance of the drift region around the entire connection semiconductor region decreases in a short time. For this reason, the loss at the time of turn-on is suppressed.

また、本明細書は、スイッチング装置の好適な製造方法を提供する。この製造方法は、半導体基板の上面にトレンチを形成する工程と、前記トレンチの底面が露出するように前記トレンチの側面を覆う保護膜を成膜する工程と、前記保護膜と前記トレンチの底面を覆う金属層を形成する工程と、前記金属層を加熱することによって前記金属層と前記トレンチの底面が合金化した導体層を形成する工程と、前記導体層が残存するように前記保護膜を覆う前記金属層をエッチングにより除去する工程と、前記導体層と前記トレンチを用いてスイッチング装置を完成させる工程を有する。前記スイッチング装置が、前記導体層の上面を覆う底部絶縁層と、前記底部絶縁層よりも上側の前記トレンチの側面を覆うゲート絶縁層と、前記トレンチの内部に配置されているとともに前記底部絶縁層及び前記ゲート絶縁層によって前記半導体基板及び前記導体層から絶縁されているゲート電極と、前記ゲート絶縁層に接する第１導電型の第１半導体領域と、前記第１半導体領域の下側で前記ゲート絶縁層に接する第２導電型のボディ領域と、前記ボディ領域の下側で前記ゲート絶縁層に接するとともに前記ボディ領域によって前記第１半導体領域から分離されている第１導電型の第２半導体領域と、前記導体層に接するように前記トレンチの長手方向に沿って伸びるとともに前記第２半導体領域に接する第２導電型の底部半導体領域と、前記トレンチの側面の一部に沿って伸びるとともに前記ボディ領域と前記底部半導体領域に接続されている第２導電型の接続半導体領域を有する。   The present specification also provides a preferred method for manufacturing a switching device. The manufacturing method includes forming a trench on an upper surface of a semiconductor substrate, forming a protective film covering a side surface of the trench so that a bottom surface of the trench is exposed, and forming the protective film and the bottom surface of the trench. Forming a covering metal layer; heating the metal layer to form a conductor layer in which the bottom surface of the metal layer and the trench is alloyed; and covering the protective film so that the conductor layer remains A step of removing the metal layer by etching, and a step of completing a switching device using the conductor layer and the trench. The switching device is disposed inside the trench and the bottom insulating layer, the bottom insulating layer covering the top surface of the conductor layer, the gate insulating layer covering the side surface of the trench above the bottom insulating layer, And a gate electrode insulated from the semiconductor substrate and the conductor layer by the gate insulating layer, a first semiconductor region of a first conductivity type in contact with the gate insulating layer, and the gate below the first semiconductor region A body region of a second conductivity type in contact with the insulating layer, and a second semiconductor region of the first conductivity type in contact with the gate insulating layer below the body region and separated from the first semiconductor region by the body region A bottom semiconductor region of a second conductivity type that extends along the longitudinal direction of the trench so as to contact the conductor layer and that contacts the second semiconductor region; Serial having said connection semiconductor region of a second conductivity type which is connected to the body region and the bottom semiconductor region with extending along a portion of the side surface of the trench.

なお、スイッチング装置を完成させる工程の一部（例えば、第１半導体領域、ボディ領域等の半導体領域の形成工程）を、金属層をエッチングする工程よりも前の任意のタイミング（例えば、トレンチを形成する工程の前）で行ってもよい。   Note that a part of the process for completing the switching device (for example, a process for forming a semiconductor region such as the first semiconductor region or the body region) is performed at an arbitrary timing (for example, a trench is formed before the process for etching the metal layer). May be performed in the step before).

この製造方法では、金属層を形成する工程において、トレンチの底面では金属層と半導体基板が接触し、トレンチの側面では保護膜と金属層が接触するように金属層が形成される。その後、金属層を加熱すると、トレンチの底面において金属層とトレンチの底面（すなわち、半導体基板を構成する半導体材料）が合金化する。これによって、トレンチの底面に導体層が形成される。トレンチの側面では、金属層が半導体基板に接していないので、合金が形成されない。その後、合金化しなかった金属層を除去することで、導体層がトレンチの底部に残存する。この方法によれば、トレンチの底部に導体層を容易に形成することができる。   In this manufacturing method, in the step of forming the metal layer, the metal layer is formed such that the metal layer and the semiconductor substrate are in contact with each other on the bottom surface of the trench, and the protective film and the metal layer are in contact with each other on the side surface of the trench. Thereafter, when the metal layer is heated, the metal layer and the bottom surface of the trench (that is, the semiconductor material constituting the semiconductor substrate) are alloyed at the bottom surface of the trench. As a result, a conductor layer is formed on the bottom surface of the trench. On the side surface of the trench, the metal layer is not in contact with the semiconductor substrate, so that no alloy is formed. Thereafter, by removing the metal layer that has not been alloyed, the conductor layer remains at the bottom of the trench. According to this method, the conductor layer can be easily formed at the bottom of the trench.

実施形態のＭＯＳＦＥＴの平面図。The top view of MOSFET of an embodiment. 図１のＩＩ―ＩＩ線における断面図。Sectional drawing in the II-II line | wire of FIG. 図１のＩＩＩ―ＩＩＩ線における断面図。Sectional drawing in the III-III line of FIG. トレンチ形成前の半導体基板の断面図。Sectional drawing of the semiconductor substrate before trench formation. トレンチ形成後の半導体基板の断面図。Sectional drawing of the semiconductor substrate after trench formation. 酸化膜形成後の半導体基板の断面図。Sectional drawing of the semiconductor substrate after oxide film formation. 酸化膜エッチング後の半導体基板の断面図。Sectional drawing of the semiconductor substrate after an oxide film etching. 底部半導体領域形成後の半導体基板の断面図。Sectional drawing of the semiconductor substrate after bottom part semiconductor region formation. 金属層形成後の半導体基板の断面図。Sectional drawing of the semiconductor substrate after metal layer formation. 合金化処理後の半導体基板の断面図。Sectional drawing of the semiconductor substrate after alloying process. 金属層及び酸化膜除去後の半導体基板の断面図。Sectional drawing of the semiconductor substrate after a metal layer and an oxide film removal. 底部絶縁層形成後の半導体基板の断面図。Sectional drawing of the semiconductor substrate after bottom part insulating layer formation. 接続半導体領域の位置が異なる例のＭＯＳＦＥＴの平面図。The top view of MOSFET of the example from which the position of a connection semiconductor region differs. 図１３のＸＩＶ―ＸＩＶ線における断面図。Sectional drawing in the XIV-XIV line | wire of FIG.

図１〜３は、実施形態のＭＯＳＦＥＴ１０を示している。図２、３に示すように、ＭＯＳＦＥＴ１０は、半導体基板１２と、電極、絶縁層等を備えている。なお、図１では、図の見易さのため、半導体基板１２の上面１２ａ上の電極、絶縁層の図示を省略している。以下では、半導体基板１２の上面１２ａと平行な一方向をｘ方向といい、上面１２ａに平行でｘ方向に直交する方向をｙ方向といい、半導体基板１２の厚み方向をｚ方向という。   1-3 have shown MOSFET10 of embodiment. As shown in FIGS. 2 and 3, the MOSFET 10 includes a semiconductor substrate 12, an electrode, an insulating layer, and the like. In FIG. 1, illustration of electrodes and insulating layers on the upper surface 12 a of the semiconductor substrate 12 is omitted for easy viewing. Hereinafter, one direction parallel to the upper surface 12a of the semiconductor substrate 12 is referred to as an x direction, a direction parallel to the upper surface 12a and orthogonal to the x direction is referred to as a y direction, and a thickness direction of the semiconductor substrate 12 is referred to as a z direction.

半導体基板１２は、ＳｉＣにより構成されている。図２に示すように、半導体基板１２の上面１２ａには、複数のトレンチ２２が設けられている。図１に示すように、各トレンチ２２は、ｙ方向に直線状に長く伸びている。複数のトレンチ２２は、ｘ方向に間隔を開けて配列されている。図２、３に示すように、各トレンチ２２の内部に、導体層４０、底部絶縁層２４、ゲート絶縁層２５及びゲート電極２６が配置されている。   The semiconductor substrate 12 is made of SiC. As shown in FIG. 2, a plurality of trenches 22 are provided on the upper surface 12 a of the semiconductor substrate 12. As shown in FIG. 1, each trench 22 extends linearly in the y direction. The plurality of trenches 22 are arranged at intervals in the x direction. As shown in FIGS. 2 and 3, the conductor layer 40, the bottom insulating layer 24, the gate insulating layer 25, and the gate electrode 26 are disposed inside each trench 22.

図２、３に示すように、導体層４０は、トレンチ２２の底面上に設けられている。導体層４０は、トレンチ２２の底面に接している。図３に示すように、導体層４０は、トレンチ２２の長手方向（すなわち、ｙ方向）に沿って長く伸びている。導体層４０は、トレンチ２２の長手方向において、トレンチ２２の一方の端部２２ａ近傍の位置から他方の端部２２ｂ近傍の位置まで伸びている。導体層４０は、金属化合物（例えば、ニッケルシリサイド）により構成されている。   As shown in FIGS. 2 and 3, the conductor layer 40 is provided on the bottom surface of the trench 22. The conductor layer 40 is in contact with the bottom surface of the trench 22. As shown in FIG. 3, the conductor layer 40 extends long along the longitudinal direction of the trench 22 (that is, the y direction). The conductor layer 40 extends in the longitudinal direction of the trench 22 from a position near one end 22a of the trench 22 to a position near the other end 22b. The conductor layer 40 is made of a metal compound (for example, nickel silicide).

底部絶縁層２４は、トレンチ２２の底部に配置されている。底部絶縁層２４は、導体層４０の上面を覆っている。また、底部絶縁層２４は、トレンチ２２の底面近傍において、トレンチ２２の側面を覆っている。底部絶縁層２４は、トレンチ２２の深さ方向に厚く形成されている。底部絶縁層２４は、酸化シリコンにより構成されている。   The bottom insulating layer 24 is disposed at the bottom of the trench 22. The bottom insulating layer 24 covers the upper surface of the conductor layer 40. The bottom insulating layer 24 covers the side surface of the trench 22 in the vicinity of the bottom surface of the trench 22. The bottom insulating layer 24 is formed thick in the depth direction of the trench 22. The bottom insulating layer 24 is made of silicon oxide.

ゲート絶縁層２５は、底部絶縁層２４の上部に位置するトレンチ２２の側面を覆っている。ゲート絶縁層２５は、酸化シリコンにより構成されている。   The gate insulating layer 25 covers the side surface of the trench 22 located above the bottom insulating layer 24. The gate insulating layer 25 is made of silicon oxide.

ゲート電極２６は、底部絶縁層２４の上部に配置されている。すなわち、ゲート電極２６とトレンチ２２の底面の間の絶縁層が、底部絶縁層２４である。また、ゲート電極２６とトレンチ２２の側面の間の絶縁層が、ゲート絶縁層２５である。ゲート電極２６は、ゲート絶縁層２５と底部絶縁層２４によって半導体基板１２から絶縁されている。また、ゲート電極２６は、ゲート絶縁層２５と底部絶縁層２４によって導体層４０から絶縁されている。ゲート電極２６の上面は、層間絶縁膜２８によって覆われている。   The gate electrode 26 is disposed on the bottom insulating layer 24. That is, the insulating layer between the gate electrode 26 and the bottom surface of the trench 22 is the bottom insulating layer 24. The insulating layer between the gate electrode 26 and the side surface of the trench 22 is the gate insulating layer 25. The gate electrode 26 is insulated from the semiconductor substrate 12 by the gate insulating layer 25 and the bottom insulating layer 24. The gate electrode 26 is insulated from the conductor layer 40 by the gate insulating layer 25 and the bottom insulating layer 24. The upper surface of the gate electrode 26 is covered with an interlayer insulating film 28.

ゲート絶縁層２５の厚み（すなわち、トレンチ２２の側面とゲート電極２６の側面の間の間隔）は、底部絶縁層２４の厚み（すなわち、底部絶縁層２４の上面と下面の間の幅（言い換えると、ゲート電極２６の下端とトレンチ２２の底面の間の間隔））よりも薄い。   The thickness of the gate insulating layer 25 (that is, the distance between the side surface of the trench 22 and the side surface of the gate electrode 26) is the thickness of the bottom insulating layer 24 (that is, the width between the upper surface and the lower surface of the bottom insulating layer 24 (in other words, , The distance between the lower end of the gate electrode 26 and the bottom surface of the trench 22)).

半導体基板１２の上面１２ａには、上部電極７０が配置されている。上部電極７０は、層間絶縁膜２８が設けられていない部分で半導体基板１２の上面１２ａに接している。上部電極７０は、層間絶縁膜２８によってゲート電極２６から絶縁されている。半導体基板１２の下面１２ｂには、下部電極７２が配置されている。下部電極７２は、半導体基板１２の下面１２ｂに接している。   An upper electrode 70 is disposed on the upper surface 12 a of the semiconductor substrate 12. The upper electrode 70 is in contact with the upper surface 12 a of the semiconductor substrate 12 at a portion where the interlayer insulating film 28 is not provided. The upper electrode 70 is insulated from the gate electrode 26 by the interlayer insulating film 28. A lower electrode 72 is disposed on the lower surface 12 b of the semiconductor substrate 12. The lower electrode 72 is in contact with the lower surface 12 b of the semiconductor substrate 12.

図１〜３に示すように、半導体基板１２の内部には、複数のソース領域３０、ボディ領域３２、ドリフト領域３４、ドレイン領域３５、複数の底部半導体領域３６及び複数の接続半導体領域３８が設けられている。   As shown in FIGS. 1 to 3, a plurality of source regions 30, a body region 32, a drift region 34, a drain region 35, a plurality of bottom semiconductor regions 36, and a plurality of connection semiconductor regions 38 are provided inside the semiconductor substrate 12. It has been.

各ソース領域３０は、ｎ型領域である。図１、２に示すように、各ソース領域３０は、半導体基板１２の上面１２ａに露出しており、上部電極７０にオーミック接触している。また、各ソース領域３０は、トレンチ２２の短手方向の側面（短手方向の端部に位置する側面であり、ｙ方向に沿って伸びる側面）において、ゲート絶縁層２５に接している。各ソース領域３０は、トレンチ２２の上端部において、ゲート絶縁層２５に接している。   Each source region 30 is an n-type region. As shown in FIGS. 1 and 2, each source region 30 is exposed on the upper surface 12 a of the semiconductor substrate 12 and is in ohmic contact with the upper electrode 70. Further, each source region 30 is in contact with the gate insulating layer 25 on the side surface in the short direction of the trench 22 (the side surface located at the end portion in the short direction and extending along the y direction). Each source region 30 is in contact with the gate insulating layer 25 at the upper end of the trench 22.

ボディ領域３２は、ｐ型領域である。ボディ領域３２は、各ソース領域３０に接している。ボディ領域３２は、２つのソース領域３０に挟まれた各範囲から各ソース領域３０の下側まで伸びている。ボディ領域３２は、低濃度領域３２ｂと複数の高濃度領域３２ａを有している。各高濃度領域３２ａは、低濃度領域３２ｂよりも高いｐ型不純物濃度を有している。各高濃度領域３２ａは、２つのソース領域３０に挟まれた各範囲に配置されている。各高濃度領域３２ａは、上部電極７０にオーミック接触している。低濃度領域３２ｂは、各高濃度領域３２ａと各ソース領域３０の下側に配置されている。低濃度領域３２ｂは、トレンチ２２の短手方向の側面において、ゲート絶縁層２５に接している。すなわち、低濃度領域３２ｂは、各ソース領域３０の下側で、ゲート絶縁層２５に接している。また、図１、３に示すように、低濃度領域３２ｂは、トレンチ２２の長手方向の側面（長手方向の端部に位置する側面であり、ｘ方向に沿って伸びる側面）に隣接する範囲にも配置されている。低濃度領域３２ｂは、トレンチ２２の長手方向の側面において、ゲート絶縁層２５に接している。ボディ領域３２の下端（すなわち、低濃度領域３２ｂの下端）は、ゲート電極２６の下端（すなわち、底部絶縁層２４の上面）よりも上側に配置されている。   Body region 32 is a p-type region. The body region 32 is in contact with each source region 30. The body region 32 extends from each range sandwiched between the two source regions 30 to the lower side of each source region 30. The body region 32 has a low concentration region 32b and a plurality of high concentration regions 32a. Each high concentration region 32a has a higher p-type impurity concentration than the low concentration region 32b. Each high concentration region 32 a is disposed in each range sandwiched between two source regions 30. Each high concentration region 32 a is in ohmic contact with the upper electrode 70. The low concentration region 32 b is disposed below each high concentration region 32 a and each source region 30. The low concentration region 32 b is in contact with the gate insulating layer 25 on the side surface in the short direction of the trench 22. That is, the low concentration region 32 b is in contact with the gate insulating layer 25 on the lower side of each source region 30. As shown in FIGS. 1 and 3, the low-concentration region 32 b is in a range adjacent to the side surface in the longitudinal direction of the trench 22 (the side surface located at the end in the longitudinal direction and extending along the x direction). Also arranged. The low concentration region 32 b is in contact with the gate insulating layer 25 on the side surface in the longitudinal direction of the trench 22. The lower end of the body region 32 (that is, the lower end of the low concentration region 32b) is arranged above the lower end of the gate electrode 26 (that is, the upper surface of the bottom insulating layer 24).

ドリフト領域３４は、ｎ型領域である。ドリフト領域３４は、ボディ領域３２の下側に配置されており、ボディ領域３２によって各ソース領域３０から分離されている。ドリフト領域３４は、トレンチ２２の短手方向の側面において、ゲート絶縁層２５及び底部絶縁層２４に接している。すなわち、ドリフト領域３４は、ボディ領域３２の下側で、ゲート絶縁層２５及び底部絶縁層２４に接している。   The drift region 34 is an n-type region. The drift region 34 is disposed below the body region 32 and is separated from each source region 30 by the body region 32. The drift region 34 is in contact with the gate insulating layer 25 and the bottom insulating layer 24 on the lateral side surface of the trench 22. That is, the drift region 34 is in contact with the gate insulating layer 25 and the bottom insulating layer 24 below the body region 32.

ドレイン領域３５は、ｎ型領域である。ドレイン領域３５は、ドリフト領域３４よりも高いｎ型不純物濃度を有している。ドレイン領域３５は、ドリフト領域３４の下側に配置されている。ドレイン領域３５は、半導体基板１２の下面１２ｂに露出している。ドレイン領域３５は、下部電極７２にオーミック接触している。   The drain region 35 is an n-type region. The drain region 35 has a higher n-type impurity concentration than the drift region 34. The drain region 35 is disposed below the drift region 34. The drain region 35 is exposed on the lower surface 12 b of the semiconductor substrate 12. The drain region 35 is in ohmic contact with the lower electrode 72.

各底部半導体領域３６は、ｐ型領域である。各底部半導体領域３６は、対応するトレンチ２２の底面に露出する範囲に配置されている。各底部半導体領域３６は、対応するトレンチ２２の底面において、導体層４０に接している。図３に示すように、各底部半導体領域３６は、対応するトレンチ２２の底面に沿ってｙ方向に長く伸びている。各底部半導体領域３６は、対応するトレンチ２２の一方の端部２２ａから他方の端部２２ｂまで伸びている。図２に示すように、各底部半導体領域３６の周囲は、ドリフト領域３４に囲まれている。後述する接続半導体領域３８が形成されている箇所を除いて、各底部半導体領域３６は、ドリフト領域３４によってボディ領域３２から分離されている。また、各底部半導体領域３６は、ドリフト領域３４によって互いから分離されている。   Each bottom semiconductor region 36 is a p-type region. Each bottom semiconductor region 36 is disposed in a range exposed on the bottom surface of the corresponding trench 22. Each bottom semiconductor region 36 is in contact with the conductor layer 40 at the bottom surface of the corresponding trench 22. As shown in FIG. 3, each bottom semiconductor region 36 extends in the y direction along the bottom surface of the corresponding trench 22. Each bottom semiconductor region 36 extends from one end 22a of the corresponding trench 22 to the other end 22b. As shown in FIG. 2, the periphery of each bottom semiconductor region 36 is surrounded by a drift region 34. Each bottom semiconductor region 36 is separated from the body region 32 by a drift region 34 except for a portion where a connection semiconductor region 38 described later is formed. Each bottom semiconductor region 36 is separated from each other by a drift region 34.

図１、３に示すように、各接続半導体領域３８は、対応するトレンチ２２の長手方向の側面に露出する範囲に配置されている。各接続半導体領域３８は、トレンチ２２の長手方向の側面に沿ってｚ方向に長く伸びている。図３に示すように、各接続半導体領域３８の下端は、対応する底部半導体領域３６に接続されている。各接続半導体領域３８の上端は、ボディ領域３２（低濃度領域３２ｂ）に接続されている。すなわち、各接続半導体領域３８は、ボディ領域３２と底部半導体領域３６に接続されている。なお、本明細書では、トレンチ２２の側面に沿ってボディ領域３２から底部半導体領域３６に向かって長く伸びている部分を、接続半導体領域３８という。つまり、半導体基板１２の上面１２ａに沿って横方向に分布しているｐ型領域がボディ領域３２であり、そのボディ領域３２からトレンチ２２の側面に沿って下方向に突出している部分が、接続半導体領域３８である。図３に示すように、各接続半導体領域３８は、対応するトレンチ２２の長手方向の側面において、ゲート絶縁層２５と底部絶縁層２４に接している。各接続半導体領域３８のｐ型不純物濃度は、各底部半導体領域３６のｐ型不純物濃度よりも低い。   As shown in FIGS. 1 and 3, each connection semiconductor region 38 is arranged in a range exposed on the side surface in the longitudinal direction of the corresponding trench 22. Each connection semiconductor region 38 extends long in the z direction along the longitudinal side surface of the trench 22. As shown in FIG. 3, the lower end of each connection semiconductor region 38 is connected to the corresponding bottom semiconductor region 36. The upper end of each connection semiconductor region 38 is connected to the body region 32 (low concentration region 32b). That is, each connection semiconductor region 38 is connected to the body region 32 and the bottom semiconductor region 36. In the present specification, a portion extending along the side surface of the trench 22 from the body region 32 toward the bottom semiconductor region 36 is referred to as a connection semiconductor region 38. That is, the p-type region distributed in the lateral direction along the upper surface 12 a of the semiconductor substrate 12 is the body region 32, and a portion protruding downward from the body region 32 along the side surface of the trench 22 This is a semiconductor region 38. As shown in FIG. 3, each connection semiconductor region 38 is in contact with the gate insulating layer 25 and the bottom insulating layer 24 on the side surface in the longitudinal direction of the corresponding trench 22. The p-type impurity concentration of each connection semiconductor region 38 is lower than the p-type impurity concentration of each bottom semiconductor region 36.

次に、ＭＯＳＦＥＴ１０の動作について説明する。ＭＯＳＦＥＴ１０の使用時には、ＭＯＳＦＥＴ１０と負荷（例えば、モータ）と電源が直列に接続される。ＭＯＳＦＥＴ１０と負荷の直列回路に対して、電源電圧（本実施形態では、約８００Ｖ）が印加される。ＭＯＳＦＥＴ１０のドレイン側（下部電極７２）がソース側（上部電極７０）よりも高電位となる向きで、電源電圧が印加される。ゲート電極２６にゲートオン電位（ゲート閾値よりも高い電位）を印加すると、ゲート絶縁層２５に接する範囲のボディ領域３２（低濃度領域３２ｂ）にチャネル（反転層）が形成され、ＭＯＳＦＥＴ１０がオンする。ゲート電極２６にゲートオフ電位（ゲート閾値以下の電位）を印加すると、チャネルが消滅し、ＭＯＳＦＥＴ１０がオフする。以下に、ＭＯＳＦＥＴ１０のターンオフ時とターンオン時の動作について、詳細に説明する。なお、導体中にホールは存在しないが、以下では、説明の都合上、半導体と導体の間でホールに相当する電荷が流れる場合に、ホールに相当する電荷が導体中を流れることを、導体中をホールが流れるという場合がある。   Next, the operation of the MOSFET 10 will be described. When the MOSFET 10 is used, the MOSFET 10, a load (for example, a motor), and a power source are connected in series. A power supply voltage (about 800 V in this embodiment) is applied to the series circuit of the MOSFET 10 and the load. The power supply voltage is applied in such a direction that the drain side (lower electrode 72) of the MOSFET 10 has a higher potential than the source side (upper electrode 70). When a gate-on potential (potential higher than the gate threshold) is applied to the gate electrode 26, a channel (inversion layer) is formed in the body region 32 (low-concentration region 32b) in contact with the gate insulating layer 25, and the MOSFET 10 is turned on. When a gate-off potential (potential below the gate threshold) is applied to the gate electrode 26, the channel disappears and the MOSFET 10 is turned off. Hereinafter, the operation of the MOSFET 10 when it is turned off and when it is turned on will be described in detail. Although there are no holes in the conductor, in the following, for the sake of explanation, it is assumed that when a charge corresponding to a hole flows between the semiconductor and the conductor, a charge corresponding to the hole flows in the conductor. There are cases where the hole flows.

ＭＯＳＦＥＴ１０をターンオフさせる場合には、ゲート電極２６の電位をゲートオン電位からゲートオフ電位に引き下げる。すると、チャネルが消失し、下部電極７２の電位が上昇する。下部電極７２の電位は、上部電極７０に対して電源電圧分（すなわち、約８００Ｖ）だけ高い電位まで上昇する。下部電極７２の電位が上昇する過程において、底部半導体領域３６と下部電極７２の間の容量結合によって、底部半導体領域３６の電位が少し上昇する。すると、底部半導体領域３６から導体層４０、接続半導体領域３８及びボディ領域３２を介して上部電極７０へホールが流れる。より詳細には、底部半導体領域３６内のホールは、底部半導体領域３６と導体層４０の内部をトレンチ２２の長手方向に沿って流れる。底部半導体領域３６が導体層４０に接しており、導体層４０の抵抗が底部半導体領域３６の抵抗よりも遥かに低いので、ホールは、主に導体層４０の内部を通ってトレンチ２２の長手方向に沿って流れる。導体層４０の抵抗が極めて低いので、ホールは導体層４０内をトレンチ２２の長手方向に沿って高速で流れる。導体層４０及び底部半導体領域３６に沿ってトレンチ２２の端部２２ａまたは２２ｂまで流れたホールは、接続半導体領域３８及びボディ領域３２を介して上部電極７０へ流れる。このようにホールが流れている間は、底部半導体領域３６の電位の上昇が抑制され、底部半導体領域３６の電位が上部電極７０の電位よりもわずかに高い電位に維持される。導体層４０によってホールがトレンチ２２の長手方向に沿って高速で流れることが可能とされているので、接続半導体領域３８から遠い位置の底部半導体領域３６（すなわち、トレンチ２２の長手方向の中央部２２ｃに位置する部分の底部半導体領域３６（図３参照））からも短時間でホールが排出される。したがって、中央部２２ｃに位置する部分でも電位の上昇が効果的に抑制される。   When the MOSFET 10 is turned off, the potential of the gate electrode 26 is lowered from the gate-on potential to the gate-off potential. Then, the channel disappears and the potential of the lower electrode 72 increases. The potential of the lower electrode 72 rises to a potential that is higher than the upper electrode 70 by a power supply voltage (ie, about 800 V). In the process of increasing the potential of the lower electrode 72, the potential of the bottom semiconductor region 36 slightly increases due to capacitive coupling between the bottom semiconductor region 36 and the lower electrode 72. Then, holes flow from the bottom semiconductor region 36 to the upper electrode 70 through the conductor layer 40, the connection semiconductor region 38, and the body region 32. More specifically, the holes in the bottom semiconductor region 36 flow along the longitudinal direction of the trench 22 through the bottom semiconductor region 36 and the conductor layer 40. Since the bottom semiconductor region 36 is in contact with the conductor layer 40 and the resistance of the conductor layer 40 is much lower than the resistance of the bottom semiconductor region 36, holes mainly pass through the inside of the conductor layer 40 in the longitudinal direction of the trench 22. Flowing along. Since the resistance of the conductor layer 40 is extremely low, the holes flow in the conductor layer 40 along the longitudinal direction of the trench 22 at a high speed. The holes flowing along the conductor layer 40 and the bottom semiconductor region 36 to the end 22a or 22b of the trench 22 flow to the upper electrode 70 via the connection semiconductor region 38 and the body region 32. While the holes are flowing in this way, the rise in the potential of the bottom semiconductor region 36 is suppressed, and the potential of the bottom semiconductor region 36 is maintained at a potential slightly higher than the potential of the upper electrode 70. Since the holes can flow at high speed along the longitudinal direction of the trench 22 by the conductor layer 40, the bottom semiconductor region 36 (that is, the central portion 22 c in the longitudinal direction of the trench 22) far from the connection semiconductor region 38. Holes are also discharged in a short time from the bottom semiconductor region 36 (see FIG. 3) located at the position. Therefore, an increase in potential is effectively suppressed even at the portion located at the central portion 22c.

また、下部電極７２の電位の上昇に伴って、ドレイン領域３５及びドリフト領域３４の電位も上昇する。ドリフト領域３４の電位が上昇すると、ボディ領域３２とドリフト領域３４の間に電位差が生じる。このため、ボディ領域３２とドリフト領域３４の界面のｐｎ接合に逆電圧が印加される。したがって、ボディ領域３２からドリフト領域３４に空乏層が広がる。また、ドリフト領域３４の電位が上昇すると、底部半導体領域３６とドリフト領域３４の間に電位差が生じる。このため、底部半導体領域３６とドリフト領域３４の界面のｐｎ接合に逆電圧が印加される。したがって、底部半導体領域３６からドリフト領域３４に空乏層が広がる。このようにドリフト領域３４内に空乏層が広がることで、ドリフト領域３４内における電界集中が抑制される。特に、底部半導体領域３６から広がる空乏層によって、トレンチ２２の底面近傍における電界集中が抑制される。   As the potential of the lower electrode 72 increases, the potentials of the drain region 35 and the drift region 34 also increase. When the potential of the drift region 34 increases, a potential difference is generated between the body region 32 and the drift region 34. For this reason, a reverse voltage is applied to the pn junction at the interface between the body region 32 and the drift region 34. Therefore, a depletion layer extends from the body region 32 to the drift region 34. Further, when the potential of the drift region 34 increases, a potential difference is generated between the bottom semiconductor region 36 and the drift region 34. For this reason, a reverse voltage is applied to the pn junction at the interface between the bottom semiconductor region 36 and the drift region 34. Therefore, a depletion layer extends from the bottom semiconductor region 36 to the drift region 34. As described above, the depletion layer spreads in the drift region 34, so that electric field concentration in the drift region 34 is suppressed. In particular, the electric field concentration in the vicinity of the bottom surface of the trench 22 is suppressed by the depletion layer extending from the bottom semiconductor region 36.

また、ドリフト領域３４の電位が上昇すると、接続半導体領域３８とドリフト領域３４の界面のｐｎ接合にも逆電圧が印加される。接続半導体領域３８のｐ型不純物濃度が低いので、ｐｎ接合から接続半導体領域３８に広く空乏層が広がる。これによって、接続半導体領域３８が空乏化される。接続半導体領域３８が空乏化されることによって、底部半導体領域３６が上部電極７０から電気的に分離される。   Further, when the potential of the drift region 34 increases, a reverse voltage is also applied to the pn junction at the interface between the connection semiconductor region 38 and the drift region 34. Since the p-type impurity concentration of the connection semiconductor region 38 is low, a depletion layer spreads widely from the pn junction to the connection semiconductor region 38. As a result, the connection semiconductor region 38 is depleted. As the connection semiconductor region 38 is depleted, the bottom semiconductor region 36 is electrically isolated from the upper electrode 70.

底部半導体領域３６がボディ領域３２から電気的に分離されると、底部半導体領域３６から上部電極７０に向かうホールの流れが停止し、底部半導体領域３６の電位がフローティングとなる。このため、底部半導体領域３６の電位が、下部電極７２の電位の上昇に伴って上昇する。このように、底部半導体領域３６の電位がある程度上昇することで、底部半導体領域３６と下部電極７２の間の電位差が過大となることが防止される。下部電極７２の電位が上部電極７０に対して電源電圧分高い電位まで上昇することで、ＭＯＳＦＥＴ１０のターンオフか完了する。   When the bottom semiconductor region 36 is electrically isolated from the body region 32, the flow of holes from the bottom semiconductor region 36 toward the upper electrode 70 stops, and the potential of the bottom semiconductor region 36 becomes floating. For this reason, the potential of the bottom semiconductor region 36 increases as the potential of the lower electrode 72 increases. Thus, the potential difference between the bottom semiconductor region 36 and the lower electrode 72 is prevented from being excessively increased by increasing the potential of the bottom semiconductor region 36 to some extent. When the potential of the lower electrode 72 rises to a potential higher than the upper electrode 70 by the power supply voltage, the turn-off of the MOSFET 10 is completed.

ＭＯＳＦＥＴ１０をターンオンさせる場合には、ゲート電極２６の電位をゲートオフ電位からゲートオン電位に引き上げる。すると、トレンチ２２の短手方向の側面においてゲート絶縁層２５に接している範囲のボディ領域３２（低濃度領域３２ｂ）に電子が引き寄せられる。これによって、この範囲のボディ領域３２がｐ型からｎ型に反転し、チャネルが形成される。チャネルによって、ソース領域３０とドリフト領域３４が接続される。これによって、ドリフト領域３４、ドレイン領域３５及び下部電極７２の電位が低下する。ドリフト領域３４の電位が低下すると、ボディ領域３２とドリフト領域３４の界面のｐｎ接合に印加されていた逆電圧が低下する。このため、ボディ領域３２からドリフト領域３４に広がっていた空乏層が、ボディ領域３２に向かって収縮する。これにより、上部電極７０から、ソース領域３０、チャネル、ドリフト領域３４、ドレイン領域３５を経由して下部電極７２へ電子が流れるようになる。すなわち、ＭＯＳＦＥＴ１０がオンする。   When the MOSFET 10 is turned on, the potential of the gate electrode 26 is raised from the gate-off potential to the gate-on potential. Then, electrons are attracted to the body region 32 (low concentration region 32 b) in a range in contact with the gate insulating layer 25 on the side surface in the short direction of the trench 22. As a result, the body region 32 in this range is inverted from p-type to n-type, and a channel is formed. The source region 30 and the drift region 34 are connected by the channel. As a result, the potentials of the drift region 34, the drain region 35, and the lower electrode 72 are lowered. When the potential of the drift region 34 decreases, the reverse voltage applied to the pn junction at the interface between the body region 32 and the drift region 34 decreases. For this reason, the depletion layer extending from the body region 32 to the drift region 34 contracts toward the body region 32. As a result, electrons flow from the upper electrode 70 to the lower electrode 72 via the source region 30, the channel, the drift region 34, and the drain region 35. That is, the MOSFET 10 is turned on.

また、ドリフト領域３４の電位が低下する過程において、接続半導体領域３８に広がっている空乏層が、ドリフト領域３４に向かって収縮して略消滅する。その結果、底部半導体領域３６が、ボディ領域３２に電気的に接続される。すると、上部電極７０からボディ領域３２、接続半導体領域３８及び導体層４０を介して底部半導体領域３６にホールが流れる。より詳細には、上部電極７０から、ボディ領域３２と接続半導体領域３８を介して導体層４０と底部半導体領域３６へホールが流れる。導体層４０の抵抗が底部半導体領域３６の抵抗よりも遥かに低いので、ホールは、主に導体層４０の内部を通ってトレンチ２２の長手方向に沿って流れる。導体層４０を介して、底部半導体領域３６の全体にホールが供給される。底部半導体領域３６にホールが供給されると、底部半導体領域３６からドリフト領域３４に広がっていた空乏層が底部半導体領域３６に向かって収縮する。このため、ドリフト領域３４の抵抗が低下し、上部電極７０から下部電極７２に向かって電子が流れ易くなる。このため、ドリフト領域３４で損失が生じ難い。特に、本実施形態では、導体層４０の抵抗が極めて低いので、ホールは導体層４０内をトレンチ２２の長手方向に沿って高速で流れることが可能とされている。このため、接続半導体領域３８から遠い位置の底部半導体領域３６（すなわち、中央部２２ｃに位置する部分の底部半導体領域３６）にも短時間でホールが供給される。したがって、底部半導体領域３６の全体に短時間でホールが供給される。このため、底部半導体領域３６全体の周囲で、ドリフト領域３４に広がっていた空乏層を高速で収縮させることができる。したがって、このＭＯＳＦＥＴ１０では、ゲート電極２６の電位をゲートオン電位に引き上げてから短時間でドリフト領域３４の抵抗が低下する。すなわち、このＭＯＳＦＥＴ１０は、ターンオンするときに短時間でオン抵抗が低下する。したがって、このＭＯＳＦＥＴ１０では、損失が生じ難い。   In addition, in the process in which the potential of the drift region 34 is lowered, the depletion layer spreading in the connection semiconductor region 38 contracts toward the drift region 34 and is almost extinguished. As a result, the bottom semiconductor region 36 is electrically connected to the body region 32. Then, holes flow from the upper electrode 70 to the bottom semiconductor region 36 through the body region 32, the connection semiconductor region 38, and the conductor layer 40. More specifically, holes flow from the upper electrode 70 to the conductor layer 40 and the bottom semiconductor region 36 through the body region 32 and the connection semiconductor region 38. Since the resistance of the conductor layer 40 is much lower than the resistance of the bottom semiconductor region 36, the holes flow mainly along the inside of the conductor layer 40 along the longitudinal direction of the trench 22. Holes are supplied to the entire bottom semiconductor region 36 via the conductor layer 40. When holes are supplied to the bottom semiconductor region 36, the depletion layer that has spread from the bottom semiconductor region 36 to the drift region 34 contracts toward the bottom semiconductor region 36. For this reason, the resistance of the drift region 34 decreases, and electrons easily flow from the upper electrode 70 toward the lower electrode 72. For this reason, it is difficult for loss to occur in the drift region 34. In particular, in this embodiment, since the resistance of the conductor layer 40 is extremely low, holes can flow in the conductor layer 40 along the longitudinal direction of the trench 22 at a high speed. For this reason, holes are also supplied to the bottom semiconductor region 36 far from the connection semiconductor region 38 (that is, the bottom semiconductor region 36 located at the central portion 22c) in a short time. Therefore, holes are supplied to the entire bottom semiconductor region 36 in a short time. Therefore, the depletion layer that has spread to the drift region 34 can be contracted at high speed around the entire bottom semiconductor region 36. Therefore, in this MOSFET 10, the resistance of the drift region 34 decreases in a short time after the potential of the gate electrode 26 is raised to the gate-on potential. That is, when the MOSFET 10 is turned on, the on-resistance decreases in a short time. Therefore, in this MOSFET 10, it is difficult for loss to occur.

以上に説明したように、ＭＯＳＦＥＴ１０では、ターンオン時に、導体層４０を介して底部半導体領域３６全体に短時間でホールが供給される。このため、底部半導体領域３６全体の周囲において、底部半導体領域３６からドリフト領域３４に広がっている空乏層を短時間で収縮させることができる。したがって、ＭＯＳＦＥＴ１０では、ターンオン時に損失が生じ難い。   As described above, in the MOSFET 10, holes are supplied to the entire bottom semiconductor region 36 through the conductor layer 40 in a short time when the MOSFET 10 is turned on. Therefore, the depletion layer extending from the bottom semiconductor region 36 to the drift region 34 can be contracted in a short time around the entire bottom semiconductor region 36. Therefore, in the MOSFET 10, it is difficult for loss to occur at the time of turn-on.

次に、ＭＯＳＦＥＴ１０の製造方法について説明する。まず、図４に示すように、ドレイン領域３５、ドリフト領域３４、ボディ領域３２及びソース領域３０を備える半導体基板１２ｘ（ＭＯＳＦＥＴ１０の材料となる半導体基板）を準備する。半導体基板１２ｘは、ＳｉＣによって構成されている。ドリフト領域３４は、ドレイン領域３５上にエピタキシャル成長によって形成された領域である。ボディ領域３２とソース領域３０は、エピタキシャル成長またはイオン注入によって形成された領域である。   Next, a method for manufacturing MOSFET 10 will be described. First, as shown in FIG. 4, a semiconductor substrate 12 x (a semiconductor substrate serving as a material for the MOSFET 10) including the drain region 35, the drift region 34, the body region 32, and the source region 30 is prepared. The semiconductor substrate 12x is made of SiC. The drift region 34 is a region formed on the drain region 35 by epitaxial growth. The body region 32 and the source region 30 are regions formed by epitaxial growth or ion implantation.

次に、図５に示すように、半導体基板１２ｘの上面１２ａを部分的にエッチングすることによって、複数のトレンチ２２を形成する。トレンチ２２は、ソース領域３０とボディ領域３２を貫通してドリフト領域３４に達するように形成される。   Next, as shown in FIG. 5, the plurality of trenches 22 are formed by partially etching the upper surface 12a of the semiconductor substrate 12x. The trench 22 is formed so as to penetrate the source region 30 and the body region 32 and reach the drift region 34.

次に、図６に示すように、半導体基板１２ｘの上面１２ａとトレンチ２２の内面（すなわち、底面と側面）に、薄い酸化膜５０を形成する。酸化膜５０は、酸化シリコンにより構成されており、絶縁性を有する。半導体基板１２ｘの表面を酸化させることで、酸化膜５０を形成することができる。   Next, as illustrated in FIG. 6, a thin oxide film 50 is formed on the upper surface 12 a of the semiconductor substrate 12 x and the inner surface (that is, the bottom surface and the side surface) of the trench 22. The oxide film 50 is made of silicon oxide and has an insulating property. The oxide film 50 can be formed by oxidizing the surface of the semiconductor substrate 12x.

次に、図７に示すように、異方性のドライエッチングによって、半導体基板１２ｘの上面１２ａ上とトレンチ２２の底面上の酸化膜５０を除去する。トレンチ２２の側面には、酸化膜５０を残存させる。   Next, as shown in FIG. 7, the oxide film 50 on the upper surface 12a of the semiconductor substrate 12x and the bottom surface of the trench 22 is removed by anisotropic dry etching. The oxide film 50 is left on the side surface of the trench 22.

次に、図８に示すように、トレンチ２２の底面にアルミニウムイオンを注入することによって、底部半導体領域３６を形成する。また、トレンチ２２の長手方向の側面にアルミニウムイオンを注入することによって、接続半導体領域３８を形成する。   Next, as shown in FIG. 8, the bottom semiconductor region 36 is formed by implanting aluminum ions into the bottom surface of the trench 22. In addition, the connection semiconductor region 38 is formed by implanting aluminum ions into the longitudinal side surface of the trench 22.

次に、図９に示すように、半導体基板１２ｘの上面１２ａとトレンチ２２の内面（すなわち、トレンチ２２の底面と酸化膜５０の表面）に、金属層５２（例えば、ニッケル層）を成膜する。   Next, as shown in FIG. 9, a metal layer 52 (for example, a nickel layer) is formed on the upper surface 12a of the semiconductor substrate 12x and the inner surface of the trench 22 (that is, the bottom surface of the trench 22 and the surface of the oxide film 50). .

次に、半導体基板１２ｘを約７００℃で熱処理する。トレンチ２２の底面では、金属層５２と半導体基板１２ｘとが直接接触しているので、金属層５２（すなわち、ニッケル）と半導体基板１２ｘ中のシリコンが合金化（シリサイド化）する。これによって、図１０に示すように、トレンチ２２の底部に、導体層４０が形成される。また、半導体基板１２ｘの上面１２ａでも、金属層５２の合金化により導体層４０が形成される。トレンチ２２の側面では、金属層５２が半導体基板１２ｘの間に酸化膜５０が存在しているので、合金化反応は生じない。導体層４０を形成したら、図１１に示すように、エッチング（例えば、リン硝酢酸ウェットエッチング）によって、合金化しなかった金属層５２を除去する。このとき、導体層４０はほとんどエッチングされないので、導体層４０を残存させることができる。さらに、エッチング（例えば、フッ酸エッチング）によって、酸化膜５０を除去する。その後、半導体基板１２ｘを約１０００℃で熱処理して、合金化（シリサイド化）の反応を促進する。これによって、導体層４０の抵抗が低減されるとともに、導体層４０の底部半導体領域３６に対するコンタクト抵抗が低減される。   Next, the semiconductor substrate 12x is heat-treated at about 700 ° C. Since the metal layer 52 and the semiconductor substrate 12x are in direct contact with each other at the bottom surface of the trench 22, the metal layer 52 (that is, nickel) and silicon in the semiconductor substrate 12x are alloyed (silicided). As a result, a conductor layer 40 is formed at the bottom of the trench 22 as shown in FIG. Further, the conductor layer 40 is also formed on the upper surface 12a of the semiconductor substrate 12x by alloying the metal layer 52. On the side surface of the trench 22, since the oxide film 50 exists between the metal layer 52 and the semiconductor substrate 12 x, no alloying reaction occurs. After the conductor layer 40 is formed, as shown in FIG. 11, the metal layer 52 that has not been alloyed is removed by etching (for example, phosphorous nitrate acetic acid wet etching). At this time, since the conductor layer 40 is hardly etched, the conductor layer 40 can remain. Further, the oxide film 50 is removed by etching (for example, hydrofluoric acid etching). Thereafter, the semiconductor substrate 12x is heat-treated at about 1000 ° C. to promote an alloying (silicide) reaction. Thereby, the resistance of the conductor layer 40 is reduced, and the contact resistance of the conductor layer 40 to the bottom semiconductor region 36 is reduced.

次に、ＬＰ−ＣＶＤ等によってトレンチ２２内に酸化シリコンを埋め込み、その後に酸化シリコンをエッチングする。これによって、図１２に示すように、底部絶縁層２４が形成される。その後、従来周知の方法により、ゲート絶縁層２５、ゲート電極２６、層間絶縁膜２８、上部電極７０及び下部電極７２等を形成することで、図１〜３に示すＭＯＳＦＥＴ１０が完成する。なお、半導体基板１２ｘの上面１２ａ上の導体層４０は、上部電極７０の形成前に除去してもよいし、上部電極７０の一部として利用してもよい。   Next, silicon oxide is buried in the trench 22 by LP-CVD or the like, and then the silicon oxide is etched. As a result, the bottom insulating layer 24 is formed as shown in FIG. Thereafter, the gate insulating layer 25, the gate electrode 26, the interlayer insulating film 28, the upper electrode 70, the lower electrode 72, and the like are formed by a conventionally known method, thereby completing the MOSFET 10 shown in FIGS. Note that the conductor layer 40 on the upper surface 12a of the semiconductor substrate 12x may be removed before the formation of the upper electrode 70, or may be used as a part of the upper electrode 70.

なお、上述した実施形態では、接続半導体領域３８がトレンチ２２の長手方向の側面に設けられていた。しかしながら、接続半導体領域３８は、トレンチ２２の側面の任意の部分に設けることができる。例えば、図１３に示すように、トレンチ２２の短手方向の側面の一部に接続半導体領域３８を設けてもよい。この場合、接続半導体領域３８を有する部分のトレンチ２２の断面は、図１４の構造となる。このような構成でも、導体層４０によってトレンチ２２の長手方向におけるホールの流れが促進されるので、上述した実施形態と同様の効果が得られる。但し、接続半導体領域３８を形成した位置ではＭＯＳＦＥＴの主電流が流れないので、接続半導体領域３８の数はなるべく少ないことが好ましい。他方、底部半導体領域３６全体により短時間でホールを供給するには、接続半導体領域３８をより分散して配置することが好ましい。接続半導体領域３８の数とその配置を最適化するために、上述した実施形態（図１）のように、接続半導体領域３８をトレンチ２２の長手方向の両端部に配置し、両端部近傍まで伸びるように導体層４０を設ける構造がより好ましい。   In the above-described embodiment, the connection semiconductor region 38 is provided on the side surface in the longitudinal direction of the trench 22. However, the connection semiconductor region 38 can be provided in any part of the side surface of the trench 22. For example, as shown in FIG. 13, a connection semiconductor region 38 may be provided on a part of the lateral surface of the trench 22 in the short direction. In this case, the cross section of the trench 22 in the portion having the connection semiconductor region 38 has the structure shown in FIG. Even in such a configuration, since the hole flow in the longitudinal direction of the trench 22 is promoted by the conductor layer 40, the same effect as the above-described embodiment can be obtained. However, since the main current of the MOSFET does not flow at the position where the connection semiconductor region 38 is formed, the number of connection semiconductor regions 38 is preferably as small as possible. On the other hand, in order to supply holes to the entire bottom semiconductor region 36 in a short time, it is preferable to dispose the connection semiconductor regions 38 in a more dispersed manner. In order to optimize the number and arrangement of the connection semiconductor regions 38, the connection semiconductor regions 38 are arranged at both ends in the longitudinal direction of the trench 22 and extend to the vicinity of both ends as in the above-described embodiment (FIG. 1). Thus, a structure in which the conductor layer 40 is provided is more preferable.

なお、上述した実施形態では、導体層４０の材料としてニッケルシリサイドを用いたが、チタンシリサイド、チタンカーバイド、アルミニウムシリサイド、アルミニウムカーバイド等を用いてもよい。また、ＳｉＣと反応性が有る鉄（Ｆｅ）や銅（Ｃｕ）を主成分とした化合物を導体層４０の材料として用いてもよい。また、導体層４０によるチャネル部の金属汚染を防止するために、底部絶縁層２４の厚みはなるべく厚いことが好ましい。底部絶縁層２４の厚みは、１００ｎｍ以上であることが好ましく、５００ｎｍ以上であることがより好ましい。また、底部絶縁層２４は、酸化シリコン以外の絶縁体（例えば、酸化アルミニウム（Ａｌ２Ｏ３））により構成されていてもよい。 In the embodiment described above, nickel silicide is used as the material of the conductor layer 40, but titanium silicide, titanium carbide, aluminum silicide, aluminum carbide, or the like may be used. A compound mainly composed of iron (Fe) or copper (Cu) that has reactivity with SiC may be used as the material of the conductor layer 40. In addition, in order to prevent metal contamination of the channel portion by the conductor layer 40, the bottom insulating layer 24 is preferably as thick as possible. The thickness of the bottom insulating layer 24 is preferably 100 nm or more, and more preferably 500 nm or more. The bottom insulating layer 24 may be made of an insulator other than silicon oxide (for example, aluminum oxide (Al 2 O 3 )).

また、上述した実施形態では、ｎチャネル型のＭＯＳＦＥＴについて説明したが、ｐチャネル型のＭＯＳＦＥＴに本明細書に開示の技術を適用してもよい。上述した実施形態のｎ型領域とｐ型領域を入れ換えることで、ｐチャネル型のＭＯＳＦＥＴを構成することができる。   In the above-described embodiments, the n-channel MOSFET has been described. However, the technology disclosed in this specification may be applied to a p-channel MOSFET. By replacing the n-type region and the p-type region in the above-described embodiment, a p-channel MOSFET can be configured.

また、上述した実施形態では、トレンチ２２の長手方向において、導体層４０がトレンチ２２の底面の略全域に設けられていた。しかしながら、トレンチ２２の長手方向において、導体層４０がトレンチ２２の底面の一部にのみ設けられていてもよい。このような構成でも、トレンチ２２の底面において、導体層４０によってホールがトレンチ２２の長手方向に移動し易くなり、底部半導体領域３６全体に短時間でホールを供給することができる。   In the above-described embodiment, the conductor layer 40 is provided over substantially the entire bottom surface of the trench 22 in the longitudinal direction of the trench 22. However, the conductor layer 40 may be provided only on a part of the bottom surface of the trench 22 in the longitudinal direction of the trench 22. Even in such a configuration, the holes are easily moved in the longitudinal direction of the trench 22 by the conductor layer 40 on the bottom surface of the trench 22, and the hole can be supplied to the entire bottom semiconductor region 36 in a short time.

上述した実施形態の各構成要素と請求項の各構成要素との関係について説明する。実施形態のソース領域３０は、請求項の第１半導体領域の一例である。実施形態のドリフト領域３４は、請求項の第２半導体領域の一例である。実施形態の酸化膜５０は、請求項の保護膜の一例である。   The relationship between each component of the embodiment described above and each component of the claims will be described. The source region 30 in the embodiment is an example of a first semiconductor region in the claims. The drift region 34 in the embodiment is an example of a second semiconductor region in the claims. The oxide film 50 according to the embodiment is an example of a protective film in claims.

本明細書が開示する技術要素について、以下に列記する。なお、以下の各技術要素は、それぞれ独立して有用なものである。   The technical elements disclosed in this specification are listed below. The following technical elements are each independently useful.

本明細書が開示する一例の構成では、接続半導体領域が、トレンチの長手方向の一方の端部の側面に沿って伸びる第１部分と、他方の端部の側面に沿って伸びる第２部分を有している。   In the configuration of an example disclosed in the present specification, the connection semiconductor region includes a first portion extending along the side surface of one end portion in the longitudinal direction of the trench and a second portion extending along the side surface of the other end portion. Have.

この構成によれば、トレンチの両端部から底部半導体領域に電荷が供給されるので、底部半導体領域の周囲のドリフト領域の抵抗がより速く低下する。   According to this configuration, since electric charges are supplied from both ends of the trench to the bottom semiconductor region, the resistance of the drift region around the bottom semiconductor region is more quickly reduced.

以上、実施形態について詳細に説明したが、これらは例示にすぎず、特許請求の範囲を限定するものではない。特許請求の範囲に記載の技術には、以上に例示した具体例をさまざまに変形、変更したものが含まれる。本明細書または図面に説明した技術要素は、単独あるいは各種の組み合わせによって技術有用性を発揮するものであり、出願時請求項記載の組み合わせに限定されるものではない。また、本明細書または図面に例示した技術は複数目的を同時に達成するものであり、そのうちの１つの目的を達成すること自体で技術有用性を持つものである。   The embodiments have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above. The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or the drawings achieves a plurality of objects at the same time, and has technical usefulness by achieving one of them.

１０：ＭＯＳＦＥＴ
１２：半導体基板
２２：トレンチ
２４：底部絶縁層
２５：ゲート絶縁層
２６：ゲート電極
２８：層間絶縁膜
３０：ソース領域
３２：ボディ領域
３４：ドリフト領域
３５：ドレイン領域
３６：底部半導体領域
３８：接続半導体領域
４０：導体層
７０：上部電極
７２：下部電極 10: MOSFET
12: Semiconductor substrate 22: Trench 24: Bottom insulating layer 25: Gate insulating layer 26: Gate electrode 28: Interlayer insulating film 30: Source region 32: Body region 34: Drift region 35: Drain region 36: Bottom semiconductor region 38: Connection Semiconductor region 40: Conductor layer 70: Upper electrode 72: Lower electrode

Claims (3)

半導体基板と、
前記半導体基板の上面に設けられたトレンチと、
前記トレンチの底面に接するように前記トレンチの長手方向に沿って伸びる導体層と、
前記導体層の上面を覆う底部絶縁層と、
前記底部絶縁層よりも上側の前記トレンチの側面を覆うゲート絶縁層と、
前記トレンチの内部に配置されており、前記底部絶縁層及び前記ゲート絶縁層によって前記半導体基板及び前記導体層から絶縁されているゲート電極、
を有し、
前記半導体基板が、
前記ゲート絶縁層に接する第１導電型の第１半導体領域と、
前記第１半導体領域の下側で前記ゲート絶縁層に接する第２導電型のボディ領域と、
前記ボディ領域の下側で前記ゲート絶縁層に接しており、前記ボディ領域によって前記第１半導体領域から分離されている第１導電型の第２半導体領域と、
前記導体層に接するように前記トレンチの長手方向に沿って伸び、前記第２半導体領域に接する第２導電型の底部半導体領域と、
前記トレンチの側面の一部に沿って伸び、前記ボディ領域と前記底部半導体領域に接続されている第２導電型の接続半導体領域、
を有するスイッチング装置。 A semiconductor substrate;
A trench provided on an upper surface of the semiconductor substrate;
A conductor layer extending along the longitudinal direction of the trench so as to contact the bottom surface of the trench;
A bottom insulating layer covering the top surface of the conductor layer;
A gate insulating layer covering a side surface of the trench above the bottom insulating layer;
A gate electrode disposed within the trench and insulated from the semiconductor substrate and the conductor layer by the bottom insulating layer and the gate insulating layer;
Have
The semiconductor substrate is
A first semiconductor region of a first conductivity type in contact with the gate insulating layer;
A body region of a second conductivity type in contact with the gate insulating layer under the first semiconductor region;
A second semiconductor region of a first conductivity type that is in contact with the gate insulating layer under the body region and is separated from the first semiconductor region by the body region;
A bottom semiconductor region of a second conductivity type extending along a longitudinal direction of the trench so as to be in contact with the conductor layer and in contact with the second semiconductor region;
A connection semiconductor region of a second conductivity type extending along a part of the side surface of the trench and connected to the body region and the bottom semiconductor region;
A switching device. 前記接続半導体領域が、前記トレンチの長手方向の一方の端部の側面に沿って伸びる第１部分と、他方の端部の側面に沿って伸びる第２部分を有している、
請求項１のスイッチング装置。 The connection semiconductor region has a first portion extending along a side surface of one end portion in the longitudinal direction of the trench, and a second portion extending along a side surface of the other end portion.
The switching device according to claim 1. 半導体基板の上面にトレンチを形成する工程と、
前記トレンチの底面が露出するように前記トレンチの側面を覆う保護膜を成膜する工程と、
前記保護膜と前記トレンチの底面を覆う金属層を形成する工程と、
前記金属層を加熱することによって前記金属層と前記トレンチの底面が合金化した導体層を形成する工程と、
前記導体層が残存するように前記保護膜を覆う前記金属層をエッチングにより除去する工程と、
前記導体層と前記トレンチを用いて、スイッチング装置を完成させる工程、
を有しており、
前記スイッチング装置が、
前記導体層の上面を覆う底部絶縁層と、
前記底部絶縁層よりも上側の前記トレンチの側面を覆うゲート絶縁層と、
前記トレンチの内部に配置されており、前記底部絶縁層及び前記ゲート絶縁層によって前記半導体基板及び前記導体層から絶縁されているゲート電極と、
前記ゲート絶縁層に接する第１導電型の第１半導体領域と、
前記第１半導体領域の下側で前記ゲート絶縁層に接する第２導電型のボディ領域と、
前記ボディ領域の下側で前記ゲート絶縁層に接し、前記ボディ領域によって前記第１半導体領域から分離されている第１導電型の第２半導体領域と、
前記導体層に接するように前記トレンチの長手方向に沿って伸び、前記第２半導体領域に接する第２導電型の底部半導体領域と、
前記トレンチの側面の一部に沿って伸び、前記ボディ領域と前記底部半導体領域に接続されている第２導電型の接続半導体領域、
を有する、
製造方法。 Forming a trench on the upper surface of the semiconductor substrate;
Forming a protective film covering a side surface of the trench so that a bottom surface of the trench is exposed;
Forming a metal layer covering the protective film and the bottom of the trench;
Forming a conductor layer in which the bottom surface of the metal layer and the trench are alloyed by heating the metal layer;
Removing the metal layer covering the protective film by etching so that the conductor layer remains; and
A step of completing a switching device using the conductor layer and the trench;
Have
The switching device is
A bottom insulating layer covering the top surface of the conductor layer;
A gate insulating layer covering a side surface of the trench above the bottom insulating layer;
A gate electrode disposed within the trench and insulated from the semiconductor substrate and the conductor layer by the bottom insulating layer and the gate insulating layer;
A first semiconductor region of a first conductivity type in contact with the gate insulating layer;
A body region of a second conductivity type in contact with the gate insulating layer under the first semiconductor region;
A second semiconductor region of a first conductivity type in contact with the gate insulating layer under the body region and separated from the first semiconductor region by the body region;
A bottom semiconductor region of a second conductivity type extending along a longitudinal direction of the trench so as to be in contact with the conductor layer and in contact with the second semiconductor region;
A connection semiconductor region of a second conductivity type extending along a part of the side surface of the trench and connected to the body region and the bottom semiconductor region;
Having
Production method.
JP2016190035A 2016-09-28 2016-09-28 Switching device and manufacturing method Pending JP2018056304A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2016190035A JP2018056304A (en) 2016-09-28 2016-09-28 Switching device and manufacturing method
US15/664,379 US9954096B2 (en) 2016-09-28 2017-07-31 Switching device and method of manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2016190035A JP2018056304A (en) 2016-09-28 2016-09-28 Switching device and manufacturing method

Publications (1)

Publication Number Publication Date
JP2018056304A true JP2018056304A (en) 2018-04-05

Family

ID=61685716

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2016190035A Pending JP2018056304A (en) 2016-09-28 2016-09-28 Switching device and manufacturing method

Country Status (2)

Country Link
US (1) US9954096B2 (en)
JP (1) JP2018056304A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2020047726A (en) * 2018-09-18 2020-03-26 トヨタ自動車株式会社 Semiconductor device
JP2021125605A (en) * 2020-02-06 2021-08-30 株式会社デンソー Switching element

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6560141B2 (en) * 2016-02-26 2019-08-14 トヨタ自動車株式会社 Switching element
JP6560142B2 (en) * 2016-02-26 2019-08-14 トヨタ自動車株式会社 Switching element
JP6669628B2 (en) * 2016-10-20 2020-03-18 トヨタ自動車株式会社 Switching element
CN114122129A (en) * 2020-08-27 2022-03-01 旭矽半导体(上海)有限公司 Groove type MOSFET device and preparation method thereof
CN114122130A (en) * 2020-08-27 2022-03-01 旭矽半导体(上海)有限公司 Trench type MOSFET device

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4414863B2 (en) * 2004-10-29 2010-02-10 トヨタ自動車株式会社 Insulated gate semiconductor device and manufacturing method thereof
JP5751213B2 (en) 2012-06-14 2015-07-22 株式会社デンソー Silicon carbide semiconductor device and manufacturing method thereof
DE112013006638T5 (en) * 2013-02-25 2015-10-29 Hitachi, Ltd. Semiconductor device, semiconductor device driving device, and power conversion device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2020047726A (en) * 2018-09-18 2020-03-26 トヨタ自動車株式会社 Semiconductor device
JP2021125605A (en) * 2020-02-06 2021-08-30 株式会社デンソー Switching element
JP7359012B2 (en) 2020-02-06 2023-10-11 株式会社デンソー switching element

Also Published As

Publication number Publication date
US20180090612A1 (en) 2018-03-29
US9954096B2 (en) 2018-04-24

Similar Documents

Publication Publication Date Title
US9214526B2 (en) Semiconductor device
JP2018056304A (en) Switching device and manufacturing method
JP6784921B2 (en) Switching element and its manufacturing method
KR101439310B1 (en) Semiconductor device
JP6606007B2 (en) Switching element
JPWO2014188569A1 (en) IGBT with built-in diode
JP6453188B2 (en) Silicon carbide semiconductor device
JP6563639B2 (en) Semiconductor device and manufacturing method of semiconductor device
JP2015185700A (en) semiconductor device
JP2019087611A (en) Switching element and manufacturing method thereof
JP6571467B2 (en) Insulated gate type switching element and manufacturing method thereof
JP2017191817A (en) Method for manufacturing switching element
CN107833921B (en) Switching device and method of manufacturing switching device
JP6639365B2 (en) Semiconductor device
JP6299658B2 (en) Insulated gate type switching element
JP7326991B2 (en) switching element
JP7147510B2 (en) switching element
JP2018206914A (en) Semiconductor device
US20150364585A1 (en) Power semiconductor device
JP6450659B2 (en) Semiconductor device
JP6337969B2 (en) Semiconductor device and manufacturing method thereof
JP7352151B2 (en) switching element
JP7560344B2 (en) Semiconductor Device
JP2020047726A (en) Semiconductor device
JP2018046254A (en) Switching element