JP2017216527A - A/d converter and jitter correction method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an A/D converter capable of performing jitter correction by a simpler configuration.SOLUTION: An A/D converter 10 includes a clock signal generation unit 20 for generating multiple clock signals of the same frequency and different phase, an A/D converter 32 for sampling analog signals inputted repeatedly based on a clock signal generated in the clock signal generation unit 20, a storage unit 43 for storing unit period data consisting of digital data sampled in the A/D converter 32, and an operation unit 42 for averaging multiple unit period data.SELECTED DRAWING: Figure 1

Description

  The present invention relates to an A / D converter and a jitter correction method.

  In an analog-to-digital conversion (A / D conversion) device that samples an analog signal to obtain a digital output signal, in order to digitize the analog signal with high accuracy, a sampling period is set to a period of the analog signal to be sampled It is necessary to set it short.

  However, there is a limit to increasing the frequency of the reference clock for determining the sampling timing in order to shorten the sampling period. For this reason, it is known that sampling with a frequency higher than that of the reference clock signal is realized by generating a clock signal delayed by a certain phase from the reference clock and making it a multiphase clock signal (Patent Document 1).

JP 2002-71724 A

  When the sampling timing of A / D conversion is determined using the above-described multiphase clock signal, the noise of each circuit such as an oscillation circuit, a phase interpolation circuit, and a multiplexer that generates the multiphase clock, manufacturing variation, etc. Variations occur in the rise timing interval and the fall timing interval.

  As a result, the sampling interval varies, so that the digitized output signal includes a jitter component, and the accuracy (signal-to-noise ratio) of the output signal decreases.

  The present invention has been made in view of the above-described circumstances, and an object thereof is to provide an A / D conversion device and a jitter correction method that can improve the accuracy of an output signal with a simple configuration.

In order to achieve the above object, an A / D conversion device according to the first aspect of the present invention provides:
A clock signal generator for generating a plurality of clock signals having the same frequency and different phases;
An A / D converter that samples an analog signal repeatedly input based on the clock signal generated by the clock signal generation unit;
A storage unit for storing unit cycle data composed of digital data sampled by the A / D converter;
An arithmetic unit that averages a plurality of the unit period data;
Is provided.

The A / D converter is
You may provide the control part which selects the clock signal which starts sampling among the several clock signals produced | generated by the said clock signal production | generation part for every said unit period data.

  The analog signal may be a periodic analog signal.

The clock signal generator is
You may transmit the clock signal which prescribes | regulates the transmission timing of the said analog signal to the transmission part which transmits the said analog signal.

In addition, the calculation unit
The received waveform included in each unit period data to be averaged may be synchronized.

The clock signal generator is
A phase interpolation circuit that generates a clock signal having an arbitrary intermediate phase based on two clock signals having different phases may be provided.

Further, the phase interpolation circuit includes:
A plurality of inverters having different driving forces may be provided.

The jitter correction method according to the second aspect of the present invention is:
Based on the reference clock signal, generate multiple clock signals with the same frequency and different phases,
Sampling an input signal that is a periodic analog signal based on the clock signal, and generating a plurality of unit period data obtained by starting sampling from the different clock signals,
A plurality of the unit period data is averaged to generate an output signal.

  According to the present invention, since a plurality of unit period data can be averaged and jitter correction can be performed, the accuracy of the output signal can be increased with a simple configuration.

It is a block diagram which shows the structure of the A / D converter which concerns on embodiment. It is a block diagram which shows the structure of a phase locked loop. (A) is a block diagram which shows the structure of the phase interpolation circuit which concerns on embodiment, (B) is a block diagram which shows the structure of the conventional phase interpolation circuit. (A) is a block diagram illustrating a configuration example of an inverter having the same driving force, and (B) is a block diagram illustrating a configuration example of an inverter having a different driving force. It is a figure which shows the input-output waveform of a phase interpolation circuit. It is a block diagram which shows the structure of a multiplexer. It is a block diagram which shows the hardware constitutions of a data processing part. It is a conceptual diagram which shows the example of equivalent time sampling. It is a conceptual diagram which shows the averaging process of unit period data.

  Embodiments according to the present invention will be described below with reference to the drawings.

  As shown in the block diagram of FIG. 1, the A / D conversion apparatus 10 according to the present embodiment includes an oscillation circuit 30, a clock signal generation unit 20, a reception unit 31, an A / D converter 32, and a data processing unit 40. Prepare.

  The oscillation circuit 30 is a circuit that generates a reference clock signal RCLK and outputs the reference clock signal RCLK to the clock signal generation unit 20, and is, for example, a crystal oscillation circuit including a crystal oscillator, a capacitor, and the like.

  Based on the input reference clock signal RCLK, the clock signal generation unit 20 defines the sampling clock signal SCLK that defines the sampling timing of the A / D converter 32 and the transmission timing of the radiation pulse of the transmission unit 50 described later. A transmission clock signal TCLK is generated. The clock signal generation unit 20 sends the generated sampling clock signal SCLK to the A / D converter 32 and sends the generated transmission clock signal TCLK to the transmission unit 50.

  More specifically, the clock signal generation unit 20 includes a phase synchronization circuit 201, a phase interpolation circuit 202, a multiplexer 203, and a frequency divider 204, as shown in FIG.

  The phase synchronization circuit 201 is connected to the oscillation circuit 30 and receives the reference clock signal RCLK from the oscillation circuit 30. The phase synchronization circuit 201 is a phase synchronization circuit having a general configuration shown in FIG. 2 and outputs a clock signal synchronized with the reference clock signal RCLK.

  The phase synchronization circuit 201 according to the present embodiment outputs a plurality of clock signals having different phases. Based on the plurality of clock signals, a phase interpolation circuit 202 to be described later further generates an intermediate phase clock signal. Thereby, sampling at high frequency can be performed. Details will be described later.

  The phase interpolation circuit 202 is a circuit that generates an intermediate phase clock signal based on the clock signals having different phases received from the phase synchronization circuit 201. Specifically, as shown in FIG. 3A, the phase interpolation circuit 202 includes inverters 202a to 202h having different driving forces. The phase interpolation circuit 202 outputs a clock signal having an intermediate phase between the input clock signal Φi1 and the input clock signal Φi2 by the driving force of the inverters 202a to 202h.

  The driving forces A to H of the inverters 202a to 202h are set to have a ratio of A: B: C: D = H: G: F: E = 4: 3: 2: 1. As shown in FIGS. 4A and 4B, the inverters 202a to 202h according to the present embodiment are CMOS inverters. The driving force of each inverter is adjusted by changing the number of transistors constituting the inverter. Specifically, as shown in FIG. 4A, the inverters 202c and 202f that generate the output clock signal Φo3 both have two n-type transistors and two p-type transistors connected in parallel. On the other hand, as shown in FIG. 4B, the inverter 202b for generating the output clock signal Φo2 is configured by connecting three n-type transistors and three p-type transistors in parallel, and the inverter 202e It is composed of one n-type transistor and one p-type transistor.

  The output clock signal Φo3 is generated with the same configuration as the conventional phase interpolation circuit. That is, when the input clock signal Φi1 falls, the output clock signal Φo1 rises due to the output of the inverter 202a, and the output clock signal Φo3 rises due to the output of the inverter 202c (FIG. 5). At this time, since the ratio of the driving force of the inverter 202a and the driving force of the inverter 202c is set to 4: 2 (= 2: 1), the output clock signal Φo3 is more gradual than the output clock signal Φo1. stand up.

  Further, when the input clock signal Φi2 falls, the output of the inverter 202f and the output of the inverter 202c are combined, and the output clock signal Φo3 rises with a slope approximately equal to the output clock signal Φo1. When the input clock signal Φi2 falls, the output clock signal Φo5 rises by the output of the inverter 202h. Since the ratio between the driving force of the inverter 202a and the driving force of the inverter 202h is set to 4: 4 (= 1: 1), the output clock signal Φo5 rises with a slope approximately equal to the output clock signals Φo1 and Φo3. . Thus, the phase interpolation circuit 202 generates an output clock signal Φo3 having an intermediate phase between the input clock signal Φi1 and the output clock signal Φo1 based on the inverter 202a and the output clock signal Φo5 based on the input clock signal Φi2 and the inverter 202h. be able to.

  The phase interpolation circuit 202 of the present embodiment further includes inverters 202b and 202e having different driving forces in order to generate an output clock signal Φo2 having an intermediate phase between the output clock signal Φo1 and the output clock signal Φo3. As described above, the driving force ratio of the inverters 202a, 202b, 202c, and 202e is set to 4: 3: 2: 1.

  As a result, when the input clock signal Φi1 falls, the output clock signal Φo2 rises with an inclination smaller than the output clock signal Φo1 and larger than the output clock signal Φo3 by the output of the inverter 202b. Further, when the input clock signal Φi2 falls, the output of the inverter 202e and the output of the inverter 202b are combined, and the output clock signal Φo2 rises with a slope approximately equal to the output clock signals Φo1 and Φo3. Thereby, the phase interpolation circuit 202 can generate an output clock signal Φo2 having an intermediate phase between the output clock signal Φo1 and the output clock signal Φo3 from the input clock signals Φi1 and Φi2.

  Further, the phase interpolation circuit 202 is configured to generate an output clock signal Φo4 having an intermediate phase between the output clock signal Φo3 and the output clock signal Φo5. The circuit configuration for generating the output clock signal Φo4 has a ratio of the driving power of the inverter on the input clock signal Φi1 side to the driving power of the inverter on the input clock signal Φi2 side as compared with the circuit configuration for generating the output clock signal Φo2. It has been replaced. Other configurations are the same as in the case of the output clock signal Φo2, and thus description thereof is omitted.

  As described above, by using inverters having different driving powers, three clock signals having a phase between the input clock signal Φi1 and the input clock signal Φi2 can be generated. Therefore, as shown in FIG. 3B, there is no need to add a phase interpolation circuit for generating an output clock signal Φo2 having an intermediate phase from the output clock signal Φo1 and the output clock signal Φo3. A phase clock signal can be generated. As a result, it is possible to reduce random jitter and delay variation compared to the case where a two-stage phase interpolation circuit is provided.

  As shown in FIGS. 1 and 6, the multiplexer 203 receives a plurality of clock signals generated by the phase interpolation circuit 202 as input signals. The multiplexer 203 sends one clock signal of the input clock signals as the sampling clock signal SCLK to the frequency divider 204 according to the selection control signal from the control unit 41. Further, the multiplexer 203 sends one clock signal of the input clock signals to the frequency divider 204 as the reference transmission clock TCLK0 according to the selection control signal from the control unit 41. The reference transmission clock TCLK0 is a clock signal that serves as a reference for the transmission clock signal TCLK. The transmission clock signal TCLK is a clock signal that defines the signal transmission timing of the transmission unit 50 described later.

  The frequency divider 204 sends the sampling clock signal SCLK received from the multiplexer 203 to the A / D converter 32. The frequency divider 204 divides the reference transmission clock TCLK0 received from the multiplexer 203. The frequency divider 204 transmits the divided clock signal to the transmission unit 50 as a transmission clock signal TCLK.

  The transmission unit 50 is a wireless transmission unit that transmits an analog signal sampled by the A / D conversion device 10, and includes a transmission antenna 501 and a transmission signal processing unit 502. The transmission signal processing unit 502 generates a transmission signal according to the transmission clock signal TCLK received from the clock signal generation unit 20 and sends it to the transmission antenna 501. The transmission antenna 501 transmits a transmission signal.

  The reception unit 31 is a wireless reception unit that receives a signal transmitted from the transmission unit 50, and includes a reception antenna 311 and a reception signal processing unit 312. The reception antenna 311 sends the received signal to the reception signal processing unit 312. The reception signal processing unit 312 sends the received signal to the A / D converter 32 as a sampling target signal.

  The A / D converter 32 samples the analog signal received from the reception unit 31 according to the sampling clock signal SCLK received from the clock signal generation unit 20 and sends the sampled signal to the calculation unit 42 of the data processing unit 40.

  As shown in the block diagram of FIG. 1, the data processing unit 40 includes a control unit 41, a calculation unit 42, and a storage unit 43.

  The control unit 41 controls the entire A / D conversion device 10.

  The calculation unit 42 generates unit cycle data UD described later from the digital data sampled by the A / D converter 32. Further, an averaging process for correcting jitter of the unit cycle data UD is performed.

  The storage unit 43 stores unit cycle data UD generated by the data processing unit 40.

  The data processing unit 40 shown in FIG. 1 has a hardware configuration shown in FIG. 7, for example. Specifically, the data processing unit 40 includes a CPU (Central Processing Unit) 61 that controls the entire apparatus, a main storage unit 62 that operates as a work area of the CPU 61, and an external storage that stores an operation program of the CPU 61 and the like. Unit 63, an A / D converter 32, an input / output interface 67 that communicates with the clock signal generation unit 20, and the like, and a bus 68 that connects them.

  The main storage unit 62 is composed of a RAM (Random Access Memory) or the like. The main storage unit 62 is loaded with an operation program and data that are stored in the external storage unit 63 and cause the CPU 61 to operate as the control unit 41. The main storage unit 62 is also used as a work area (temporary data storage area) for the CPU 61.

  The external storage unit 63 includes a nonvolatile memory such as a flash memory. The external storage unit 63 stores an operation program to be executed by the CPU 61 in advance. Specifically, the operation program includes a unit cycle data generation program 631 for generating unit cycle data UD, which will be described later, and a jitter correction program 632 for correcting the influence of jitter included in the unit cycle data UD. The main storage unit 62 and the external storage unit 63 function as the storage unit 43.

  Next, the operation of the A / D converter 10 having the above configuration will be described.

  Based on the 1.6 GHz reference clock signal RCLK output from the oscillation circuit 30, the clock signal generation unit 20 generates multiphase clock signals having the same frequency and different phases. Further, a sampling clock signal SCLK is generated based on this multiphase clock signal and sent to the A / D converter 32. The phase difference between the clock signals in the multiphase clock signal, that is, the number of generated multiphase clock signals is determined according to the frequency of the analog signal to be sampled.

  As shown in FIG. 8, in the present embodiment, the transmission unit 50 repeatedly transmits a radiation pulse having a predetermined frequency as a transmission signal. The center frequency of the radiation pulse is, for example, 5 GHz and has a pulse width of 200 ps. The transmission unit 50 transmits this radiation pulse at a repetition period of 100 MHz.

  In general, it is difficult to perform sampling a plurality of times within a pulse width of 200 ps and perform A / D conversion on an input signal in real time. Therefore, in this embodiment, as conceptually shown in FIG. 8, sampling is performed once for one pulse wave, the pulse wave is repeatedly output, and the sampling timing is relatively moved. This enables sampling of a plurality of points equivalently for one pulse wave (equivalent time sampling).

  Specifically, the phase synchronization circuit 201 generates a 1.6 GHz clock signal CLi_n (n is an integer of 1 to 16) having different phases based on the input reference clock signal RCLK. The clock signal CLi_1 is synchronized with the reference clock signal, and the clock signal CLi_2 is a signal delayed by 1/16 of 40 ps, that is, 640 ps that is one cycle of the reference clock (1.6 GHz) from the CLi_1. Thereafter, CLi_1 to CLi_16 are generated as clock signals delayed by 40 ps. The phase synchronization circuit 201 sends the clock signal CLi_n to the phase interpolation circuit 202.

  As described above, the phase interpolation circuit 202 has a basic circuit configuration of a circuit that generates three intermediate phase clock signals from two input clock signals having different phases. The phase interpolation circuit 202 according to the present embodiment includes 16 basic circuit configurations. Each basic circuit configuration generates intermediate phase clock signals CLo_ (4n−2), CLo_ (4n−1), and CLo_4n from the clock signal CLi_n and CLi_ (n + 1) delayed by 40 ps from CLi_n.

  As a result, the phase interpolation circuit 202 generates a clock signal CLo_m (m is an integer of 1 to 64) delayed by 10 ps and sends it to the multiplexer 203. When n = 16, intermediate phase clock signals CLo_62, CLo_63, and CLo_64 are generated from the clock signals CLi_16 and CLi_1.

  The control unit 41 sends a selection control signal for selecting the reference transmission clock TCLK0 to the multiplexer 203. The reference transmission clock TCLK0 is a clock signal that serves as a reference for the transmission clock signal TCLK. The multiplexer 203 selects one clock signal from the clock signals CLo_1 to CLo_64 having a frequency of 1.6 GHz according to the selection control signal, and divides the clock signal by 1/16. And the clock signal which became 100 MHz by frequency division is transmitted to the transmission part 50 as the transmission clock signal TCLK.

  The transmitter 50 transmits a radiation pulse at the rising timing of the transmission clock signal TCLK. Thereby, the transmission signal transmitted from the transmission part 50 becomes a signal repeated with a period (100 MHz) of 10 ns.

  Further, the control unit 41 sends a selection control signal for selecting one of the clock signals CLo_1 to CLo_64 to the multiplexer 203 as the sampling clock signal SCLK that defines the sampling timing of the A / D converter 32. The multiplexer 203 sends the clock signal selected as the sampling clock signal SCLK to the A / D converter 32 via the frequency divider 204.

  The control unit 41 sequentially selects the clock signal CLo_m delayed by 10 ps as the sampling clock signal SCLK, such as the clock signals CLo_1, CLo_2,..., CLo_64. More specifically, the control unit 43 first selects the clock signal CLo_1 as the sampling clock signal SCLK, and changes the sampling clock signal SCLK to the clock signal CLo_2 10 ns after the clock signal CLo_1 rises. Thereafter, by changing the sampling clock signal SCLK every 10 ns, the sampling clock signal SCLK is shifted by 10 ps for each cycle of the transmission clock signal TCLK. In other words, the cycle of the sampling clock signal SCLK is shifted by 10 ps with respect to the transmission cycle of the radiation pulse.

  The A / D converter 32 samples the received analog signal received from the receiving unit 31 in accordance with the sampling clock signal SCLK described above, and sends it to the computing unit 42.

  The calculation unit 42 divides the received sampling data into 64 data groups for each clock signal CLo_m selected as the sampling clock signal SCLK, that is, every 10 ns. Then, the output data of FIG. 8 is generated by superimposing these 64 data groups shifted by 10 ps. As a result, it is possible to equivalently sample a radiation pulse signal having a high cycle with a slower sampling cycle.

  The calculation unit 42 causes the storage unit 43 to store the output data obtained by the superposition as one unit period data UD. In other words, the calculation unit 42 causes the storage unit 43 to store 10 ns of the received analog signal (one cycle of 100 MHz) as unit cycle data UD that is equivalently sampled at a cycle of 10 ps (100 GHz).

  In other words, the unit cycle data UD is digital data of a unit length including a radiation pulse as a transmission waveform and subjected to jitter correction by averaging. In the above, the length of the unit cycle data UD is set to one cycle of the transmission clock signal TCLK, thereby facilitating the averaging process described later.

  By the way, the phase difference between the clock signals CLo_m is not necessarily equal due to variations in circuits in the multiplexer. Therefore, the unit cycle data UD digitized as described above includes jitter.

  The A / D conversion apparatus 10 according to the present embodiment acquires the unit cycle data UD while changing the clock signal for starting the sampling, and stores it in the storage unit 43. Then, the jitter component is corrected by averaging the plurality of stored unit period data UD.

  More specifically, first, the multiplexer 203 selects the clock signal CLo_1 as the reference transmission clock TCLK0 according to the selection control signal of the control unit 41, and sends it to the frequency divider 204. The frequency divider 204 divides the received reference transmission clock TCLK 0, generates a transmission clock signal TCLK as a synchronous clock signal, and sends it to the transmission unit 50.

  In addition, as described above, the A / D converter 32 performs sampling for 10 ns 64 times by the sampling clock signal SCLK started from the clock signal CLo_1 to acquire digital data. The calculation unit 42 generates unit cycle data UD_1 from the acquired digital data and stores it in the storage unit 43.

  After the sampling for 10 ns is completed, the control unit 41 sends a reset signal to the multiplexer 203. Upon receiving the reset signal, the multiplexer 203 changes the reference transmission clock TCLK0 for generating the transmission clock signal TCLK from the clock signal CLo_1 to CLo_2. Also, the clock signal for starting 64 samplings is changed to CLo_2.

  As a result, the unit cycle data UD_2 composed of 10 ns worth of digital data sampled next by the A / D converter 32 is the clock used for sampling with respect to the unit cycle data UD_1, as conceptually shown in FIG. The signal is shifted by 10 ps.

  The A / D converter 10 repeats the reset of the transmission clock signal a predetermined number of times, for example, 10 times, and generates 10 unit cycle data UD.

  Thereafter, the calculation unit 42 reads the 10 unit cycle data UD stored in the storage unit 43 and obtains an average value for each data element constituting each unit cycle data UD.

  Specifically, each unit period data to be averaged is defined as UD_k (k = 1 to 10), and the jth data element constituting the unit period data UD_k is defined as ak_j (j = 1 to 1000). Then, the data element a_j of the output data to be obtained is obtained by the following equation.

  Output data is generated based on each data element obtained by the above equation.

  In the A / D conversion device 10 according to the present embodiment, since the transmission clock signal TCLK and the change timing of the sampling clock signal SCLK are synchronized, the position where the radiation pulse appears in each unit period data UD is constant. is there. For this reason, it is possible to correct the jitter component while leaving the waveform of the radiation pulse by simply averaging each data element using the above equation.

  As described above, the A / D conversion apparatus 10 according to the present embodiment can easily correct the jitter component included in the unit cycle data UD by averaging the plurality of unit cycle data UD. . More specifically, the phase difference between the clock signals CLo_m used for sampling, that is, the error in the sampling data caused by the deviation between the rising timings can be corrected by the averaging process.

  Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments, and various modifications and applications are possible.

  In the A / D converter 10 described above, the number of resets of the transmission clock signal and the number of acquisitions of the unit cycle data UD are set to 10 times, but the present invention is not limited to this. These numbers may be any number that provides a sufficient correction effect with respect to the expected magnitude of jitter. In order to obtain a more accurate output waveform, reset is performed a number of times equal to the number of clock signals CLo_m, that is, 64 times, and all clock signals CLo_m are selected as start clocks.

  Further, the start clock signal CLo_m of the sampling clock signal SCLK may not select the clock signal CLo_m having a continuous phase. For example, the phase difference between the clock signals CLo_m to be selected may be sequentially changed or may be selected at random.

  Further, the start clock signal CLo_m of the sampling clock signal SCLK may not be changed. For example, the unit cycle data UD with the start clock signal as CLo_1 may be acquired 10 times, and the acquired unit cycle data UD may be averaged. This method is effective as a jitter correction method when it is desired to reduce the influence of random jitter generated during A / D conversion rather than the influence of jitter based on phase variation between CLo_m.

  In the A / D converter 10 described above, when resetting the transmission clock signal TCLK, the start clock signal CLo_m of the sampling clock signal SCLK is changed to adjust the transmission clock signal TCLK and the sampling clock signal SCLK. However, the start clock signal CLo_m of the sampling clock signal SCLK may not be changed, and only the transmission clock signal TCLK may be arbitrarily switched.

  In this case, it is unclear at which position in the unit cycle data UD the radiation pulse included as the received waveform in the unit cycle data UD appears. For this reason, as preprocessing of the averaging processing by the data processing unit 41, symbols such as rising edges and vertex portions of radiation pulses in the stored unit cycle data UD are detected. For example, among the three consecutive data elements in the unit cycle data UD, the part where the central data element is the largest is detected as the apex part which is the symbol position.

  Then, after the unit period data UD is synchronized based on the detected symbol position, the averaging process is performed. As a result, adjustment of the clock signal SCLK becomes unnecessary, and jitter can be easily corrected only by the arithmetic processing by the data processing unit 40.

  Further, the inverters 202a to 202h of the phase interpolation circuit 202 described above include different numbers of transistors. Thereby, although it comprised so that the driving force of each inverter might differ, it is not restricted to this. For example, the drive power of each inverter may be different by changing the gate width, gate length, and the like of a transistor included in each inverter.

  Further, a general-purpose computer device may be used as the data processing unit 40. Thereby, an A / D conversion device can be configured with a simpler circuit configuration.

  The present invention is not limited to the above-described embodiments, and the scope of the present invention is indicated by the claims. Embodiments obtained by various modifications made within the scope of the claims and within the scope of the equivalent invention are also included in the technical scope of the present invention.

  The present invention is suitable as an A / D conversion device used for detecting abnormal tissue in vivo such as cancer. The present invention is not limited to an abnormal tissue detection device, and can be applied to an A / D conversion device that digitally converts a high-frequency analog signal that is repeatedly input.

DESCRIPTION OF SYMBOLS 10 A / D converter 20 Clock signal generation part 30 Oscillation circuit 31 Reception part 32 A / D converter 40 Data processing part 41 Control part 42 Operation part 43 Storage part 50 Transmission part 61 CPU
62 Main storage unit 63 External storage unit 67 Input / output interface 68 Bus 201 Phase synchronization circuit 202 Phase interpolation circuits 202a to 202h Inverter 203 Multiplexer 204 Frequency divider 311 Reception antenna 312 Reception signal processing unit 501 Transmission antenna 502 Transmission signal processing unit 631 Unit Period data generation program 632 Jitter correction program

Claims (8)

A clock signal generator for generating a plurality of clock signals having the same frequency and different phases;
An A / D converter that samples an analog signal repeatedly input based on the clock signal generated by the clock signal generation unit;
A storage unit for storing unit cycle data composed of digital data sampled by the A / D converter;
An arithmetic unit that averages a plurality of the unit period data;
An A / D conversion device. A control unit that selects a clock signal for starting sampling among the plurality of clock signals generated by the clock signal generation unit for each unit period data,
The A / D conversion device according to claim 1. The analog signal is a periodic analog signal.
The A / D conversion device according to claim 1. The clock signal generator is
Transmitting a clock signal defining the transmission timing of the analog signal to a transmission unit that transmits the analog signal;
The A / D conversion device according to any one of claims 1 to 3. The computing unit is
Synchronize the received waveform included in each unit period data to be averaged,
The A / D conversion device according to any one of claims 1 to 4. The clock signal generator is
A phase interpolation circuit that generates a clock signal having an arbitrary intermediate phase based on two clock signals having different phases;
The A / D conversion device according to any one of claims 1 to 5. The phase interpolation circuit includes:
With a plurality of inverters with different driving forces,
The A / D conversion device according to any one of claims 1 to 6. Based on the reference clock signal, generate multiple clock signals with the same frequency and different phases,
Sampling an input signal that is a periodic analog signal based on the clock signal, and generating a plurality of unit period data obtained by starting sampling from the different clock signals,
A plurality of the unit period data is averaged to generate an output signal.
Jitter correction method.

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