JP2000221248A - Semiconductor testing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a semiconductor testing device provided with such a digitizer that can make A/D-converted measurement at an equivalently high sampling frequency, by changing the phase of sampling making A/D conversion at every fixed period by using one A/D converter by a specific phase shifting amount by means of a phase shifting means. SOLUTION: A synchronization control section 40 supplies a sampling clock 40clk and a fixed period signal 40s to a phase shifting means 20 at a fixed period time repetitively generated by a device to be tested. A controller 15 supplies the information corresponding to a phase shifting amount ΔP to the shifting means 20. Upon receiving the clock 40clk, the means 20 supplies a sampling clock 20clk by adding the desired phase shifting amount P to the clock 40clk at every fixed period T. When the fixed period T is set in such a way that M times of periods T become one-round measuring period, the phase shifting amount ΔP becomes 360 deg./M. When, for example, M=8, the clock 20clk which is phase-shifted 45 deg. by 45 deg. is supplied to an A/D converter 30.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor test apparatus including a digitizer that continuously converts an analog signal output from a device under test into an analog signal for measurement. In particular, the present invention relates to an apparatus capable of equivalently increasing a sampling frequency for AD conversion.

[0002]

2. Description of the Related Art As for the prior art, FIG.
An example of a conceptual configuration of a signal test system, an example of a conceptual configuration of a digitizer according to the present invention in FIG. 5, and two ADs in FIG.
7 shows a configuration example of a main part of a digitizer using C and two A's shown in FIG.
This will be described below with reference to a timing chart example for explaining the operation by DC. First, a mixed signal test system will be described. The mixed signal test system enables testing of a digital / analog mixed type IC. As shown in FIG. 4, the resources of the digital tester unit (FTU), the resources of the analog tester unit, And a synchronization control unit for synchronizing the two. On the FTU side, a timing generator TG, which is a component of a general semiconductor test apparatus, and an ALP
A pattern generator including G and SQPG and an FC for shaping the waveform at a predetermined timing are provided. The tester channels include, for example, 256 channels, and are connected via pin electronics (PE) to digital input / output pins of IC pins of the DUT in the test station.

[0003] The synchronization control unit 40 includes an event master,
It has a digital / analog synchronous control unit and others. In response to the generated signal on the SQPG side, a synchronization start signal or trigger signal is generated to synchronize the timing of the generated pattern on the FTU side with the timing of signal generation on the analog tester side or the timing of measurement. To a predetermined analog unit.

A clock source 48 includes a clock source,
A clock master is provided, receives a clock signal such as a rate clock from the TG on the FTU side, a clock from the SSG, receives a clock signal from a clock generator provided therein, and receives a desired signal for each analog unit. A clock or a clock obtained by dividing the frequency is supplied.

As an example of resources on the analog tester side, as shown in FIG. 4, a DAW for generating digital waveform data, an acquisition memory AQM (Acquisition Memory) which is a storage device for capturing a digital output code, an arbitrary frequency signal A synthesizer (SSG) that generates an analog signal, an arbitrary waveform generator (AWG), a digitizer (DGT) that converts an analog waveform into a digital data sequence, a time measuring device (TMU) that measures a frequency and a period, and a DC voltage , A high-precision voltage measuring device (PVM) that measures a DC voltage, a DSP and a CPU that perform data arithmetic processing, and the like. Many of these various resources are provided in a plurality of systems, and can receive a desired synchronization signal from the synchronization control unit 40 to generate a signal or start measurement. Each analog unit and the DUT IC pin are connected to a pin electronics (P) for transmitting and receiving signals.
E).

Next, the prior art will be described with reference to a conceptual configuration example of a digitizer (DGT) shown in FIG. The main configuration of the digitizer according to the present application includes a filter (FLT) 60 and an AD
And a converter (ADC) 30. Here, the signal under measurement output from the DUT is various, and has a high-speed waveform or a highly accurate waveform. These various DUTs
, A plurality of types of digitizers are provided, and are appropriately switched according to the DUT for use. For example, an ADC in a high-speed digitizer has 12 bits 100
It has a sampling rate of MHz and a ADC of a high-precision digitizer has a sampling rate of 26 bits and 100 KHz.

The FLT 60 is, for example, an anti-aliasing filter. A plurality of low-pass filters having desired pass band characteristics are provided for each frequency band.
One of these is selected for use. Normally, a DUT is used to function as an anti-aliasing filter.
Receives the analog input signal from the
A filter for removing a frequency component equal to or higher than the sampling frequency fc is used.
0 input.

The ADC 30 is an A / D converter, has a sampling clock input terminal, and has a sampling clock 4
The input signal at the edge of every 0 clk is sampled. That is, the analog signal from the FLT 60 is continuously converted into code data 30 s at the sampling frequency fc, which is the sampling clock 40 clk, and supplied to the AQM 50.

An acquisition memory (AQM) 50 is a storage memory, which receives the code data 30s and receives the code data 30s.
When the storage timing signal 47s is received from 0, code data 30s continuous from a predetermined address is sequentially stored.

[0010] By the way, the finer the sampling resolution, the more accurate the evaluation and analysis of the DUT. Therefore, in order to sample the analog signal output from the DUT at sufficiently small intervals, the digitizer measures at a sampling frequency fc as high as possible.

Next, a sampling frequency exceeding the highest sampling frequency fc available in the ADC, for example, 2
A configuration example in which measurement can be performed at twice the sampling frequency will be described with reference to FIGS. 6 and 7. Here, two A
Sampling using DC and equivalently sampling at twice the sampling rate is called an equivalent sampling rate, and the frequency is defined as an equivalent sampling frequency fce.

As shown in FIG. 6, the main parts of the digitizer are an FLT 60, a first ADC 31, and a second ADC 32.
And a multiplexer 35. The setting condition of the FLT 60 is set to an anti-aliasing filter condition corresponding to the equivalent sampling frequency fce.

The first ADC 31 performs A / D conversion with the sampling clock 41 clk from the synchronization control unit 40 and outputs the result as shown in the timing chart of FIG. 7A. The sampling clock 41clk is the highest sampling rate of the ADC. The second ADC 32 receives the sampling clock 42cl from the synchronization control unit 40 as shown in the timing of FIG.
A / D-converted by k and output. Sampling clock 42c
lk is the maximum sampling rate of the ADC and is a clock whose phase is shifted by 180 degrees from the sampling clock 41clk.

The multiplexer 35 receives the code data from the first ADC 31 and the code data from the second ADC 32 like the clock 45 s of a square wave shown in FIG. The serial data alternately selected is sequentially output to the AQM 50 according to the high level / low level of the clock 45s.

The synchronization control unit 40 sends the first A
A corresponding control signal is supplied to the DC 31, the second ADC 32, the multiplexer 35, and the AQM 50.

As a result, an input analog signal can be captured at an equivalent sampling frequency fce twice as fast as the maximum sampling rate of the ADC. Similarly, by connecting M = 5 systems and 10 systems of ADCs in parallel and sampling, an input analog signal can be captured at an equivalent sampling frequency fce of 5 × or 10 ×.
Here, it is assumed that the ADC is capable of sampling the input analog signal at the edge point of the sampling clock 41clk with practical accuracy. As a result, M is higher than in the case of a single ADC.
As a result of being able to sample practically up to twice the frequency,
The advantage that the upper limit of the frequency of the DUT evaluation analysis is improved by a factor of M can be obtained. However, in this circuit configuration, there is a great difficulty that the circuit scale of the digitizer increases twice, five times, and ten times.

[0017]

As described above, in the prior art, when sampling at a sampling frequency exceeding the maximum sampling rate of the ADC provided in the digitizer, the circuit scale of the digitizer is equivalent as shown in FIG. There is a great difficulty that increases in proportion to the sampling frequency fce, which is undesirable in a semiconductor test apparatus and a practical difficulty. By the way, in a semiconductor test apparatus, a clock signal and other signals can be supplied to a DUT under arbitrary conditions. For this reason, the analog signal output from the DUT can often be repeatedly generated at a fixed cycle. Accordingly, the problem to be solved by the present invention is to focus on the point that a signal to be measured output from a DUT can be repeatedly generated and controlled at a constant cycle by a semiconductor test apparatus, and one AD converter is used for each fixed cycle. By changing the sampling phase for AD conversion and performing AD conversion,
An object of the present invention is to provide a semiconductor test apparatus including a digitizer capable of performing AD conversion measurement at an equivalently high sampling frequency.

[0018]

First, in order to solve the above-mentioned problems, in the configuration of the present invention, an analog signal under test output from a device under test is converted into a DUT using resources of a semiconductor test apparatus. An A / D converter (A) that is an output signal that can be repeatedly generated at a known constant period T by performing predetermined control, and that samples a signal under measurement at a predetermined time interval Ts using a sampling clock and converts it into code data.
DC), the phase of the sampling clock at a predetermined time interval Ts is changed by a predetermined phase shift amount ΔP = 360 / M in a semiconductor test apparatus provided with a waveform digitizer that continuously stores the sampling clock in an acquisition memory (AQM). (Where M is the number of cycles) Sampling clock 20cl changed
By measuring the period of the number of cycles M with the phase shift means 20 for generating k, the signal under test is equivalently converted to Ts /
A semiconductor test apparatus characterized by realizing a waveform digitizer that samples at equal intervals of M. According to the invention described above, focusing on the point that the signal to be measured output from the DUT can be repeatedly generated and controlled at a fixed cycle by the semiconductor test apparatus, the sampling phase for performing the A / D conversion at a fixed cycle using one AD converter is used. By changing the A / D conversion, a semiconductor test apparatus having a digitizer capable of performing an A / D conversion measurement at an equivalently high sampling frequency can be realized.

Continuous code data 3 obtained by AD conversion
As an address generating means for storing 0s in a storage device (for example, AQM50), it is assumed that the measurement is completed at a constant period T every M times, and the generation position of the constant period T is Q (where Q is 0 to M− 1) and an address generating means for generating an address value of Q + (M × N) and supplying the address value to the storage device when the generation position of the sampling clock 20 clk at every constant period T is N. There is the above-mentioned semiconductor test apparatus.

The address generating means has a period counter which generates a period counting signal 72s which is initially reset to "0" and is incremented by one each time the fixed period signal 40s is received thereafter. , Cycle number M
Receiving the value at one input, receiving the address signal 79s from register 79 at the other input, and adding the two;
A first adding means, and a gate means for making the output zero only when the fixed period signal 40s is received, and passing the accumulated data from the first adding means at any other time. A second input means for receiving the signal 72s at one input terminal, receiving the accumulated data 76s from the gate means, and adding the two, and receiving the data from the second adder means;
comprising a register 79 that latches with clk,
An address signal 79s from the register output may be supplied to an address input terminal of the storage device to constitute a semiconductor test device.

As another configuration of the address generating means, when the value of the number of cycles M is an exponent of 2, the count value is incremented by one every time the fixed cycle signal 40s is received, and the address value to the lower bits is changed. Generating a first counting means,
A second counting means is provided which counts +1 each time the constant sampling clock 20clk is received and generates the remaining upper address bits 79H, receives data from the first counting means, latches the data by the sampling clock 20clk, and sets an address. A flip-flop for generating a lower address bit 79L of the signal; a lower address bit 79L from the flip-flop;
The remaining upper address bits 79H from the counting means are
The semiconductor test apparatus may be configured by supplying the data to the address input terminal of the storage device.

As a result, the advantage is obtained that the waveform data of the fixed period T is arranged and stored in the AQM 50 in the order of data sampled in units of the predetermined phase shift amount ΔP.

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in detail with reference to the drawings together with embodiments.

Regarding the present invention, a main part configuration of the digitizer of FIG. 1 and a timing chart for explaining the operation of FIG.
This will be described below with reference to the principle configuration of the phase shift means of FIG. Elements corresponding to the conventional configuration are denoted by the same reference numerals.

First, the configuration of the present invention will be described. Where D
The signal to be measured output from the UT is repeatedly generated at a constant period T, and a device that can be measured in a synchronous relationship between the timing of the semiconductor test apparatus and the constant period T, or the constant period T is known. Of the cycle time. For example, in the case of the control of the synchronous relation, there is a case where the synchronous control of the waveform generation of the DUT is performed by the test pattern supplied by the FTU. Further, even in the case of an asynchronous relationship, the present invention can be applied as long as the fixed cycle time is known. In addition, even if the relationship is asynchronous, if the constant cycle time can be measured each time using the resources of the semiconductor test apparatus, the frequency of the sampling clock can be easily set based on the measured cycle time, so that the present invention is applicable. .

As shown in FIG. 1, the main components of the present application are an FLT 60, an ADC 30, and a phase shifter 20.
, A controller 15 and a synchronization control unit 40. In this configuration, the FLT 60 and the ADC 30 are the same elements as the conventional one.

The synchronization control unit 40 controls the sampling clock 40cl for a certain period of time in which the DUT repeatedly occurs.
k and the constant period signal 40 s are supplied to the phase shift means 20. The controller 15 supplies information corresponding to the phase shift amount ΔP to the phase shift means 20. For example, in FIG. 3, the set value “M” is supplied. The description of FIG. 3 will be described later.

The phase shift means 20 receives the sampling clock 40clk from the synchronization control unit 40, and generates and supplies a sampling clock 20clk obtained by adding a desired phase shift amount ΔP at regular intervals T. here,
When a period in which the constant period T is M times is set as a cycle measurement period, the phase shift amount ΔP of the sampling clock is 360 degrees / M
Is the phase amount of For example, when M = 8, 360 degrees / 8 =
The unit is 45 degrees, which is initially 0 degrees in the constant period T, and 45 degrees, 90 degrees, 135 degrees, and 18 degrees in the subsequent constant period T.
A sampling clock 20clk whose phase is shifted by 0 degrees, 315 degrees is supplied to the ADC.

As a result, the measurement can be performed at an equivalent sampling rate M times the maximum sampling rate which is the upper limit of the performance of the ADC. However, it is necessary that the fixed period T is maintained at least for one round period as the measurement period. The apparent sampling rate, that is, the equivalent sampling rate can be reduced by reducing the phase shift amount ΔP, but the voltage measurement accuracy at the time of sampling is affected by the characteristics of the sample & hold time for sampling inside the ADC 30. I do. Therefore, it is desired to use an ADC having a good sample & hold time characteristic.

FIG. 3 shows an example of a block configuration for generating a sampling clock 20clk for adding a predetermined phase shift amount ΔP. The configuration is an M multiplier 22 and a 1 / M frequency divider 2
4 The M multiplier 22 receives a sampling clock 40 clk from the synchronization control unit 40 and generates a clock multiplied by M. The 1 / M frequency divider 24 receives the M-multiplied clock and divides it by 1 / M to obtain a sampling clock 20 clk.
Is generated and output. However, each time the fixed period signal 40s is received from the synchronization control unit 40, the frequency division operation is suspended once. As a result, a sampling clock 20 clk to which a 1 / M phase shift amount ΔP is added at every constant period T is obtained. By the way, from the synchronization control unit 40, the sampling clock 4 of M times
If 0 clk is supplied, the M multiplier 22 can be eliminated. The phase shifter having the same function as the phase shift means 20 may be configured using a commercially available IC (PLL oscillation method or the like).

Next, the operation of the configuration of FIG. 1 will be described with reference to FIG.
This will be described with reference to the time chart of FIG. FIG. 2 shows a specific example in which the number of cycles M = 2, that is, a phase shift of 180 degrees.
Therefore, it is necessary to perform measurement for a period in which the fixed period T is twice. In the figure, the first fixed cycle is T1 and the next fixed cycle is T2. The sampling clock 20clk in the first constant period T1 is the same as the sampling clock 40clk from the synchronization control unit 40 (see FIG. 2B). Sampling clock 20 clk in the next constant cycle T2
Generates a sampling clock 20clk to which a 180-degree phase shift amount ΔP (see FIG. 2D) is added at the beginning of the fixed period T2.

As a result, it can be seen that the cycle time Tclk of the sampling clock 40clk supplied to the ADC 30 is either 1.0 times or 1.5 times the clock and is lower than the maximum sampling rate. Therefore, ADC3
0 indicates that the input analog signal can be received and normal AD conversion can be normally performed. On the other hand, in the fixed period T2, sampling is performed with a predetermined phase shift amount ΔP. In this specific example, since M = 2, the entire waveform data is obtained by measuring both periods of the fixed periods T1 and T2. As a result, the equivalent sampling rate is doubled. This is a great advantage of the present invention.

The means for realizing the present invention is not limited to the above embodiment. That is, in addition to the digitizer of the semiconductor test device, the equivalent sampling frequency is improved by providing the phase shift means 20 for other devices that receive a signal repeatedly generated at a constant period T and perform AD conversion using the ADC. Clearly, it is possible.

If desired, an address generating means 70 for aligning and storing the data in the AQM in the order of data sampled in units of the phase shift amount ΔP may be additionally provided.
An example of this is shown in FIG. The configuration includes a period counter 72, a first adding means 74, a gate means 76, and a second adding means 7.
8 and a register 79. The period counter 72 is initially reset to a value of “0”, and thereafter the constant period signal 4
Each time 0 s is received, +1 is counted.
Is supplied to one input terminal of the second adding means 78. The first adding means 74 receives the number of cycles M at one input terminal, receives the address signal 79 s from the register 79 at the other input terminal, and supplies data obtained by adding both to the gate 76.
The gate 76 makes the output zero only when receiving the fixed period signal 40 s, and at other times receives the accumulated data from the first adding means 74 and supplies it to the second adding means 78. The second adding means 78 outputs a cycle count signal 72 from the cycle counter 72.
s is received at one input terminal, the accumulated data 76 s from the gate 76 is received, and the sum of the two is stored in a register 79.
Supply to The register 79 receives the data from the second adding means 78, and outputs an address signal 79s latched by the sampling clock 20clk. This address signal 79s is supplied to an address input terminal of the AQM. In the configuration of the address generating means 70, if the value of the number of cycles M is an exponent of 2, such as 2, 4, 8, and 16, the address value to the lower bits of the address signal 79s is equal to the fixed periodic signal 40s. The address generation means may be configured to supply the data by the counting means which increments by 1 every time and supply the address value of the remaining upper address bits by the counting means which increments by 1 every 20 clocks of the sampling clock.

FIG. 9 shows another example of the configuration of the address generating means for aligning and storing in the AQM. That is, as shown in FIG. 9, when the value of the number of cycles M is an exponent of 2 as the configuration of the address generating means 70, the fixed cycle signal 40s
The first counting means 82 counts +1 each time a constant sampling clock 20clk is received and generates the remaining upper address bits 79H each time the constant sampling clock 20clk is received. ,
A second counting means 83 is provided, and a flip-flop 89 is provided which receives the data from the first counting means 82, latches the data by the sampling clock 20clk, and generates the lower address bits 79L of the address signal. Then, the lower address bits 79 from the flip-flop 89
L and the remaining upper address bits 79H from the second counting means 83 are supplied to the address input terminal of the storage device 50 to constitute a semiconductor test device.

The advantage that the address generation means 70 according to the above-described configuration example is arranged and stored in the AQM in the order of data sampled in the unit of the phase shift ΔP is obtained.

[0037]

According to the present invention, the following effects can be obtained from the above description. As described above, according to the present invention, the sampling clock 20 clk which receives a signal repeatedly generated at a fixed period T from the DUT and adds a predetermined phase shift amount ΔP for each of the predetermined period T times the predetermined period T times. Is provided with a phase shift means for generating an A.D.
The great advantage of being convertible is obtained. Therefore, there is no need to use a plurality of ADCs, and as a result, there is an advantage that AD conversion at a high sampling frequency can be realized with a low-cost configuration. Therefore, the technical effect of the present invention is great, and the industrial economic effect is also great.

[Brief description of the drawings]

FIG. 1 is a main configuration of a digitizer according to the present invention.

FIG. 2 is a timing chart illustrating the operation of FIG.

FIG. 3 is an example of the principle configuration of a phase shift means.

FIG. 4 is a conceptual configuration diagram of a mixed signal test system.

FIG. 5 is a main configuration of a conventional digitizer.

FIG. 6 shows a main configuration of a conventional digitizer using two ADCs.

FIG. 7 is a timing chart illustrating the operation of FIG.

FIG. 8 is a configuration example of an address generation unit that performs aligned storage in an AQM.

FIG. 9 shows another example of the configuration of the address generation means for aligning and storing in the AQM.

[Explanation of symbols]

 15 Controller 20 Phase shift means 22 M multiplier 24 1 / M frequency divider 30 A / D converter (ADC) 35 Multiplexer 40 Synchronization control unit 48 Clock source 50 Acquisition memory (AQM) 60 Filter (FLT) 70 Address generation means 72 period Counter 74 first adding means 76 gate means 78 second adding means 79 register DUT device under test PE pin electronics FTU digital tester section

Claims (4)

[Claims] 1. An analog signal under test output from a device under test (DUT) is an output signal that can be repeatedly generated at a constant period T. The signal under test is sampled by a sampling clock at predetermined time intervals Ts. In a semiconductor test apparatus equipped with a waveform digitizer using an AD converter (ADC) for converting the
A phase shift means for generating a sampling clock in which the phase of the sampling clock at the predetermined time interval Ts is changed by a predetermined phase shift amount ΔP = 360 / M (where M is the number of cycles) for each period of the number of cycles M A semiconductor test apparatus characterized by realizing a waveform digitizer that samples a signal under measurement at an equal interval of Ts / M by measuring. 2. It is assumed that the measurement is completed at a constant period T every M times, and the occurrence position of the constant period T is Q (here, Q
Is a value of 0 to M−1), and when the generation position of the sampling clock in the constant period T is N, Q +
2. The apparatus according to claim 1, further comprising an address generating means for generating an address value of (M × N), wherein the continuous code data subjected to AD conversion is stored in a storage device based on the address value. Semiconductor test equipment. 3. A cycle counter, comprising: a cycle counter for generating a cycle count signal 72s which is initially reset to “0” and is incremented by 1 each time a fixed cycle signal 40s is received thereafter; A first adding means for receiving the value at one input terminal, receiving the address signal 79s from the register 79 at the other input terminal, and adding the two, and setting the output to zero only when receiving the constant period signal 40s, At other times, the gate means for passing the accumulated data from the first adding means and the cycle count signal 72s from the cycle counter are received at one input terminal, and the accumulated data 76s from the gate means are received. A second adder for adding the two, and a register 7 for receiving the data from the second adder and latching the data with the sampling clock 20clk.
9. The semiconductor test apparatus according to claim 2, further comprising: supplying an address signal 79s from the register output to an address input terminal of the storage device. 4. The method according to claim 1, wherein when the value of the number of cycles M is an exponent of 2, the address generating means counts up by one each time the fixed cycle signal 40s is received, and generates an address value for the lower bit. The counting means, the second counting means which counts +1 each time a constant sampling clock 20clk is received, and generates the remaining upper address bits 79H. The data is latched by the sampling clock 20clk upon receiving the data from the first counting means. And a flip-flop for generating a lower address bit 79L of the address signal. The lower address bit 79L from the flip-flop and the remaining upper address bit 79H from the second counting means are stored in the memory. 3. The semiconductor test apparatus according to claim 2, wherein the test signal is supplied to an address input terminal of the apparatus.