JP2017162095A - Information processing device, information processing method, and information processing program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce data loss occurring at a time of communication abnormality and improve communication quality.SOLUTION: An information processing method for an information processing device comprising a storage area includes the steps of: transmitting obtained information to the storage area; retaining the information transmitted to the storage area; outputting an abnormality signal if an abnormality occurs to power output supplied to the storage area; obtaining the retained information if the abnormality signal is output; and transmitting the obtained information to the storage area.SELECTED DRAWING: Figure 1

Description

  The present invention relates to an information processing apparatus, an information processing method, and an information processing program.

  In recent years, communication in electronic devices has been speeded up, and at the same time, the importance of communication quality has been increasing day by day. During communication, transmitted data is generally written to a storage element on the receiving side, and it is essential in data communication that transfer data and received data match.

  However, the data being transmitted to the storage elements constituting the storage device may be lost due to a drop in the power supply voltage of the storage device during communication. In order to solve this, there is a technique for holding the output of the signal path when the power is shut off (see, for example, Patent Document 1). In the technique disclosed in Patent Document 1, data loss caused by a communication failure at the time of data writing is reduced by providing the same number of nonvolatile memory elements as the memory elements in the memory and backing up the data.

  In addition, a technique for shortening the processing time of reading data (hereinafter referred to as “verify processing”) for reading data at a written location in order to check whether writing to the storage element has been performed correctly is disclosed (for example, , See Patent Document 2). In the technique disclosed in Patent Document 2, a threshold value is set for the number of retries in the verify process to reduce the number of retries.

  However, when a voltage abnormality occurs in the memory during data transmission from the CPU (Central Processing Unit) to the memory, the data transmitted by the CPU when the voltage abnormality occurs cannot be identified and the data cannot be recovered. In addition, since the data verification process needs to be executed on software, it is difficult to specify the data transmitted when the voltage abnormality occurs.

  The present invention has been made to solve such a problem, and an object of the present invention is to reduce data loss that occurs when communication is abnormal and to improve communication quality.

  In order to solve the above problems, an aspect of the present invention is an information processing apparatus including a storage area, and includes a first information transmission control unit that transmits acquired information to the storage area, and the information transmission control unit An information holding unit that holds the information transmitted to the storage area, an abnormality detection unit that outputs an abnormality signal when an abnormality occurs in the power output supplied to the storage area, and the abnormality signal is output And a second information transmission control unit that acquires the information held in the information holding unit and transmits the acquired information to the first information transmission control unit.

  ADVANTAGE OF THE INVENTION According to this invention, the loss of the data which generate | occur | produces at the time of communication abnormality can be reduced, and communication quality can be improved.

It is a block diagram which shows typically the hardware constitutions of the information processing apparatus which concerns on embodiment of this invention. It is a figure which illustrates the format of the transfer data which concerns on embodiment of this invention. It is a sequence diagram which shows the flow of the data transfer in the information processing apparatus which concerns on embodiment of this invention. It is a flowchart which shows the flow of the abnormality process at the time of the data transfer which concerns on embodiment of this invention. It is a figure which shows the flow of a data recovery process in the information processing apparatus 1 which concerns on embodiment of this invention. It is a schematic diagram of the transfer data transmitted to the transmission buffer from the CPU according to the embodiment of the present invention. It is a schematic diagram of the transfer data transmitted to the transmission buffer from the CPU according to the embodiment of the present invention. It is a schematic diagram of the transfer data transmitted from the CPU to the EEPROM when the voltage drop according to the embodiment of the present invention occurs. It is a schematic diagram of transfer data in a state where data loss has occurred according to an embodiment of the present invention. It is a schematic diagram of the transmission buffer from which the transfer data according to the embodiment of the present invention has been erased. It is a schematic diagram of the data read from the holding | maintenance buffer which concerns on embodiment of this invention. It is a schematic diagram of the read data transmitted to the transmission buffer from the CPU according to the embodiment of the present invention. It is a schematic diagram of the data written in EEPROM which concerns on embodiment of this invention.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the present embodiment, a data transfer method when an I2C (Inter Integrated Circuit) standard is used for communication between a CPU and an EEPROM (Electrically Erasable Programmable Read Only Memory) device will be described as an example.

  First, the hardware configuration of the information processing apparatus 1 according to the present embodiment will be described with reference to FIG. FIG. 1 is a block diagram schematically illustrating a hardware configuration of the information processing apparatus 1 according to the present embodiment.

  As illustrated in FIG. 1, the information processing apparatus 1 according to the present embodiment includes a microcontroller 100, an EEPROM 105, a memory power source 106, and a reset IC 107.

  The microcontroller 100 is a control unit that controls the entire information processing apparatus 1. The EEPROM 105 is a non-volatile storage medium that is used to store data that should be retained even when the power is turned off by the electronic device. The memory power supply 106 supplies power to the EEPROM 105.

  The reset IC 107 detects the voltage of the power supply circuit, and inputs a reset signal to the CPU 101 so as not to malfunction due to a low voltage when the voltage drops. In order to reduce battery consumption, the power switch is turned off. Therefore, the reset IC 107 functions as an abnormality detection unit that notifies the CPU 101 of an abnormality signal when the power output is abnormal.

  The microcontroller 100 includes a CPU 101, a transmission buffer 102, an I2C bus 103, and a holding buffer 104. The CPU 101 is a calculation means and controls the operation of the entire information processing apparatus 1 according to a software program stored in a storage medium mounted on the information processing apparatus 1. In the present embodiment, the CPU 101 is a second information transmission control unit that controls transmission / reception of information in the information processing apparatus 1 in particular.

  The transmission buffer 102 is a storage area for temporarily storing data transmitted from the CPU 101. The transmission buffer 102 transmits data to the I2C bus 103 and the holding buffer 104 in parallel. Accordingly, the transmission buffer 102 functions as a first information transmission control unit.

  The I2C bus 103 is a bus including SCL (serial clock) and SDA (serial data) as signal lines, and is used as an interface in this embodiment. The holding buffer 104 is a storage area for temporarily storing data received from the transmission buffer 102, and functions as an information holding unit.

  In this embodiment, the transfer data is sent from the CPU 101 to the transmission buffer 102, and then transmitted from the transmission buffer 102 in parallel to the I2C bus 103 and the holding buffer 104. Therefore, when data is transmitted, data to be transmitted next is stored in the transmission buffer 102, and data being transferred from the transmission buffer 102 to the EEPROM 105 is stored in the holding buffer 104.

  Therefore, when an abnormality occurs in the memory power supply 106 during data transfer from the transmission buffer 102 to the EEPROM 105, the transfer data held in the holding buffer 104 can be read and the same transfer data can be transmitted to the EEPROM 105 again.

  The transmission buffer 102 and the holding buffer 104 are FIFO (First In First Out) type storage devices. Therefore, when new data is set in a state where the data stored in the transmission buffer 102 and the holding buffer 104 is not erased, the previously stored data is transmitted.

  The transmission buffer 102 and the holding buffer 104 are not limited to FIFO storage devices. For example, when data is input, a storage device that stores input data after automatically deleting information stored in the storage device so far may be used. In this case, the CPU 101 does not need to control to reset the buffer.

  Next, a data transfer format according to the present embodiment will be described with reference to FIG. FIG. 2 is a schematic diagram of a data transfer format of the I2C bus 103 according to the present embodiment. In the I2C standard, a device that starts communication is “master”, and a device that is selected as a communication destination is “slave”. Each device is given a unique address on the bus, and the “master” designates this device as a communication destination device.

  Therefore, in this embodiment, the “master” that generates a clock and controls the start or end of data communication is the CPU 101. The “slave” that is controlled by the CPU 101 by an address that is unique on the bus is the EEPROM 105.

  As shown in FIG. 2, in the I2C bus 103, when the CPU 101 and the EEPROM 105 transition from the non-communication state to the communication state (hereinafter referred to as “start condition”), the data transfer from the CPU 101 is started and immediately thereafter. The slave address is input to. The slave address is fixed to 0 or 1 by connecting power supply or GND to the external terminal of the EEPROM 105, and the value is determined for each device.

  The slave address is an address of a device to be communicated, and is specified with a data length of 7 bits. Then, whether to transmit or receive data from the master is specified by bits to the device specified by the slave address. In the present embodiment, as shown in FIG. 2, data for writing data to the EEPROM 105 is transmitted from the CPU 101.

  At this time, if the slave address input from the CPU 101 is a value set in the external terminal of the EEPROM 105, a response is returned from the EEPROM 105, so that "ACK" (response is received) is obtained. In addition, the CPU 101 that has received “ACK” establishes communication with the EEPROM 105.

  At this time, if the slave address input from the CPU 101 is different from the value set in the external terminal of the EEPROM 105, a response is not returned from the EEPROM 105, so the response is “No ACK” (no response). Further, the CPU 101 that has input the slave address also detects that there is an abnormality in data transfer.

  In the present embodiment, the following description will be made assuming that the CPU 101 and the EEPROM 105 are in a communication state.

  Next to the slave address, a word address which is identification information for uniquely specifying a storage area on the EEPROM 105 is input. Data to be input next to the word address is written to an address on the EEPROM 105 designated by the word address. Therefore, the EEPROM 105 functions as a storage control unit. Further, every time 8-bit data is input, “ACK” indicating that data transfer has been performed correctly is issued.

  In the information processing apparatus 1 having such a configuration, when an abnormality occurs in the memory power source 106 at the time of data transfer, it is a gist of the present invention to recover data lost during transmission from the CPU 101 to the EEPROM 105. is there.

  Next, the flow of data transfer in the information processing apparatus 1 according to this embodiment will be described with reference to FIG. FIG. 3 is a sequence diagram illustrating a flow of data transfer in the information processing apparatus 1 according to the present embodiment.

  First, data to be transferred (hereinafter referred to as transfer data) is input from the CPU 101 to the transmission buffer 102 (S301). The transmission buffer 102 accumulates the received transfer data in its internal storage area (S302). Then, the transmission buffer 102 sends the accumulated transfer data to the EEPROM 105 and the holding buffer 104 (S303).

  The EEPROM 105 writes and stores the received transfer data at the address on the EEPROM 105 designated by the word address (S304). The holding buffer 104 stores the received transfer data in a storage area inside the holding buffer 104 (S305).

  In the present embodiment, the processing described above is performed and data is transmitted from the CPU 101 to the EEPROM 105. At this time, the power supply voltage may unexpectedly drop in the memory power supply 106 that supplies power to the EEPROM 105. In such a case, transfer data being transmitted from the CPU 101 to the EEPROM 105 is lost, and transfer data cannot be normally written.

  Therefore, in this embodiment, the transfer data stored in the holding buffer 104 is transmitted again to the EEPROM 105 to restore the data, and data transfer between the CPU 101 and the EEPROM 105 is performed so that the transfer data is normally written.

  FIG. 4 is a flowchart showing a flow of abnormality processing during data transfer according to the present embodiment. Hereinafter, the flow of processing when a voltage drop occurs in the memory power source 106 when data is transferred from the CPU 101 to the EEPROM 105 will be described with reference to FIG.

  When the CPU 101 and the EEPROM 105 transition from the non-communication state to the communication state and a start condition is output (S401), the transmission buffer 102 transmits the transfer data to the holding buffer 104 simultaneously with the transfer data to the EEPROM 105. (Mirroring start, S402). The holding buffer 104 stores the received transfer data in a storage medium (mirroring).

  If a voltage drop occurs in the memory power supply 106 while transfer data is being sent from the CPU 101 to the EEPROM 105, the reset IC 107 detects the voltage drop and notifies the CPU 101 of the voltage drop. When the notification that the voltage drop is detected is received from the reset IC 107 (S403 / Yes), the CPU 101 executes a data recovery sequence (S405). Specific processing performed in the data recovery sequence will be described later.

  If the notification that the voltage drop is detected is not received from the reset IC 107 by the time the stop condition is output (S404 / Yes) (S403 / No), the CPU 101 ends the transmission of the transfer data and communicates with the EEPROM 105. To no communication.

  Next, the flow of the data recovery sequence in the information processing apparatus according to the present embodiment will be described with reference to FIG. FIG. 5 is a sequence diagram showing a flow of data recovery processing according to the present embodiment. As shown in FIG. 5, the reset IC 107 monitors the power supply voltage of the memory power supply 106 while data transfer from the CPU 101 described in FIG. 3 to the EEPROM 105 is performed (S501).

  FIG. 6 is a schematic diagram of transfer data transmitted from the CPU 101 to the transmission buffer 102. In the schematic diagram of transfer data to be described later, an “ACK” response from the EEPROM 105 is used as a data boundary, and data units are described as A to E,. Therefore, as described in FIG. 2, A: slave address, B: 1st word address, C: 2nd word address, D, E: data are transferred. The transmission buffer 102 sends the transfer data received from the CPU 101 to the holding buffer 104.

  When the data sent from the CPU 101 to the transmission buffer 102 is sent to the EEPROM 105, the CPU 101 inputs the transfer data shown in FIG. The transfer data shown in FIG. 7 is F: slave address, G: 1st word address, H: 2nd word address, I, J: data.

  If a voltage drop occurs in the memory power supply 106 during data transfer from the CPU 101 to the EEPROM 105 (S502), the reset IC 107 detects the voltage drop (S503), and a voltage drop occurs in the memory power supply 106 in the CPU 101. (S504). FIG. 8 exemplifies transfer data transmitted from the CPU 101 to the EEPROM 105 when a voltage drop occurs.

As shown in FIG. 8, when the timing at which the voltage drop generated in the memory power source 106 and respectively T _2, T _4, the transfer data of the timing T ₂ and timing T _4, the data loss. In FIG. 8, the lost data is indicated by broken lines. When a voltage drop occurs in the memory power supply 106, data loss occurs in data written from the CPU 101 to the EEPROM 105 as shown in FIG.

Therefore, the CPU 101 that has received a notification indicating that a voltage drop has occurred in the memory power source 106 from the reset IC 107 interrupts transmission of the transfer data (S505) and executes initialization of the transmission buffer 102 (S506). In the present embodiment, a following explanation assumes that the voltage drop of the memory power supply 106 is generated at timing T ₂ and timing T _4.

When initialized by the CPU 101, the transfer data stored in the transmission buffer 102 are all erased as shown in FIG. 10 (S507). When the CPU 101 initializes the transmission buffer 102, the CPU 101 reads data stored in the holding buffer 104 as shown in FIG. 11 (S508). In FIG. 11, T ₂ and T ₄ indicate timings at which voltage drops occur in the memory power source 106, respectively.

  Since the transfer data stored in the holding buffer 104 is not affected by the voltage drop, no loss of data occurs in the transfer data even at the timing when the voltage drop occurs in the memory power supply 106. The holding buffer 104 sends the stored data to the CPU 101 (S509).

  The CPU 101 transmits the read data acquired from the holding buffer 104 to the transmission buffer 102 (S510). The transmission buffer 102 receives the read data from the CPU 101 and stores it in the storage medium (S511). As shown in FIG. 12, the CPU 101 transmits the transfer data read from the holding buffer 104 without data loss to the transmission buffer 102. In FIG. 12, the read data is shaded.

  When the CPU 101 transmits the read data acquired from the holding buffer 104 to the transmission buffer 102, the CPU 101 initializes the holding buffer 104 (S512). When initialized by the CPU 101, all transfer data stored in the holding buffer 104 is erased (S513).

  When the read data is sent out, the CPU 101 resumes transfer of the transfer data (S514). After the restart, data is written to the missing portion by the transfer data sent from the transmission buffer 102 to the EEPROM 105 as shown in FIG. In FIG. 13, the read data is indicated by shading.

  As described above, in this embodiment, when the transfer data is sent from the CPU to the memory, the transfer data is mirrored in an area that can be read by the CPU. Therefore, when a voltage abnormality occurs in the memory power supply, the transfer data mirrored by the CPU can be transmitted to the memory again.

  Therefore, even when a voltage abnormality occurs in the memory power supply when data is transferred from the CPU to the memory, the data can be restored from the mirrored data to prevent data loss and improve communication quality. Is possible.

  In the present embodiment, the data transfer method when communicating using the I2C standard has been described as an example. However, if the information processing apparatus has the same hardware configuration as that illustrated in FIG. Regardless of the communication standard, the same effect can be obtained by applying the present invention.

1 Information processing apparatus 100 Microcontroller 101 CPU
102 Transmission buffer 103 I2C bus 104 Holding buffer 105 EEPROM
106 Memory power supply 107 Reset IC

JP 2000-323671 A JP 2006-350898 A

Claims (7)

An information processing apparatus comprising a storage area,
A first information transmission control unit for transmitting the acquired information to the storage area;
An information holding unit for holding the information transmitted to the storage area by the first information transmission control unit;
An abnormality detection unit that outputs an abnormality signal when an abnormality occurs in the power output supplied to the storage area;
A second information transmission control unit for acquiring the information held in the information holding unit when the abnormal signal is output, and transmitting the acquired information to the first information transmission control unit;
An information processing apparatus comprising: The second information transmission control unit is
When the abnormal signal is received, the information acquired by the first information transmission control unit is deleted, the information held in the information holding unit is acquired, and transmitted to the first information transmission control unit The information processing apparatus according to claim 1. The second information transmission control unit is
Obtaining the information transmitted from the first information transmission control unit to the storage area at the timing when the abnormal signal is output from the information holding unit, and transmitting the information to the first information transmission control unit. The information processing apparatus according to claim 1, wherein the information processing apparatus is characterized. The information is
A slave address that uniquely identifies a storage device configured by the storage area;
A word address uniquely identifying the storage area in the storage device;
4. The information processing apparatus according to claim 1, further comprising: data stored in the storage area specified by the slave address and the word address. 5. The abnormality detection unit
5. The information processing apparatus according to claim 1, wherein the abnormality signal is output when a voltage of a power supply circuit of the information processing apparatus decreases. An information processing method in an information processing apparatus including a storage area,
Send the acquired information to the storage area,
Holding the information sent to the storage area;
When an abnormality occurs in the power output supplied to the storage area, an abnormality signal is output,
Acquiring the information held when the abnormal signal is output, and transmitting the acquired information to the storage area;
An information processing method characterized by the above. An information processing program in an information processing apparatus having a storage area,
Transmitting the acquired information to the storage area;
Holding the information transmitted to the storage area in a storage area different from the storage area;
Outputting an abnormality signal when an abnormality occurs in the power output supplied to the storage area;
Acquiring the information held in the different storage area when the abnormal signal is output, and transmitting the acquired information to the storage area;
An information processing program for causing a computer to execute.