JP2016197945A - Switching power supply and image forming apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To save power of a switching power supply and suppress a reduction in output voltage when a sudden change in load occurs.SOLUTION: A switching power supply comprises: a switching element that is connected with a primary winding of a transformer; detection means that detects a signal according to a current flowing on a primary side of the transformer; feedback means that feeds back a signal according to a voltage output from a secondary winding on a secondary side of the transformer to the primary side; change amount detection means that detects the amount of change in the signal from the feedback means; and time determination means that compares the signal from the feedback means with a reference value and limits an on-time of the switching element according to a result of the comparison. When the amount of change detected by the change amount detection means is equal to or more than a predetermined value, the time determination part releases the limitation of the on-time of the switching element.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a switching power supply, and more particularly to a switching power supply having a burst mode in which a switching operation is stopped for a certain period.

  2. Description of the Related Art A switching power supply that controls an output voltage using an IC is known as a low-voltage power supply for electronic devices. In recent years, there has been a trend to further reduce the power consumption in a state where the operation of the electronic device is on standby, and there is a demand for reducing the power consumption of the switching power supply itself. As a configuration for reducing the power consumption of the switching power supply, for example, Patent Document 1 discloses a switching operation (hereinafter referred to as a burst operation) so that the on period is shortened and the off period is lengthened when the load state of the switching power supply is light. A method for controlling the above has been proposed.

  As an operation state of the switching power supply, for example, there is a heavy load state in which a device to be applied is in operation. And in order to reduce power consumption, the device is not in operation, a part of it is in a light load state that is stopped, and a medium load that is in a standby state so that it can start operation at any time There is a state. Conventionally, a continuous switching operation has been performed in this medium load state. However, in order to further reduce power consumption, it is effective to perform a burst operation.

JP 2008-245419 A

  Performing burst operation at medium load in a switching power supply is effective for reducing power consumption, but if load current increases rapidly during burst operation, power can be sufficiently supplied to the load temporarily. There is a possibility of disappearing.

  The present invention has been made to solve the above problems, and aims to realize power saving of a switching power supply and to suppress a decrease in output voltage when a sudden load fluctuation occurs. .

  In order to achieve the above object, a switching power supply according to the present invention includes a transformer having a primary winding insulated from a primary side and a primary winding on the primary side, a switching element connected to the primary winding, and the transformer. Detecting means for detecting a signal corresponding to the current flowing in the primary side, feedback means for feeding back a signal corresponding to the voltage output from the secondary winding on the secondary side to the primary side, and A change amount detecting means for detecting a change amount of the signal; and a time determining section that compares a signal from the feedback means with a reference value and limits an ON time of the switching element according to the comparison result, and the time determination When the change amount detected by the change amount detection means is a predetermined value or more, the unit releases the restriction on the ON time of the switching element.

  The image forming apparatus of the present invention further includes an image forming unit and a switching power supply that supplies power to the image forming apparatus. The switching power supply is insulated on the primary side and the secondary side, and the primary side is connected to the primary side. A transformer having a winding, a switching element connected to the primary winding, detection means for detecting a signal corresponding to a current flowing through the primary side of the transformer, and a secondary winding output from the secondary side. A feedback unit that feeds back a signal according to a voltage to the primary side, a change amount detection unit that detects a change amount of a signal of the feedback unit, a signal from the feedback unit and a reference value are compared, and according to a comparison result A time determining unit that limits an on-time of the switching element, and the time determining unit has a change amount detected by the change amount detecting means less than or equal to a predetermined value. For, and cancels the limit of the ON time of the switching element.

  As described above, according to the present invention, it is possible to realize power saving of a switching power supply and to suppress a decrease in output voltage when a sudden load fluctuation occurs.

The figure which shows the structure of the switching power supply of Example 1. Detailed view of the power supply IC configuration of the switching power supply according to the first embodiment The figure which shows the operation | movement waveform of the switching power supply of Example 1. The figure which shows the structure of the switching power supply of Example 2. Detailed view of the power supply IC configuration of the switching power supply according to the second embodiment The figure which shows the operation | movement waveform of the switching power supply of Example 2. The figure which shows the structure of the switching power supply of Example 3. The figure which shows the operation | movement waveform of the switching power supply of Example 3. Diagram showing the configuration of a general switching power supply Diagram showing the operation waveform of a typical switching power supply The figure which shows the state at the time of heavy load of a general switching power supply, medium load, and light load Diagram showing the configuration of the pulse limited power supply The figure which shows the operation waveform of the pulse limit electricity reduction Diagram explaining application example of switching power supply

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. The following embodiments do not limit the invention according to the claims, and all combinations of features described in the embodiments are not necessarily essential to the solution means of the invention.

  First, the configuration and operation of a switching power supply that is a premise of the present invention will be described.

  Hereinafter, the configuration and operation of a general switching power supply in each load state will be described with reference to FIG. FIG. 9 is a diagram illustrating a configuration of a general switching power supply, FIG. 10 is a diagram illustrating a switching operation when the switching power supply is under heavy load, and FIG. 11A is a diagram when the switching power supply is under heavy load. It is a figure showing a continuous operation state.

  In FIG. 9, 10 is a commercial AC power source. The AC voltage input from 10 is rectified by the diode bridge 11, smoothed by the primary electrolytic capacitor 101, and becomes a substantially constant voltage Vh. On the other hand, at the same time, a voltage is supplied to the starting VH terminal 103h of the power supply IC 103 via the resistance element 102, and the power supply IC turns on the FET 105. When the FET 105 is turned on, a drain current Id flows through the FET 105 through the primary winding 104p on the primary side of the insulating transformer 104, where the primary side and the secondary side are insulated (period t10 in FIG. 10). In this period t10, the current Id flowing through the switching FET 105 increases linearly with time. The current Id is converted into the voltage Vis by the current detection resistor 106 and supplied to the current detection IS terminal 103 i of the power supply IC 103.

  On the other hand, the feedback FB terminal 103 f of the power supply IC 103 is connected to a photocoupler 109 for feeding back a signal corresponding to the voltage on the secondary side from the secondary side to the primary side of the isolation transformer 104. The voltage Vfb is supplied from the Vcc inside the power supply IC via the resistor 308. Vfb is an error amplification signal of the output voltage of the switching power supply, and decreases when the output voltage is larger than a specified value (reference value), and increases when the output voltage is smaller than a specified value (reference value). . The power supply IC 103 turns off the FET 105 when Vis rises and becomes slightly larger than Vfb (timing t11 in FIG. 10). When the FET 105 is turned off, Id instantaneously becomes zero. Then, the drain-source voltage Vds of the FET 105 rises and becomes a substantially constant voltage Vh + Vl (period t12 in FIG. 10).

  In addition to the primary winding 104p, a secondary winding 104s and an auxiliary winding 104h are wound around the transformer T1. 104s and 104h are configured to have different winding directions with respect to 104p (so-called flyback coupling). After the FET 105 is turned off (period t12 in FIG. 10), a positive pulse voltage is induced in 104s and 104h. The pulse voltage induced in 104s is rectified and smoothed by the secondary rectifier diode 121 and the secondary smoothing capacitor 122, and becomes a substantially constant output voltage Vout. At this time, assuming that the forward voltage of the diode 121 is Vf121 and the number of turns of the primary winding 104p and the secondary winding 104s is Np and Ns, respectively, the voltage Vl is approximately expressed by the following equation (1) using Vout. expressed.

  On the other hand, when the positive pulse voltage induced in 104h is V104h, V104h is approximately expressed by the following equation (2) using Vout when the number of turns of the auxiliary winding 104h is Nh.

  The current If flowing through 104s decreases linearly and eventually becomes zero. Then, Vds begins to fall. Now, Vds is similar to the terminal voltage V104h of the auxiliary winding 104h. V104h is supplied to the BTM terminal 103b of the power supply IC 103. The power supply IC 103 detects a time (timing t13 in FIG. 10) when V104h becomes a falling edge and becomes zero, and turns on the FET 105. Thereafter, the operation is repeated from t10 to t13. When the FET 105 is turned on again in the period t14 in FIG. 10, the drain current Id begins to flow through the FET 105 again through the primary winding 104p of the insulating transformer 104.

  In such a heavy load, as shown in FIG. 11A, the FET 105 continuously oscillates, so that the switching pulse is continuously output, and the feedback voltage (FB terminal voltage) exceeds the reference voltage 304 and the output. The state where the voltage is maintained at the specified value is continued.

  Next, the operation of the power supply IC 103 will be described in detail.

  Hereinafter, the operation of the power supply IC 103 during the heavy load operation shown in FIG. 11A will be described in detail with reference to the internal block diagram of the power supply IC 103 shown in FIG. 9 and FIG.

  In FIG. 9, the voltage Vis input to the IS terminal 103i and the voltage Vfb input to the FB terminal 103f are compared with a comparison unit 302c of a pulse width determination unit 302 (also referred to as a time determination unit) for determining the driving time of the FET 105. Compared by. As shown in FIG. 10 described above, when the FET 105 is on, Vfb> Vis and the output of the comparator 302c is L level (Low level). Accordingly, the reset input of the set / reset flip-flop 310 subsequent to the pulse width determination unit 302 is at the L level, and the Q output of 310 maintains the output state (H level: High level). The Q output is connected to the OUT terminal 103o of the power supply IC 103, and is supplied to the FET 105 via the gate resistor 107 as the gate voltage Vg of the FET 105. Therefore, the FET 105 is kept on (period t10 in FIG. 10).

  As Id increases, when Vis increases and becomes slightly larger than Vfb, the output of the comparison unit 302c becomes H level. Accordingly, the flip-flop 310 is reset and the Q output becomes L level. Therefore, the OUT terminal 103o becomes L level, and the FET 105 is turned off (timing t11 in FIG. 10).

  Next, when the current If flowing through 104s decreases to zero, V104h decreases to a negative voltage. V104h is supplied to the BTM terminal 103b. The output of the bottom detection circuit 307 inside the power supply IC 103 is inverted from the previous Low level (L level) to the High level (H level) when V104h falls to zero at the falling edge, and then maintains the H level. .

  The output of the bottom detection circuit 307 is input to the logical product circuit 309. Since the H level described later is input to the other input of the AND circuit 309, the output of the AND circuit 309 becomes the H level. In response to this, the flip-flop 310 is set, and the Q output becomes the H level. Therefore, the OUT terminal 103o becomes H level, and the FET 105 is turned on (period t14 in FIG. 10).

  The output of the bottom detection circuit 307 is cleared when the output of the comparison unit 302c becomes H level, that is, when Vis rises and becomes slightly larger than Vfb, and the FET 105 is turned off. Return to level (t15).

  Next, the operation when the switching power supply is in a middle load (the load is smaller than that in the heavy load described above) will be described. FIG. 11B shows an operation at the time of middle load of the switching power supply. In FIG. 11B, there is a period in which switching stops (period in which pulses are not continuously output) with respect to the state of FIG.

  In the case of a medium load as shown in FIG. 11B, if the operation of repeating t10 to t13 in FIG. 10 is performed during the period of t103, the power consumed on the secondary side is more than the power supplied via the insulating transformer 104. Is smaller. Therefore, Vfb falls below the reference voltage 304 (timing t104 in FIG. 11B). Then, the output of the load state determination unit 303 in the power supply IC 103 becomes L level. The output of 303 is input to the logical product circuit 309. Therefore, while the output of 303 is at the L level, the output of the AND circuit 309 is at the L level regardless of the output level of the bottom detection circuit 307, and the Q output of the flip-flop 310 continues to be the previous L level. To do. Therefore, the OUT terminal 103o becomes the L bell, and the FET 105 continues to be off (period t105 in FIG. 11B). At this time, power supply to the secondary side via the insulating transformer 104 is temporarily stopped.

  When the FET 105 continues to be in the OFF state, the output of the bottom detection circuit 307 becomes H level when If flowing through 104s becomes zero (t13 in FIG. 10). Since Vfb temporarily stops the power supply to the secondary side, it rises gently, and when the pulse stop voltage 304 is exceeded, the output of the load state determination unit 303 becomes H level (FIG. 11 ( b) timing t106). At this time, the Q output of the flip-flop 310 becomes H level. Further, the relationship between Vfb and Vis at this time is Vfb> Vis because the FET 105 continues to be off. Therefore, the OUT terminal becomes H-bell, and the FET 105 is turned on. Then, the switching operation from t10 to t13 (FIG. 10) is repeated until Vfb falls below the pulse stop voltage 304 (t107).

  As described above, the control for forcibly stopping the switching operation of the FET 105 (so-called burst operation) is performed during medium load. Thereby, the loss by switching of FET105 can be reduced and the power consumption of an apparatus can be reduced.

  Next, the operation at light load will be described in detail. Recently, there is a strong demand for reducing standby power of electronic devices. In a switching power supply, power consumption at light load corresponds to this standby power.

  FIG. 11C shows the operation at light load. When the load is light, the FET 105 forced off time during the period t203 is longer than the time during the medium load period t105 shown in FIG. This is because the load current on the secondary side of the transformer is small and the output voltage drops slowly. Further, since the power consumption on the secondary side is small, the period during which the FET 105 is turned on (period t201, the number of on-times per unit time, the time of one pulse) is shorter than t103 shown in FIG. Therefore, the burst operation frequency Fbst_low at the time of light load is lower than the burst operation frequency Fbst_mid at the time of medium load, so that the loss due to switching of the FET 105 can be reduced and the power consumption of the device can be further reduced.

As described above, the burst frequency Fbst_mid (burst operation frequency) at medium load generally has the following relationship with the burst frequency Fbst_low (burst operation frequency) at light load.
Fbst_mid> Fbst_low (3)

  Next, the relationship between the output load condition, the pulse width of the FET 105, and the number of switching operations will be described. In order to reduce the power consumption at the time of the light load described above, it is important to reduce the number of switchings in addition to lowering the switching frequency of the FET 105. This is because when the number of times of switching increases, switching loss that occurs when the switching FET 105 is turned on and off increases, resulting in an increase in power consumption.

  As described above, the power supply IC 103 compares the terminal voltage Vfb of the feedback terminal 103f and the reference voltage 304 to determine the number of continuous switching. Further, the pulse width of the switching FET 105 is determined by comparing the voltage Vis input to the IS terminal 103i with the voltage Vfb input to the feedback terminal 103f. That is, since the continuous number of times of switching is continued until the terminal voltage Vfb of the feedback terminal 103f falls below the reference voltage 304, the number of times of switching generally increases as the load current increases.

Therefore, the relationship of the following equation is generally established between the number Sbst_nm of continuous switching at medium load (frequency in burst operation) and the number of continuous switching Sbst_nl at light load (frequency in burst operation).
Sbst_nm> Sbst_nl (4)

From the above, it can be seen that the number of times of switching per unit time is as follows.
Number of continuous switching times under heavy load Snh (continuous switching operation, no limit)
Number of continuous switching operations at medium load Snm (frequency within burst operation)
Number of continuous switching times at light load Snl (frequency within burst operation)
Snh>Snm> Snl (5)

Further, the pulse width when the switching FET 105 is turned on becomes longer as the difference between Vis and Vfb becomes larger, and becomes longer as the load current becomes larger. However, there is a possibility that the maximum pulse width at the time of heavy load and that at the time of medium load are equal depending on the relationship of the above-described equation (5) and the response of the feedback loop. That is, the following equation is generally established for the maximum pulse width PWh_Max at heavy load, the maximum pulse width PWm_Max at medium load, and the maximum pulse width PWl_Max at light load.
PWh_Max≈PWm_MAX> PWl_MAX (6)

  As described above, in order to reduce the power consumption of the switching power supply not only at the light load but also at the middle load, it is required to increase the pulse width when the FET 105 is turned on and reduce the number of times of switching. Further, as described above, the power supply IC 103 determines the ON time of the FET 105 according to the comparison result by the comparison unit 302c of the pulse width determination unit 302 between the voltage Vis input to the IS terminal 103i and the voltage Vfb input to the FB terminal 103f. Is determined. In a switching power supply device, the output ripple is large because burst operation is performed in the load region immediately before switching from switching operation at medium load to switching operation at heavy load, although the load current is relatively large. Become. That is, the output ripple increases during the transition period from heavy load to medium load.

  In FIG. 11B described above, since the load current is relatively large at the time of medium load, the change in the output voltage and the FB terminal voltage during the off period of FET 105 (the period during which forced off is performed in the burst operation) is also large. For this reason, the pulse width when the FET 105 is turned on, which is determined by the comparator 302c, also becomes longer. When this pulse width is long, the instantaneous power transmitted to the secondary side via the insulating transformer 104 is also large, and the change in the output voltage and the FB terminal 103f voltage Vfb during the ON period of the FET 105 is also large. As a result, the ripple voltage of the output voltage becomes large.

  Further, as described above, the burst operation frequency Fbst_low at the time of light load and the burst operation frequency Fbst_mid at the time of medium load tend to be lower than those in the past due to the recent trend of low power consumption. When the burst operation frequency Fbst_mid is lowered, the pulse width when the FET 105 is turned off and when the FET 105 is turned on becomes longer, and the ripple of the output voltage tends to appear more prominently.

  In order to solve the above problem, during the burst operation, the pulse width when the switching element is on is limited to reduce the instantaneous power transmitted to the secondary side via the insulating transformer. As a result, there is a technique for suppressing changes in the output voltage during the on-period of the switching element and the voltage fed back to suppress output ripple at the time of medium load.

  Hereinafter, an operation of a switching power supply (hereinafter referred to as a pulse width limited power supply) in which the pulse width when the switching element is turned on is limited will be described. FIG. 12 shows the configuration of the pulse width limited power supply. The same components as those of the switching power supply described with reference to FIG. FIG. 13 shows operation waveforms representing the characteristics of the pulse width limited power supply. 9 is a configuration in which a pulse width limiting unit 305 in the pulse width determining unit 302 in the power supply IC 103 and a reference voltage 306 used for determination to limit the upper limit of the driving pulse time of the switching element are added.

First, the reference voltage 304 as the first reference voltage and the reference voltage 306 as the second reference voltage have the following relationship.
Reference voltage 306> reference voltage 304 (7)

This is because the pulse width limiting unit 305 has hysteresis characteristics. The pulse width limiter 305 includes a pulse width limit determiner 305a, a mask signal generator 305b, a timer 305c, and an OR circuit 305d. The final output of the pulse width limiting unit 305 is connected to the reset terminal of the flip-flop 310. The operation of the pulse width limiting unit 305 is as follows.
(1) Pulse width limitation / restriction determination (2) Counting H level output duration of Q output of flip-flop 310 by timer 302c (3) Mask signal (4) determined by (1), (2) ) Determination of final output from mask signal and comparison unit 302c First, in (1), the voltage Vfb, the reference voltage 304, and the reference voltage 306 input to the FB terminal 103f are compared by the pulse width limit determination unit 305a, and according to the comparison result Determines whether the pulse width is restricted or released. Specifically, when Vfb falls below the reference voltage 304, an H level is output to the mask signal generation unit 305b to limit the pulse width, and when Vfb exceeds the reference voltage 306, L falls to the mask signal generation unit 305b. The level is output and the pulse width restriction is released. When Vfb is between the reference voltage 304 and the reference voltage 306, the previous state is maintained. As described above, the pulse width determining unit 302 performs the operation as described above, thereby realizing the pulse width limiting operation of the FET 105 with hysteresis characteristics.

  The counting in (2) is performed only when the output of the pulse width restriction determination unit 305a is at the H level. When the output of the pulse width limit determination unit 305a is at the H level, the output of the flip-flop 310 is at the H level, and at the same time, the mask signal generation unit 305b counts the H level duration of the Q output of the flip-flop 310 by the timer 305c. To start. When the result of (1) is the output of the pulse width restriction determination unit 305a or the Q output of the flip-flop 310 is L level, the count is not performed.

  The mask signal in (3) is generated by the mask signal generation unit 305b, and whether the result of the comparison unit 302c is valid (this state is set as a mask release state) or invalid (this state is set as a mask state). decide. Here, the mask signal generation unit 305b sets the mask release state when the timer value in (2) is less than a predetermined value, and outputs the L level. On the other hand, triggered by the timer value in (2) being equal to or greater than a predetermined value, the H level is output for several hundred nanoseconds to clear the counter.

  In (4), a signal to the flip-flop 310 which is the final output is output. Here, the OR circuit 305d is used to output the H level when the output of the mask signal generation unit 305b in (3) or the output of the comparison unit 302c is in the H level state. If the output of the mask signal generation unit 305b is H level, the signal to the flip-flop 310 is H output even if the output of the comparison unit 302c is L level.

  Here, the feature of the pulse width limited power supply is the operation at the time of medium load. The operation at the time of medium load will be described in association with the operation waveform of FIG. In the pulse width limited power supply, the output of the flip-flop 310 becomes H level, and at the same time, the pulse width limiting unit 305 counts the H level duration of the Q output of the flip-flop 310 by the timer 305c in the pulse width limiting unit 305. Start. When the FET 105 is turned on, in the conventional example shown in FIG. 9, the power supply IC 103 turns off the FET 105 when Vis rises and becomes slightly larger than Vfb. On the other hand, in the pulse width limited power supply, the pulse width limiting unit 305 limits the pulse width by the operations (1) to (4) described above. Even if Vis does not reach Vfb, the output of the pulse width limiter 305 becomes H level when the timer 305c reaches a predetermined value by the operations (1) to (4) described above. As a result, the Q output of the flip-flop 310 becomes L level, and the FET 105 is turned off.

  Under certain medium load conditions, as described above, if the FET 105 is turned off before Vis reaches Vfb, the power transmitted to the secondary side instantaneously becomes smaller than that in the conventional example shown in FIG. For this reason, the number of times the FET 105 is turned on per burst period is larger than that of the conventional power supply. This means that the necessary power is supplied by reducing the instantaneous power supplied at a time and increasing the number of switching operations during burst operation at medium load.

  Thus, in the burst operation, the pulse width limiter 305 limits the ON pulse width of the FET 105. As a result, when the instantaneous power supplied at one time is reduced, changes in the output voltage and the FB terminal voltage also become gradual, and as a result, the ripple voltage of the output voltage can be reduced. Further, since the pulse width limited power supply sets the upper limit of the ON pulse width of the FET 105 in the burst operation, there is a load condition that makes it impossible to supply sufficient power on the secondary side. In such a case, the state transitions from a medium load to a heavy load.

  In FIG. 13, after the timing t309, it is an explanatory diagram under a load condition for shifting from a medium load to a heavy load. Details are described below. In FIG. 13, when the feedback terminal voltage Vfb exceeds the reference voltage 304 at timing t <b> 309, the switching operation is repeated while the pulse width limiting unit 305 limits the pulse width for turning on the FET 105. Thereafter, when the load current increases and the output voltage decreases again at t310, sufficient power cannot be supplied for the required power consumption on the secondary side, and Vfb rises to the reference voltage 306 (timing t311).

  When the feedback terminal voltage Vfb exceeds the reference voltage 306, the pulse width restriction determination unit 305a outputs an L level to the mask signal generation unit 305b to release the pulse width restriction.

  Thereby, the power supply IC 103 turns on the FET 105 until Vis rises and becomes slightly larger than Vfb as in the conventional example shown in FIG. 9 (after t311).

Next, the operation at light load will be described below. In the pulse width limited power supply, the pulse width limiter 305 limits the pulse width of the FET 105 on in burst operation. When such pulse width restriction is performed, the number of switching operations increases, and there is a concern about an increase in power consumption at the time of a light load that requires a reduction in power consumption. In consideration of such a situation, the pulse width limited power supply is set so that the pulse width determined by the pulse width limitation is larger than the pulse width at light load. That is, the following relationship is established, assuming that the maximum pulse width determined by the pulse width limitation is PLSlim, and the pulse width determined by comparing Vfb and Vis at light load is PLSlow. Thereby, the power consumption at the time of a light load can be made comparable as a prior art example.
PLSlim> PLSlow (8)

  As described above, in the pulse width limited power supply, by adding the pulse width limiting unit 305 and the reference voltage 306, it is possible to reduce the output ripple at the middle load without increasing the power consumption at the light load. .

  However, in the state where the pulse width is limited, there is a problem as described below. For example, when the load current increases rapidly, the pulse width is limited and the instantaneous power transmitted to the secondary side via the insulating transformer is reduced, so that sufficient power cannot be supplied from the primary side. Therefore, the power supply from the primary side is insufficient with respect to the required power on the secondary side, and the output voltage decreases. The output voltage continues to decrease until the pulse restriction is released.

  At this time, the voltage specification required for the electronic device cannot be satisfied.

  Hereinafter, a countermeasure against such a sudden increase in load current will be specifically described based on an embodiment of the present invention.

Example 1
FIG. 1 shows a switching power supply according to the first embodiment. The same components as those of the switching power supply described with reference to FIGS. 9 and 12 described above are denoted by the same reference numerals and description thereof is omitted. FIG. 2 shows a detailed diagram of an internal circuit of the pulse width limiting unit 305 in the power supply IC 103 according to the first embodiment. Further, FIG. 3 shows operation waveforms representing the characteristics of the switching power supply according to the first embodiment.

  In the configuration of the present embodiment shown in FIG. 1, an inclination detector 305e (also referred to as a change detector) detects the amount of change in the feedback voltage Vfb with respect to the pulse width limiter 305 in the power supply IC 103 of the switching power source described in FIG. And an AND circuit 305f. Hereinafter, the operation of the internal circuit of the inclination detector 305e and the AND circuit 305f will be described with reference to FIG.

  As shown in FIG. 2, the inclination detecting unit 305e includes a differentiating circuit 305g, a comparator 305h, a power supply IC Vcc, a resistor 305i, and a resistor 306j. The input of the differentiation circuit 305g is connected to the feedback voltage Vfb, and the output is connected to the inverting input terminal of the comparator 305h. On the other hand, a voltage obtained by dividing the power supply Vcc of the power supply IC by the resistors 305i and 305j is input to the non-inverting input terminal of the comparator 305h as the reference voltage Vth. The comparator 305h outputs an L level to the AND circuit 305f when the output of the differentiating circuit 305g becomes high as a result of comparing the output result of the differentiating circuit 305g and the reference voltage Vth. That is, the slope of Vfb is detected, and when the slope is equal to or greater than a predetermined slope (threshold) (= when the load fluctuation is large), the L level is output to the AND circuit 305f. The inclination detection unit 305e outputs an H level when Vfb is less than a predetermined inclination (threshold) (= when the load fluctuation is small). The AND circuit 305f outputs the H level only when both the output of the pulse width restriction determination unit 305a and the output of the inclination detection unit 305e are at the H level. That is, when the inclination detection unit 305e is at the L level (when the load fluctuation is large), the AND circuit 305f outputs the L level to the mask signal generation unit 305b to release the pulse width restriction.

  Next, an operation when the load is suddenly changed from a medium load to a heavy load, which is a feature of the present embodiment, will be described with reference to FIG. The continuous switching operation of the heavy load and the pulse width limiting operation during the burst operation at the middle load and the light load in the present embodiment are the same as those described above, and thus the description thereof is omitted.

  From t400 to t410 in FIG. 3, the change amount of the feedback voltage Vfb is smaller than the predetermined gradient (= the load fluctuation is small), so the gradient detector 305e which is the configuration of this embodiment remains at the H level. Therefore, whether to operate in a state where the pulse width is limited is determined according to the output state of the pulse width limit determination unit 305a. Here, since the pulse width is limited, the pulse width limitation determination unit 305a is at H level and the AND circuit 305f is also at H level as shown in FIG. When the load current increases rapidly at time t411, Vfb rises because sufficient power cannot be supplied for the necessary power consumption on the secondary side (period t412). At this time, the value of the output voltage of the differentiating circuit 305g in the figure also rises, and when the reference voltage Vth is exceeded, the slope detecting unit 305e outputs an L level to the AND circuit 305f (timing t413). On the other hand, since Vfb is between the reference voltage 304 and the reference voltage 306, the pulse width restriction determination unit 305a holds the previous state, and at this time, outputs H level. Therefore, the AND circuit 305f outputs the L level to the mask signal generation unit 305b to release the pulse width restriction (t413). As a result, the power supply IC 103 operates to turn on the FET 105 when Vis is slightly larger than Vfb (t413 and thereafter), as in the prior art, and can sufficiently supply power.

  As described above, by detecting the slope of Vfb, even if a sudden increase in the load current occurs, the pulse width restriction is released at a timing earlier than the time point t311 in FIG. 13 so that power can be supplied. Therefore, it is possible to reduce the decrease in output voltage.

  In the present embodiment, the configuration using the differentiation circuit for detecting the slope of the feedback voltage Vfb has been described. However, this is only an example, and the circuit for detecting the change in Vfb is a circuit other than the differentiation circuit or other means. It may be.

(Example 2)
In the configuration of the first embodiment (FIG. 1), the slope of the feedback voltage Vfb is detected, and when the load suddenly increases, the output of the output voltage is reduced by releasing the pulse width restriction at a timing earlier than that of the conventional power supply. It has been explained that can be reduced. By the way, in the switching power supply of FIG. 1, when noise enters the FB terminal due to noise from the surroundings, noise from the commercial power supply, or the like, the output pulse may be disturbed. Therefore, there is a case where the capacitor 110 is connected to the FB terminal of the power supply IC 103 illustrated in FIG. Here, when the capacitance of the noise countermeasure capacitor 110 is large, the slope of the feedback voltage Vfb is reduced when the load is suddenly increased. Therefore, there is a problem that the pulse limitation cannot be released in the configuration of the first embodiment. To do.

  The present embodiment is characterized by providing a power supply that can cope with a sudden increase in load even when such a noise countermeasure capacitor is used. FIG. 4 shows a switching power supply according to the second embodiment. The same components as those of the switching power supply described with reference to FIGS. 1, 9, and 12 described above are denoted by the same reference numerals and description thereof is omitted. FIG. 5 shows a detailed diagram of the internal circuit of the pulse width limiting unit 305 in the power supply IC 103 of the second embodiment. Further, FIG. 6 shows operation waveforms representing the characteristics of the switching power supply according to the second embodiment.

  In the configuration of FIG. 4, a noise countermeasure capacitor 110 is connected to the FB terminal. Further, the power supply IC 301 is newly provided with a TH terminal, and the pull-down resistor 305j for generating the reference voltage Vth inside the inclination detection unit 305e of FIG. 2 described in the first embodiment is arranged outside the power supply IC 103 via the TH terminal. Different from Example 1 (FIG. 1). That is, the present embodiment is characterized in that the reference voltage Vth can be made variable by disposing the pull-down resistor 305j for generating the reference voltage Vth outside the power supply IC 103.

  Next, the operation of this embodiment will be described with reference to FIG. Note that description of parts similar to those in the first embodiment is omitted. 6 differs from the first embodiment in the degree of voltage increase when the load increases at the timing of t511 in the FB terminal voltage in the drawing. By adding the capacitor 110, the amount of increase in the feedback voltage Vfb becomes smaller than that in the first embodiment (indicated by a broken line). Further, since the degree of increase of the feedback voltage Vfb changes, the output result of the differentiating circuit is also smaller than that of the first embodiment (shown by a broken line) as shown by the output voltage of the differentiating circuit 305g in the figure. Therefore, in this embodiment, the resistor 305j is changed so as to be the reference voltage Vth2 (a value smaller than Vth of Embodiment 1) of the comparator 305h in the inclination detector 305e. Then, the constant is adjusted so that the pulse width restriction is released at the same timing t513 as in the first embodiment.

  As described above, even in the configuration in which the noise suppression capacitor 110 is connected to the FB terminal of the power supply IC 103, when the slope of Vfb changes (when it decreases) when the load suddenly increases, the reference voltage Change Vth to a smaller value. As a result, the pulse width restriction can be released at the same timing as in the first embodiment.

Example 3
FIG. 7 shows a switching power supply according to the third embodiment. The same components as those of the switching power supply described with reference to FIGS. 1, 9, and 12 described above are denoted by the same reference numerals and description thereof is omitted. FIG. 8 shows operation waveforms representing the characteristics of the switching power supply according to the third embodiment.

7 is different from the switching power supply described in FIG. 12 in that another reference voltage 311 is added and the feedback voltage Vfb and the reference voltage 311 are connected to the mask signal generation unit 305b. In addition, each reference voltage in a present Example becomes the relationship of the following formula | equation (9).
Reference voltage 306> reference voltage 311> reference voltage 304 (9)

Next, the operation of the mask signal generation unit 305b in the present embodiment will be described. In the switching power supply of FIG. 12, the limit value of the pulse width in the mask signal generation unit 305b is a constant value regardless of the feedback voltage Vfb. On the other hand, the mask signal generation unit 305b in this embodiment switches to two limit values according to the input feedback voltage Vfb. Specifically, Vfb and reference voltage 311 are compared. When Vfb is smaller than the other reference voltage, that is, when Vfb <reference voltage 311, the limit value of the pulse width is set to Plmt1 (first limit value). When Vfb is equal to or higher than another reference voltage, that is, when Vfb ≧ reference voltage 311, the limit value of the pulse width is set to Plmt2 (second limit value). Plim1 and Plim2, which are the limit values of the pulse width, have the relationship of the following formula (10).
Plim1> Plim2 (10)

  The characteristic operation of this embodiment will be described below with reference to FIG. From t600 to t610 in FIG. 8, the burst operation is performed with the pulse width limited. When the load current increases at time t611, Vfb rises because sufficient power cannot be supplied with respect to the required power consumption on the secondary side (period t612). When the feedback voltage Vfb becomes equal to or higher than the reference voltage 311 at time t613, the mask signal generation unit 305b changes the limit value of the pulse width from Plim1 to Plim2. Therefore, the switching power supply can supply power more in the period 614 than in the period 612, and the decrease in output voltage in the period 614 can be reduced.

  When Vfb further rises and exceeds the reference voltage 306, the pulse width restriction determination unit 305a outputs the L level and releases the pulse width restriction (t615). As a result, the power supply IC 103 operates to turn on the FET 105 when Vis becomes slightly larger than Vfb (t615 and thereafter), as in the conventional technique, and can supply more power than the period 614. When the load current decreases after the feedback voltage Vfb reaches the reference voltage 311 and before it reaches the reference voltage 306 and falls below the reference voltage 311 again, the mask signal generation unit 305b sets the limit value of the pulse width to Plim2 To Plim1.

  As described above, by changing the limit value of the pulse width according to Vfb, it is possible to reduce the decrease in the output voltage even when the load increases rapidly.

(Application example of power supply)
The switching power supply described in the first, second, and third embodiments can be applied as, for example, a low-voltage power supply for an image forming apparatus, that is, a power supply that supplies power to a drive unit such as a controller (control unit) or a motor. The configuration of the image forming apparatus to which the switching power supply according to the first, second, and third embodiments is applied will be described below.

[Configuration of Image Forming Apparatus]
A laser beam printer will be described as an example of the image forming apparatus. FIG. 14 shows a schematic configuration of a laser beam printer which is an example of an electrophotographic printer. The laser beam printer 500 includes a photosensitive drum 511 as an image carrier on which an electrostatic latent image is formed, a charging unit 517 (charging unit) that uniformly charges the photosensitive drum 511, and an electrostatic latent image formed on the photosensitive drum 511. A developing unit 512 (developing unit) that develops an image with toner is provided. The toner image developed on the photosensitive drum 511 is transferred to a sheet (not shown) as a recording material supplied from the cassette 516 by a transfer unit 518 (transfer unit), and the toner image transferred to the sheet is transferred to the fixing unit 514. Then, the toner is fixed and discharged onto the tray 515. The photosensitive drum 511, the charging unit 517, the developing unit 512, and the transfer unit 518 are image forming units. The laser beam printer 500 includes the power supply device 550 described in the first and second embodiments. Note that the image forming apparatus to which the power supply device 550 of the first and second embodiments can be applied is not limited to that illustrated in FIG. 4, and may be an image forming apparatus including a plurality of image forming units, for example. Further, the image forming apparatus may include a primary transfer unit that transfers a toner image on the photosensitive drum 511 to an intermediate transfer belt and a secondary transfer unit that transfers the toner image on the intermediate transfer belt to a sheet.

  The laser beam printer 500 includes a controller 520 that controls an image forming operation by the image forming unit and a sheet conveying operation. The power supply device 550 described in the first and second embodiments supplies power to the controller 520, for example. . Further, the power supply device 550 described in the first and second embodiments supplies power to a driving unit such as a motor for rotating the photosensitive drum 511 or driving various rollers for conveying the sheet.

10 Commercial power supply Vac
11 Bridge diode 101 Primary smoothing capacitor 102 Starting resistor 103 Power supply IC
104 Isolation transformer 105 Switching FET
106, 107, 108, 112, 114, 123, 124, 125, 128, 308 Resistive element 109 Photocoupler 113, 122, 126 Capacitor 111, 121 Diode 127 Shunt regulator

Claims (10)

A transformer having a primary winding on the primary side, the primary side and the secondary side being insulated;
A switching element connected to the primary winding;
Detecting means for detecting a signal corresponding to a current flowing through the primary side of the transformer;
Feedback means for feeding back a signal corresponding to a voltage output from the secondary winding on the secondary side to the primary side;
A change amount detecting means for detecting a change amount of the signal of the feedback means;
A time determination unit that compares a signal from the feedback means with a reference value and limits the on-time of the switching element according to the comparison result;
The switching power supply, wherein the time determining unit releases the restriction on the on-time of the switching element when the amount of change detected by the amount-of-change detecting means is a predetermined value or more. The time determination unit determines an ON time of the switching element based on a comparison result between the signal detected by the detection unit and the signal from the feedback unit,
If the signal from the feedback means is between a first reference voltage and a second reference voltage greater than the first reference voltage, the on-time of the switching element is limited,
2. The switching power supply according to claim 1, wherein when the signal from the feedback means exceeds the second reference voltage, the restriction on the ON time of the switching element is released.   The switching power supply according to claim 1, wherein the change amount detection means is a differentiation circuit.   4. The change amount detecting means determines whether or not a signal from the feedback means is a predetermined change amount based on a comparison result between an output voltage from the differentiation circuit and a third reference voltage. Switching power supply described in   5. The switching power supply according to claim 4, wherein the value of the third reference voltage is set from the outside.   6. The switching power supply according to claim 4, further comprising means for switching the value of the third reference voltage.   The time determination unit compares a signal from the feedback unit with another reference voltage between the first reference voltage and the second reference voltage, and the signal from the feedback unit is compared with the other reference voltage. When the switching element is small, the on-time of the switching element is set to a first limit value. When the signal from the feedback means is equal to or higher than the other reference voltage, the on-time of the switching element is smaller than the first limit value. The switching power supply according to any one of claims 2 to 6, wherein the second limit value is set. In an image forming apparatus for forming an image on a recording material,
Image forming means;
A switching power supply for supplying power to the image forming apparatus,
The switching power supply is
A transformer having a primary winding on the primary side, the primary side and the secondary side being insulated;
A switching element connected to the primary winding;
Detecting means for detecting a signal corresponding to a current flowing through the primary side of the transformer;
Feedback means for feeding back a signal corresponding to a voltage output from the secondary winding on the secondary side to the primary side;
A change amount detecting means for detecting a change amount of the signal of the feedback means;
A time determination unit that compares a signal from the feedback means with a reference value and limits the on-time of the switching element according to the comparison result;
The image forming apparatus according to claim 1, wherein the time determining unit releases the restriction on the on-time of the switching element when the amount of change detected by the change amount detecting unit is equal to or greater than a predetermined value. A controller for controlling the operation of the image forming means;
The image forming apparatus according to claim 8, wherein the switching power supply supplies power to the controller. Drive means for driving the image forming means;
The image forming apparatus according to claim 8, wherein the switching power supply supplies power to the driving unit.

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