JP2016082182A - Semiconductor device and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce parasitic capacitance occurring between an interconnection in a crosswise direction and an interconnection in a lengthwise direction in a semiconductor device in which refinement progresses.SOLUTION: A semiconductor device 1 comprises: a bit line BL formed to extend along a top face of an interlayer insulation film 12; a capacitive contact plug CC formed to extend in a direction crossing the top face of the interlayer insulation film 12; and an insulation film arranged to separate the bit line BL and the capacitive contact plug CC. The insulation film includes a side wall insulation film 21 which has a relatively small relative permittivity and covers a lateral face of the bit line BL, and a liner insulation film 22 which has a relatively large relative permittivity and covers the lateral face of the bit line BL via the side wall insulation film 21.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device including a vertical transistor.

  In a semiconductor device such as a DRAM (Dynamic Randam Access Memory), a vertical wiring may be arranged between two wirings extending in the horizontal direction and arranged in parallel. For example, a contact plug that connects an impurity diffusion layer embedded in the surface of the semiconductor substrate and a memory element formed above the bit line between two bit lines formed on the surface of the semiconductor substrate For example.

  In the above case, the vertical wiring is previously formed by providing a contact hole in the interlayer insulating film in a state where the horizontal wiring is covered with the interlayer insulating film made of a silicon oxide film and embedding the conductive film therein. Was formed. However, this method makes it difficult to avoid contact between the vertical wirings and the horizontal wirings as the distance between the horizontal wirings approaches as the miniaturization of semiconductor devices in recent years progresses. I came. Therefore, before forming the interlayer insulating film, the top and side surfaces of the lateral wiring are covered with a silicon nitride film, and etching with a sufficiently large selection ratio of the silicon oxide film to the silicon nitride film is performed as the etching for providing the contact hole. The method of using (SAC (Self Alignment Contact) method) has come to be used. According to this method, even after the contact hole is formed, the state in which the upper surface and the side surface of the lateral wiring are covered with the silicon nitride film can be maintained, so that the contact between the vertical wiring and the lateral wiring is prevented. It becomes possible to do.

  Patent Document 1 and Patent Document 2 disclose an example of a DRAM in which a silicon nitride film is disposed on the upper and side surfaces of a bit line.

JP 2012-84738 A JP 2012-99793 A

  However, the SAC method described above has a problem that a large parasitic capacitance is generated between the horizontal wiring and the vertical wiring. That is, in the semiconductor device formed by the SAC method, the horizontal wiring and the vertical wiring are separated only by the silicon nitride film, but the silicon nitride film has a dielectric constant compared to the silicon oxide film. It has the property that the rate is large. Specifically, the relative dielectric constant of the silicon oxide film is about 3.9, whereas the relative dielectric constant of the silicon nitride film reaches about twice that of 7.5. Since the size of the parasitic capacitance is proportional to the relative permittivity of the dielectric disposed between the interconnects, the silicon nitride film having a large relative permittivity is interposed between the lateral interconnects and the longitudinal interconnects. As a result, the parasitic capacitance generated in the circuit increases.

  A large parasitic capacitance generated between the horizontal wiring and the vertical wiring causes various problems. For example, in the case of the above-described DRAM bit line and contact plug, the ratio (Cs / Cb) between the capacitor capacitance Cs and the parasitic capacitance Cb of the bit line becomes small, and the sense margin of the DRAM decreases. Cause. Therefore, there is a need for a technique capable of reducing the parasitic capacitance generated between the horizontal wiring and the vertical wiring in a semiconductor device that has been miniaturized.

  A semiconductor device according to an aspect of the present invention is formed so as to extend in a direction intersecting the first plane and a first wiring formed so as to extend along the first plane. A second wiring; and an insulating film disposed so as to separate the first wiring from the second wiring, the insulating film having a relatively small relative dielectric constant, and the first wiring A first insulating film that covers the side surface of the first wiring; a second insulating film that has a relatively large relative dielectric constant and covers the side surface of the first wiring through the first insulating film; It is characterized by including.

  A semiconductor device according to another aspect of the present invention includes a plurality of first wirings extending along a first plane parallel to the main surface of the semiconductor substrate and formed in parallel to each other, A mask film that covers the upper surface of each of the first wirings, and a second film that extends in a direction crossing the first plane and passes between the two adjacent first wirings. And an insulating film disposed so as to separate the first wiring and the second wiring, the insulating film having a relatively small relative dielectric constant, and the first film A first insulating film that covers a side surface of the wiring, and a second insulating film that has a relatively large relative dielectric constant and covers the side surface of the first wiring through the first insulating film. The first insulating film is formed such that an upper end thereof is located at a position lower than an upper surface of the mask film. To.

  According to still another aspect of the present invention, there is provided a semiconductor device for element isolation, which is embedded in a main surface of a semiconductor substrate, thereby dividing a plurality of active regions arranged in a first direction parallel to the main surface into the main surface. Each of the insulating film and the plurality of active regions is divided into first to third active regions in order from one end side in a second direction parallel to the main surface and perpendicular to the first direction, respectively. The two fourth wirings extending in the first direction and the second active region extending in the first direction corresponding to each of the plurality of active regions and corresponding on the lower surface A plurality of first wirings that are electrically connected to each other and two adjacent first wirings corresponding to each of the plurality of active regions are orthogonal to the first and second directions. 3 extending in the direction of 3 and electrically contacting the corresponding first active region at the bottom. A plurality of second wirings extending in the third direction between the two adjacent first wirings corresponding to each of the plurality of active regions and corresponding on the lower surface. A plurality of third wirings electrically connected to the three active regions, and an insulating film disposed so as to separate the plurality of first wirings from the plurality of second and third wirings, The insulating film has a relatively small relative dielectric constant, has a relatively large relative dielectric constant, and a first insulating film that covers a side surface of each of the plurality of first wirings. And a second insulating film covering a side surface of each of the plurality of first wirings via one insulating film.

  According to one aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: forming a first wiring having an upper surface covered with a mask film; and forming a first insulating film having a relatively low relative dielectric constant. Etching back a step of covering a part of the side surface of the mask film and the side surface of the first wiring with the first insulating film, and a relatively large ratio after forming the first insulating film A step of covering the exposed surface of the first insulating film with the second insulating film by depositing and etching back a second insulating film having a dielectric constant, the first wiring, and the first wiring Forming an interlayer insulating film with a thickness that fills a region between the wiring structures including the second insulating film and planarizing the upper surface of the interlayer insulating film until the upper surface of the wiring structure is exposed Providing a first through hole in the interlayer insulating film, and in the first through hole By embedding a conductive film, characterized by comprising a step of forming a second wiring which is separated from the first wire by the first and second insulating films.

  According to the present invention, the second insulating film having a relatively large relative dielectric constant plays a role of protecting the first insulating film from etching for forming the second wiring. A first insulating film having a relatively small relative dielectric constant can be interposed between the second wirings. Therefore, in a semiconductor device that has been miniaturized, it is possible to reduce the parasitic capacitance generated between the horizontal wiring and the vertical wiring.

(A) is a figure which shows the planar positional relationship of the structure with which the semiconductor device 1 by preferable 1st Embodiment of this invention is provided, (b) is the AA line shown to (a). It is a vertical sectional view of the corresponding semiconductor device 1, and (c) is a vertical sectional view of the semiconductor device 1 corresponding to the BB line shown in (a). It is an enlarged view of the area | region C shown in FIG.1 (b). (A) is a top view in the manufacturing process of the semiconductor device 1 shown in FIG. 1, (b) is a vertical sectional view of the semiconductor device 1 corresponding to the AA line shown in (a), (C) is a vertical sectional view of the semiconductor device 1 corresponding to the line BB shown in (a). (A) is a top view in the manufacturing process (process following FIG. 3) of the semiconductor device 1 shown in FIG. 1, (b) is the semiconductor device 1 corresponding to the AA line shown in (a). (C) is a vertical sectional view of the semiconductor device 1 corresponding to the line BB shown in (a). (A) is a top view in the manufacturing process (process following FIG. 4) of the semiconductor device 1 shown in FIG. 1, (b) is the semiconductor device 1 corresponding to the AA line shown in (a). (C) is a vertical sectional view of the semiconductor device 1 corresponding to the line BB shown in (a). (A) is a top view in the manufacturing process (process following FIG. 5) of the semiconductor device 1 shown in FIG. 1, (b) is the semiconductor device 1 corresponding to the AA line shown in (a). (C) is a vertical sectional view of the semiconductor device 1 corresponding to the line BB shown in (a). (A) is a top view in the manufacturing process (process following FIG. 6) of the semiconductor device 1 shown in FIG. 1, (b) is the semiconductor device 1 corresponding to the AA line shown in (a). (C) is a vertical sectional view of the semiconductor device 1 corresponding to the line BB shown in (a). (A) is a top view in the manufacturing process (process following FIG. 7) of the semiconductor device 1 shown in FIG. 1, (b) is the semiconductor device 1 corresponding to the AA line shown in (a). (C) is a vertical sectional view of the semiconductor device 1 corresponding to the line BB shown in (a). (A) is a top view in the manufacturing process (process following FIG. 8) of the semiconductor device 1 shown in FIG. 1, (b) is the semiconductor device 1 corresponding to the AA line shown in (a). (C) is a vertical sectional view of the semiconductor device 1 corresponding to the line BB shown in (a). (A) is a top view in the manufacturing process (process following FIG. 9) of the semiconductor device 1 shown in FIG. 1, (b) is the semiconductor device 1 corresponding to the AA line shown in (a). (C) is a vertical sectional view of the semiconductor device 1 corresponding to the line BB shown in (a). (A) is a top view in the manufacturing process (process following FIG. 10) of the semiconductor device 1 shown in FIG. 1, (b) is the semiconductor device 1 corresponding to the AA line shown in (a). (C) is a vertical sectional view of the semiconductor device 1 corresponding to the line BB shown in (a). (A) is a top view in the manufacturing process (process following FIG. 11) of the semiconductor device 1 shown in FIG. 1, (b) is the semiconductor device 1 corresponding to the AA line shown in (a). (C) is a vertical sectional view of the semiconductor device 1 corresponding to the line BB shown in (a). (A) is a top view in the manufacturing process (process following FIG. 12) of the semiconductor device 1 shown in FIG. 1, (b) is the semiconductor device 1 corresponding to the AA line shown in (a). (C) is a vertical sectional view of the semiconductor device 1 corresponding to the line BB shown in (a). (A) is a top view in the manufacturing process (process following FIG. 13) of the semiconductor device 1 shown in FIG. 1, (b) is the semiconductor device 1 corresponding to the AA line shown in (a). (C) is a vertical sectional view of the semiconductor device 1 corresponding to the line BB shown in (a). (A) is a top view in the manufacturing process (process following FIG. 14) of the semiconductor device 1 shown in FIG. 1, (b) is the semiconductor device 1 corresponding to the AA line shown in (a). (C) is a vertical sectional view of the semiconductor device 1 corresponding to the line BB shown in (a). (A) is a top view in the manufacturing process (process following FIG. 15) of the semiconductor device 1 shown in FIG. 1, (b) is the semiconductor device 1 corresponding to the AA line shown in (a). (C) is a vertical sectional view of the semiconductor device 1 corresponding to the line BB shown in (a). (A) is a top view in the manufacturing process (process following FIG. 16) of the semiconductor device 1 shown in FIG. 1, and (b) is the semiconductor device 1 corresponding to the AA line shown in (a). (C) is a vertical sectional view of the semiconductor device 1 corresponding to the line BB shown in (a). (A) is a top view in the manufacturing process (process following FIG. 17) of the semiconductor device 1 shown in FIG. 1, (b) is the semiconductor device 1 corresponding to the AA line shown in (a). (C) is a vertical sectional view of the semiconductor device 1 corresponding to the line BB shown in (a). (A) is a top view in the manufacturing process (process following FIG. 18) of the semiconductor device 1 shown in FIG. 1, (b) is the semiconductor device 1 corresponding to the AA line shown in (a). (C) is a vertical sectional view of the semiconductor device 1 corresponding to the line BB shown in (a). FIGS. 15A and 15B are vertical cross-sectional views in a manufacturing process of a semiconductor device according to a comparative example of the present invention, where FIG. 15A is FIG. 15B, FIG. 16B is FIG. 16B, and FIG. , (D) correspond to FIG. 18 (b), respectively. (A) is a figure which shows the planar positional relationship of the structure with which the semiconductor device 1 by preferable 2nd Embodiment of this invention is provided, (b) is the AA line shown to (a). It is a vertical sectional view of the corresponding semiconductor device 1, and (c) is a vertical sectional view of the semiconductor device 1 corresponding to the BB line shown in (a).

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In this embodiment, an example in which the present invention is applied to a semiconductor device that is a DRAM (Dynamic Random Access Memory) will be described. In the following description, it is assumed that the feature size defined by the resolution limit of lithography, that is, the F value is 40 nm. However, the present invention can also be applied to a semiconductor device other than a DRAM or when the F value is not 40 nm.

  The semiconductor device 1 according to the first embodiment of the present invention includes a semiconductor substrate 2 as shown in FIG. A p-type single crystal silicon substrate is preferably used as the semiconductor substrate 2, but other types of substrates may be used. The main surface of the semiconductor substrate 2 is provided with a cell array portion in which a large number of memory cells are formed and a peripheral circuit portion in which various circuits for performing various controls such as reading and writing are arranged on the cell array portion. . FIG. 1 shows a part of the cell array portion.

  In the region corresponding to the cell array portion in the main surface of the semiconductor substrate 2, as shown in FIG. 1, a plurality of active regions K each having a parallelogram planar shape are arranged in a matrix. These active regions K are defined by element isolation insulating films 5 that form element isolation regions by a so-called STI (Shallow Trench Isolation) method, and each of them is independent in an island shape. The element isolation insulating film 5 is composed of a silicon oxide film embedded in the main surface of the semiconductor substrate 2.

  The width in the y direction of each active region K is the F value (40 nm) described above, and the arrangement pitch in the y direction is twice the F value (80 nm). The width in the x direction of each active region K is 5 times (200 nm) the F value, and the arrangement pitch in the x direction is 6 times the F value (240 nm). The active regions K are arranged at equal intervals along the x direction (second direction) and the y direction (first direction) orthogonal to each other within the main surface of the semiconductor substrate 2. Further, the short side whose length is equal to the F value is arranged in parallel with the y direction. Here, the z direction shown in FIGS. 1B and 1C is a direction (third direction) orthogonal to both the x direction and the y direction, and the v direction shown in FIGS. 1A and 1C is 1 is an extending direction of the line BB shown in FIG.

In each active region K, as shown in FIG. 1 (c), two cell transistors Tr _A and Tr _B (first and second cell transistors), which are n-channel MOS transistors, and 2 capacitors, respectively. Two storage elements SN _A and SN _B (first and second storage elements) are formed. In this specification, a symbol “A” or “B” may be attached to the lower right of the code like the storage elements SN _A and SN _B. This is because the configuration indicated by the code is a cell. It shows which of the transistors Tr _A and Tr _B corresponds to.

A plurality of word lines WL (fourth wirings) extending in the y direction are embedded in the main surface of the semiconductor substrate 2 via the gate insulating film 10. Width _{X WL} in the x direction of each word line WL is above F value (40 nm). A buried insulating film 13 made of, for example, a silicon nitride film is disposed on the upper surface of each word line WL. The buried insulating film 13 plays a role of ensuring insulation between each word line WL and various conductors arranged on the surface of the semiconductor substrate 2 such as a bit line BL and a capacitor contact plug CC described later.

The arrangement of the word lines WL in the x direction is determined so that the two word lines WL _A and WL _B pass through a series of active regions K arranged in the y direction. Also, the two word lines WL _A and WL _B corresponding to one active region K are arranged from the central axis in the x direction of the corresponding active region K at the arrangement pitch P _WL equal to twice the F value (80 nm). They are arranged at positions that are line symmetric when viewed. Accordingly, each active region K is equally divided into three regions in the x direction by the corresponding two word lines WL _A and WL _B. In FIG. 1C, each region in the active region K obtained by this division is expressed as active regions K1 to K3 in order from one end side in the x direction.

The word lines WL _A and WL _B constitute the control electrodes of the cell transistors Tr _A and Tr _B , respectively. Impurity diffusion layers 8 _A , 7 and 8 _B are formed on the surface of the semiconductor substrate 2 located in the active regions K1 to K3, respectively. The impurity diffusion layers 8 _A , 7, 8 _B are all n-type impurity diffusion layers formed by ion-implanting n-type impurities such as phosphorus into the semiconductor substrate 2. The impurity diffusion layer 7 (first impurity diffusion layer) constitutes one controlled electrode common to the cell transistors Tr _A and Tr _B , and the impurity diffusion layers 8 _A and 8 _B (second impurity diffusion layers) are respectively The other controlled electrode of the cell transistors Tr _A and Tr _B is configured. With this configuration, the channel of the cell transistor Tr _A is formed in a region of the semiconductor substrate 2 around the word line WL _A , and the channel of the cell transistor Tr _B is around the word line WL _B of the semiconductor substrate 2 Formed in the region located at

  On the surface of the semiconductor substrate 2, an interlayer insulating film 12, which is a silicon oxide film, for example, is disposed. The upper surface of the interlayer insulating film 12 constitutes the same plane as the upper surface of the buried insulating film 13 described above.

On the upper surface (first plane) of the interlayer insulating film 12, a plurality of bit lines BL (first wirings) each extending in the x direction are arranged. Each bit line BL is composed of a metal laminated film including a metal silicide film, a metal nitride film in contact with the upper surface of the metal silicide film, and a metal film in contact with the upper surface of the metal nitride film. A mask film 20 made of, for example, a silicon nitride film is disposed on the upper surface of each bit line BL. The side surface of the mask film 20 and the side surface of the bit line BL constitute the same plane. Width _{Y BL} in the y direction of each bit line BL is F value (40 nm) is less than 26 nm. The height _{Z BL} of the bit line BL shown in FIG. 2 is a 30 nm, the height _{Z 20} of the mask film 20 is 120 nm. Therefore, the distance (Z _BL + Z ₂₀ ) from the lower surface of the bit line BL to the upper surface of the mask film 20 is 150 nm.

The arrangement of each bit line BL in the y direction is determined so that one bit line BL passes above the active region K2 of each of the series of active regions K arranged in the x direction. Accordingly, the arrangement pitch _{P BL} of the y direction of the bit line BL shown in FIG. 1 is twice the same F values as the y-direction of the arrangement pitch of the active region K (80 nm). Each bit line BL is connected to the impurity diffusion layer 7 formed in each corresponding active region K2 by a bit line contact plug BLC penetrating the interlayer insulating film 12. The bit line contact plug BLC is composed of an n-type impurity-containing silicon film. Here, in the present embodiment, each bit line BL is assumed to be linear. However, the bit line BL does not necessarily have to be linear, and passes above the active region K2 of each of the series of active regions K arranged in the x direction. As long as it extends in the x direction as a whole.

At both ends in the y direction of each bit line BL, a sidewall insulating film 21 (first insulating film) made of, for example, a silicon oxide film (SiO ₂ ) and a liner insulating film 22 made of, for example, a silicon nitride film (SiN). (Second insulating film) is disposed. The sidewall insulating film 21 and the liner insulating film 22 together with the bit line BL and the mask film 20 constitute a bit line structure BLS (wiring structure) shown in FIG. Hereinafter, the internal structure of the bit line structure BLS will be described in detail with reference to FIG.

The sidewall insulating film 21 has a sidewall-like shape formed by forming a bit line BL and a mask film 20, forming a 5 nm thick silicon oxide film by an ALD (Atomic Layer Deposition) method, and etching back. It is an insulating film. Accordingly, the film thickness Y ₂₁ (film thickness in the y direction) of the sidewall insulating film 21 is 5 nm. The etch back is performed so that the height Z21 from the upper surface of the interlayer insulating film 12 to the upper end 21a of the sidewall insulating film ₂₁ is 130 nm. As described above, since the distance (Z _BL + Z ₂₀ ) from the lower surface of the bit line BL to the upper surface of the mask film 20 is 150 nm, as a result of etch back, the distance Z1 from the upper end of the side surface in the y direction of the mask film 20 is obtained. = 20 nm is not covered by the sidewall insulating film 21.

  On the other hand, the liner insulating film 22 is obtained by forming a sidewall insulating film 21 and then depositing a silicon nitride film with a thickness larger than the thickness of the sidewall insulating film 21 by ALD. It is a sidewall-like insulating film. In the present embodiment, the film thickness when the liner insulating film 22 is formed is 10 nm. Since the etch-back like the sidewall insulating film 21 is not performed, the liner insulating film 22 remains on the upper surface of the mask film 20 and the upper surface of the interlayer insulating film 12 as shown in FIG. In FIGS. 1B, 1C, and 2, the liner insulating film 22 remaining on the upper surface of the mask film 20 is the liner insulating film 22b, and the liner insulating film 22 remaining on the upper surface of the interlayer insulating film 12 is the liner insulating film 22c. The other liner insulating film 22 is referred to as a liner insulating film 22a.

Thickness _{Z 22b} of the liner insulating film 22b is a film 10nm equal to the thickness at the time of film formation (the liner insulating film 22c is similar). Therefore, the distance Z2 (= Z1 + Z _22b ) from the upper surface of the liner insulating film 22b to the sidewall insulating film 21 is 30 nm. Here, in the present embodiment, the distance Z1, that is, the etch back amount of the sidewall insulating film 21, is set so that the value of the distance Z2 is three times the film thickness (10 nm) when the liner insulating film 22 is formed. Has been decided. More specifically, the distance Z1 is such that the value of the distance Z2 is 3 to 8 times the film thickness when the liner insulating film 22 is formed (= distance Z1 is twice the film thickness when the liner insulating film 22 is formed). ˜7 times). This is because if the value of the distance Z2 is smaller than three times the film thickness when the liner insulating film 22 is formed, the side wall insulating film 21 may be extinguished by etching when forming the contact hole H4. This is because it is difficult to control the position of the upper end 21a of the sidewall insulating film 21 when the value of the distance Z2 is smaller than eight times the film thickness when the liner insulating film 22 is formed. From the viewpoint of controlling the position of the upper end 21a of the sidewall insulating film 21 with higher accuracy, the value of the distance Z2 is 3 to 5 times the film thickness when the liner insulating film 22 is formed (= the distance Z1 is the liner). It is more preferable to determine the distance Z1 so as to be 2 to 4 times the film thickness when the insulating film 22 is formed.

  The liner insulating film 22a remains on the side surfaces of the bit line BL and the mask film 20 with a constant film thickness of 10 nm in a portion where a contact hole H4 described later is not formed. However, the portion where the contact hole H4 is formed has a complicated shape as shown in FIG. 2 because there is a portion that is removed by etching for forming the contact hole H4. Hereinafter, the shape of the liner insulating film 22a in the portion where the contact hole H4 is formed will be described in detail with reference to FIG.

  As shown in FIG. 2, the liner insulating film 22a in the portion where the contact hole H4 is formed is constituted by six partial liner insulating films 22aa to 22af.

The partial liner insulating film 22aa is the uppermost part of the liner insulating film 22a and is connected to the liner insulating film 22b. The upper surface of the partial liner insulating film 22aa is inclined with respect to the side surface of the mask film 20. This is because the inclination formed at the time of film formation remains. Further, the maximum film thickness Y 22aa in the y direction of the partial liner insulating film 22aa is smaller than 10 nm at the time of film formation, which is because it was _removed by etching at the time of forming the contact hole H4. Width _{Y BL} and the arrangement pitch _{P BL} of the y direction of the bit line BL, and as well as the use of y-direction width _{Y H4} of the contact hole H4, a thickness _{Y 22aa} is equal to _{(P BL -Y BL -Y H4)} / 2 Value. Since Y _BL and P _BL are 26 nm and 80 nm, respectively, and the width Y _H4 is 40 nm as described later, the film thickness Y _22aa is 7 nm from the above formula. If the width Y _H4 is set to a larger value, the partial liner insulating film 22aa is completely removed and the film thickness Y _22aa becomes zero.

The partial liner insulating film 22ab is a portion connected to the lower end of the partial liner insulating film 22aa, and directly covers the mask film 20 without using the sidewall insulating film 21. The film thickness of the partial liner insulating film _22ab is equal to the maximum film thickness Y _22aa of the partial liner insulating film 22aa by etching when the contact hole H4 is formed. The side surface of the partial liner insulating film 22ab is parallel to the side surface of the mask film 20. Therefore, the width in the y-direction Y3 portion liner insulating film 22ab bit line structure BLS in the portion of the (portion shown by FIG. 2 BLSA) is twice the thickness _{Y 22aa} to the width _{Y BL} in the y direction of the bit lines BL It is a value obtained by adding.

  The partial liner insulating film 22ac is a portion connected to the lower end of the partial liner insulating film 22ab. The upper surface of the partial liner insulating film 22ac is formed by lowering the upper surface of the partial liner insulating film 22aa by etching when forming the contact hole H4, and is inclined with respect to the side surface of the mask film 20 like the partial liner insulating film 22aa. doing. The upper end of the partial liner insulating film 22ac is located above the upper end 21a of the side wall insulating film 21, but this is intentionally so that when the contact hole H4 is formed, The sidewall insulating film 21 is exposed in the contact hole H4, and as a result, the sidewall insulating film 21 is prevented from being etched together with the interlayer insulating film 23 described later. This point will be described in more detail again later when the method for manufacturing the semiconductor device 1 is described.

The partial liner insulating film 22ad is a portion connected to the lower end of the partial liner insulating film 22ac, and covers the mask film 20 via the sidewall insulating film 21. When the liner insulating film 22 is formed, the sidewall insulating film 21 exists on the side surface of the mask film 20, so that the inclined surface corresponding to the upper end 21 a of the sidewall insulating film 21 is formed on the surface of the liner insulating film 22. Is formed. The partial liner insulating film 22ad is formed by cutting the inclined surface by etching when forming the contact hole H4. Therefore, the film thickness Y _22ad of the partial liner insulating film 22ad is smaller than 10 nm at the time of film formation, specifically, a value equal to 10−Y ₂₁ . Since Y ₂₁ is 5 nm as described above, Y _22ad is also 5 nm. Further, the width Y2 in the y direction of the bit line structure BLS (part BLSb shown in FIG. 2) in the portion of the partial liner insulating film 22ad is Y _BL + 2 · Y ₂₁ + 2 · Y _22ad = 46 nm.

  The partial liner insulating film 22ae is a portion connected to the lower end of the partial liner insulating film 22ad. The upper surface of the partial liner insulating film 22ae is the above-described inclined surface (the inclined surface generated on the surface of the liner insulating film 22 due to the sidewall insulating film 21) is lowered by etching when the contact hole H4 is formed. .

The partial liner insulating film 22af is a portion connected to the lower end of the partial liner insulating film 22ae, and covers the mask film 20 via the sidewall insulating film 21. The partial liner insulating film 22af is the liner insulating film 22 remaining without being etched by the etching for forming the contact hole H4, and the film thickness Y _{22af thereof} is 10 nm. Therefore, the width Y1 in the y direction of the bit line structure BLS (part BLSa shown in FIG. 2) in the vicinity of the bit line BL is Y _BL + 2 · Y ₂₁ + 2 · Y _22af = 56 nm. Since this is the maximum value of the width in the y direction of the bit line structure BLS, the width Y _{S in} the y direction of the space between the bit line structures BLS adjacent in the y direction is P _BL −Y1 = 24 nm. Become.

  Now, the sidewall insulating film 21 and the liner insulating film 22 having the above-described shape have two roles. One is to prevent the bit line BL from being exposed in the contact hole H4 when the contact hole H4 is formed. Assuming that the liner insulating film 22 is formed of a silicon oxide film, the bit line is shifted slightly during the etching for forming the contact hole H4 in the interlayer insulating film 23, which is a silicon oxide film. BL is exposed in the contact hole H4. On the other hand, in the semiconductor device 1, since the liner insulating film 22 is composed of a silicon nitride film, an etching with a small selection ratio of the silicon nitride film to the silicon oxide film is used for the etching for forming the contact hole H4. Thus, even if the position of the contact hole H4 is shifted in the direction approaching the bit line BL, the state where the bit line BL is covered with the liner insulating film 22 can be maintained. Therefore, when the contact hole H4 is formed, exposure of the bit line BL into the contact hole H4 is prevented.

  The other is to reduce the parasitic capacitance between the capacitor contact plug CC formed in the contact hole H4 and the bit line BL. The sidewall insulating film 21 is formed of a silicon oxide film (relative dielectric constant: about 3.9) having a relative dielectric constant smaller than that of the silicon nitride film (relative dielectric constant: about 7.5). As compared with the case where the sidewall insulating film 21 is not used, the parasitic capacitance between the capacitor contact plug CC and the bit line BL is small.

  In the present embodiment, a silicon nitride film (SiN) is used as a constituent material of the liner insulating film 22, but any material other than the silicon nitride film can be used as long as the etching rate in the dry etching method is slower than that of the silicon oxide film. It is also possible to configure the liner insulating film 22 with a material. Examples of such a material include a carbon-containing silicon nitride film (SiCN) and a laminated film formed by laminating a silicon oxynitride film (SiON) on a silicon nitride film (SiN). In particular, the carbon-containing silicon nitride film (SiCN) has a relative dielectric constant of about 4.8, which is smaller than that of the silicon nitride film. It is possible to further reduce the parasitic capacitance between the plug CC and the bit line BL.

The sidewall insulating film 21 may be a film having a low relative dielectric constant other than a silicon oxide film (SiO ₂ ), such as a fluorine-containing silicon oxide film (SiOF, relative dielectric constant: about 3.5) or a carbon-containing silicon oxide film. It is also possible to use (SiOC, relative dielectric constant: 3.0) or the like.

  The description of other configurations will be continued. As shown in FIGS. 1B and 1C, an interlayer insulating film 23 that is a silicon oxide film is formed on the upper surface of the liner insulating film 22 c remaining on the upper surface of the interlayer insulating film 12. The upper surface of the interlayer insulating film 23 forms the same plane as the upper surface of the liner insulating film 22b.

In the interlayer insulating film 23, contact holes H4 (contact holes H4 _A and H4 _B ) are formed at positions corresponding to the upper portions of the impurity diffusion layers 8 (impurity diffusion layers 8 _A and 8 _B ). The contact hole H4 is a through hole penetrating the interlayer insulating film 23, and the impurity diffusion layer 8 corresponding to the bottom surface is exposed. The planar shape of the contact hole H4, in this embodiment, is square both equal to F value width _{X H4} and y direction width _{Y H4} in the x direction as shown in FIG. 1 (a) (40nm). However, as the planar shape of the contact hole H4, other shapes such as a circle, a rounded quadrangle, an ellipse, and a rectangle can be adopted.

The position of the contact hole H4 in the y direction is determined so as to be exactly in the middle between the adjacent bit line structures BLS. However, as described above, the width Y _{S in} the y direction of the space between the adjacent bit line structures BLS is 24 nm, which is smaller than the width Y _H4 (= 40 nm) in the y direction of the contact hole H4. Therefore, when the interlayer insulating film 23 is etched to provide the contact hole H4, a part of the bit line structure BLS is inevitably removed. As a result, as described above, the liner insulating film 22 has a complicated shape.

A sidewall insulating film 30 (third insulating film) that is a silicon nitride film formed in a sidewall shape is disposed on the inner side surface of the contact hole H4. Y direction of thickness _{Y 30} of the sidewall insulating film 30 is 5 nm. The sidewall insulating film 30 covers the entire inner surface of the contact hole H4. The sidewall insulating film 30 and the liner insulating film 22a constitute a single sidewall nitride film 60 as shown in FIG. 2 when viewed in a cross section corresponding to the line AA in FIG. To do.

Capacitor contact plug CC is embedded in contact hole H4 (inside sidewall insulating film 30). More specifically, a capacitive contact plug CC _A (second wiring) is embedded in the contact hole H4 _A (first through hole), and a capacitive contact plug is filled in the contact hole H4 _B (second through hole). CC _B (third wiring) is embedded. As shown in FIG. 1C, the capacitor contact plug CC is a conductor composed of a laminated film of a lower contact plug 31 and an upper contact plug 32. The upper surface of the upper contact plug 32 is formed of a liner insulating film 22b. It forms the same plane as the top surface.

The lower surface of the capacitor contact plug CC _A are connected to the corresponding impurity diffusion layers 8 _A, the top surface is connected to the corresponding storage element SN _A. Similarly, the lower surface of the capacitor contact plug CC _B are connected to the corresponding impurity diffusion layer 8 for _B, the upper surface is connected to the corresponding storage element SN _B. As a result, each capacitor contact plug CC serves to connect the corresponding impurity diffusion layer 8 and the corresponding storage element SN to each other.

As shown in FIG. 2, the capacitor contact plug CC also includes a portion CCa corresponding to the portion BLSa of the bit line structure BLS, a portion CCb corresponding to the portion BLSb of the bit line structure BLS, and the bit line structure BLS. And a portion CCc corresponding to the portion BLSc. The width C1 in the y direction of the portion CCa is determined from the width Y _S (24 nm) in the y direction of the space between the bit line structures BLS adjacent in the y direction to the film thickness Y ₃₀ (5 nm) in the y direction of the sidewall insulating film 30. Is a value obtained by subtracting 2 times (14 nm). The width C2 in the y direction of the portion CCb has a value (24 nm) equal to the width Y _S (24 nm) in the y direction of the space between the bit line structures BLS adjacent in the y direction. The width C3 in the y direction of the portion CCc is a value obtained by subtracting twice the thickness Y ₃₀ (5 nm) in the y direction of the sidewall insulating film 30 from the width Y _H4 (40 nm) in the y direction of the contact hole H4 ( ₃₀ nm). )

  On the upper surface of the interlayer insulating film 23, a stopper film 40, which is a silicon nitride film, and an interlayer insulating film 41, which is a silicon oxide film, are disposed in order from the bottom. The stopper film 40 and the interlayer insulating film 41 are provided with a cylinder hole H5 that is a cylindrical through hole for each capacitor contact plug CC. Inside each cylinder hole H5, a lower electrode 42, which is a bottomed cylindrical conductive film formed so as to cover the entire inner surface of the cylinder hole H5, is disposed. The lower electrode 42 constitutes one electrode of the corresponding storage element SN, and is connected to the upper surface of the corresponding capacitor contact plug CC on the lower surface.

  In addition to the lower electrode 42 described above, the memory element SN includes a capacitive insulating film 43 and an upper electrode 44 common to the memory elements SN. The upper electrode 44 is disposed on the inner side of the bottomed cylindrical lower electrode 42 and on the upper side of the lower electrode 42, and faces each lower electrode 42 with the capacitive insulating film 43 interposed therebetween. Therefore, the memory element SN according to the present embodiment is a cylindrical capacitor. Note that as the storage element SN, a crown-type or pillar-type capacitor may be used, or an element other than a capacitor such as a phase change element or a resistance change element may be used.

  An interlayer insulating film 45, which is a silicon oxide film, is formed on the upper surface of the upper electrode 44, and various metal wirings 47 are formed on the upper surface of the interlayer insulating film 45. The upper electrode 44 is connected to one of the metal wirings 47 by a contact plug 46 that penetrates the interlayer insulating film 45. A protective film 48 that is a silicon oxide film is formed on the upper surface of the metal wiring 47. The protective film 48 serves to protect the metal wiring 47.

  As described above, according to the semiconductor device 1 according to the present embodiment, the liner insulating film 22 having a relatively large relative dielectric constant protects the sidewall insulating film 21 from etching for forming the capacitive contact plug CC. Therefore, the sidewall insulating film 21 having a relatively small relative dielectric constant can be interposed between the bit line BL and the capacitor contact plug CC. Therefore, in the semiconductor device 1 that has been miniaturized, it is possible to reduce the parasitic capacitance generated between the bit line BL extending in the horizontal direction and the capacitor contact plug CC extending in the vertical direction.

  Next, a method for manufacturing the semiconductor device 1 according to the present embodiment will be described with reference to FIGS.

First, as shown in FIG. 3, a sacrificial film 3 made of a silicon oxide film (SiO ₂ ) is formed on the upper surface of the semiconductor substrate 2 which is a P-type silicon substrate by thermal oxidation. Subsequently, a mask film 4 made of a silicon nitride film (Si ₃ N ₄ ) is formed on the upper surface by thermal CVD (Chemical Vapor Deposition).

  Next, the sacrificial film 3 and the mask film 4 are patterned into a pattern of the active region K (an island pattern extending in a direction inclined with respect to the X direction) by using a photolithography method and a dry etching method. The short side of this pattern is 40 nm equal to the F value. Then, an element isolation trench H1 for partitioning the active region K is formed in the semiconductor substrate 2 by dry etching using this pattern as a mask. The element isolation trench H1 has a concave pattern surrounding the active region K. At this time, the region of the semiconductor substrate 2 that becomes the active region K is covered with the mask film 4.

  Next, a silicon oxide film is formed with a film thickness for embedding the element isolation trench H1 by CVD, and CMP (Chemical Mechanical Polishing) processing is performed until the upper surface of the mask film 4 is exposed as shown in FIG. As a result, the element isolation insulating film 5 is embedded in the element isolation trench H1. Thereafter, as shown in FIG. 5, the mask film 4, the sacrificial film 3, and the element isolation insulating film 5 formed above the upper surface of the semiconductor substrate 2 are removed by wet etching. Then, an n-type impurity diffusion layer 6 is formed in the vicinity of the surface of each active region K by ion-implanting N-type impurities such as phosphorus into the surface of the semiconductor substrate 2.

  Next, as shown in FIG. 6, an interlayer insulating film 12 made of, for example, a 50 nm-thick silicon oxide film and a hard mask film such as an amorphous carbon film (not shown) are formed on the upper surface of the semiconductor substrate 2 by CVD. Sequentially formed. Then, the hard mask film and the interlayer insulating film 12 are patterned into a pattern of the gate electrode trench H2 (gate trench pattern) by photolithography and dry etching. The gate trench pattern is a linear pattern straddling a plurality of active regions K juxtaposed in the y direction. In addition, two gate trench patterns are arranged in parallel per active region K. On the bottom surface of the gate trench pattern, the surface of the semiconductor substrate 2 and the surface of the element isolation insulating film 5 are alternately exposed in the y direction.

  Subsequently, the gate electrode trench H2 is formed in the semiconductor substrate 2 by etching the semiconductor substrate 2 and the element isolation insulating film 5 at a constant speed. The gate electrode trench H2 may be formed in the semiconductor substrate 2 by etching the semiconductor substrate 2 and the element isolation insulating film 5 separately. By forming the gate electrode trench H2, each active region K is divided into three active regions K1 to K3. Thereafter, a hard mask film (not shown) is selectively removed.

  Next, as shown in FIG. 7, the gate insulating film 10 is formed on the inner surface of the gate electrode trench H2. As the gate insulating film 10, a silicon oxide film formed by a thermal oxidation method can be preferably used. Thereafter, a conductive film made of titanium nitride (TiN) or tungsten (W) is sequentially deposited by a CVD method, and the conductive film is etched back by a dry etching method so as to remain only at the bottom of the gate electrode trench H2. As a result, the word line WL is formed so as to bury the lower portion of the gate electrode trench H2.

  Next, a silicon nitride film is formed on the entire surface by a CVD method, thereby burying the inside of the gate electrode trench H2 with the silicon nitride film. Then, by etching back the silicon nitride film until the upper surface of the interlayer insulating film 12 is exposed, as shown in FIG. 8, the buried insulating film 13 covering the upper surface of the gate electrode trench H2 and the upper surface of the word line WL. Buried by. After this step, the upper surface of the buried insulating film 13 and the upper surface of the interlayer insulating film 12 constitute the same plane.

Next, a mask film 50 is formed on the entire surface by forming an amorphous silicon film having a thickness of 60 nm by plasma CVD. Then, by removing the mask film 50 above the active region K2 using photolithography and dry etching, the mask film 50 is patterned into the pattern of the bit line contact plug BLC, and then the mask film 50 is used as a mask. The interlayer insulating film 12 exposed by removing the mask film 50 is etched by a dry etching method. As a result, as shown in FIG. 9, a hole-shaped bit contact opening H3 with the impurity diffusion layer 6 exposed at the bottom is formed. Thereafter, N-type impurities such as arsenic are ion-implanted again into the surface of the semiconductor substrate 2 through the bit contact opening H3, whereby the impurity diffusion layer 6 exposed at the bottom surface of the bit contact opening H3 is used as the impurity diffusion layer 7. As described above, the impurity diffusion layer 7 functions as one controlled electrode (source or drain) common to the cell transistors Tr _A and Tr _B.

  Subsequently, a conductive film made of a silicon film containing N-type impurities such as phosphorus is deposited by thermal CVD. Then, the conductive film and the mask film 50 are removed until the upper surface of the interlayer insulating film 12 and the upper surface of the buried insulating film 13 are exposed. After this step, the conductive film remains in the bit contact opening H3, and as shown in FIG. 10, the bit line contact plug BLC connected to the impurity diffusion layer 7 on the lower surface is formed.

Next, a laminated conductive film is formed by sequentially depositing a titanium (Ti) film, a titanium nitride (TiN) film, a tungsten silicide (WSi ₂ ) film, and a tungsten (W) film by a sputtering method or a CVD method. Note that the titanium film formed on the upper surface of the bit line contact plug BLC made of silicon is converted into titanium silicide simultaneously with the film formation, which contributes to a reduction in contact resistance. The film thickness of the laminated conductive film is 30 nm. After the laminated conductive film is formed, a silicon nitride film having a thickness of 120 nm is further formed by plasma CVD. Then, by sequentially patterning the silicon nitride film and the laminated conductive film using a photolithography method and a dry etching method, as shown in FIG. 11, the bit line BL and the mask film 20 covering the upper surface of the bit line BL are formed. Form. Each width _{Y BL} and the arrangement pitch _{P BL} of the bit line BL, 26 nm as described above, and 80 nm. Therefore, the space width Y _S1 between the bit lines BL is 54 nm. The lower surface of the bit line BL is connected to the upper surface of a series of bit line contact plugs BLC arranged in the x direction.

Next, a 5 nm-thickness silicon oxide film is formed on the entire surface so as to cover the side surface of the bit line BL by ALD. By etching back the silicon oxide film, as shown in FIG. 12, to form the sidewall insulating film 21 up to a thickness Y ₂₁ in the y direction is 5nm on the side surface of the bit line BL. By this etch back, the upper surface of the sidewall insulating film 21 is inclined as shown in FIGS.

In the etch back, as described above with reference to FIG. 2, the distance Z1 from the upper surface of the mask film 20 to the upper end 21a of the sidewall insulating film 21 is the film thickness when the liner insulating film 22 is formed later. The etchback amount is controlled so as to be 2 to 7 times (10 nm), more preferably 2 to 4 times. The reason is as described above. In this embodiment, the etch back amount is controlled so that the distance Z1 is 20 nm. As a result, since the distance Z ₂₁ (see FIG. 2) from the upper surface of the interlayer insulating film 12 to the upper end 21a of the sidewall insulating film 21 is 130 nm, the side surface in the y direction of the bit line BL is completely covered by the sidewall insulating film 21. It becomes a state covered with.

  The sidewall insulating film 21 is formed by forming a silicon oxide film on a silicon nitride film having a thickness in the range of 0.5 to 1.0 nm (10% to 20% of the thickness of the sidewall insulating film 21). It is good also as a laminated film formed. By doing so, it becomes possible to prevent the side surface of the bit line BL from being oxidized.

Next, as shown in FIG. 13, a liner insulating film 22 made of a silicon nitride film having a thickness Y ₂₂ of 10 nm is formed on the entire surface by ALD. As a result, the width Y _S of the space between adjacent bit lines BL (the distance between the surfaces of the liner insulating film 22) is 24 nm as described above. At this time, the liner insulating film 22 is formed with inclined portions corresponding to the above-described partial liner insulating films 22aa and 22ae (see FIG. 2), as shown in FIG.

Next, a polysilazane organic film is formed by a spin coating method so as to fill a space between adjacent bit lines BL. Then, the polysilazane organic film is converted into a silicon oxide film by heat treatment in an oxidizing atmosphere such as ozone. Thereafter, the upper surface of the silicon oxide film is planarized by CMP until the upper surface of the liner insulating film 22 is exposed, thereby forming an interlayer insulating film 23 as shown in FIG. Height _{Z 23} of the interlayer insulating film 23 becomes 150 nm. The liner insulating film 22 is a silicon oxynitride film (SiON) having a thickness in the range of 0.5 to 2.0 nm (5% to 20% of the thickness of the liner insulating film 22). It may be a laminated film formed on SiN). This facilitates formation of the interlayer insulating film 23.

Next, as shown in FIG. 15, a mask film 51 made of a silicon nitride film having a thickness of 20 nm covering the upper surface of the interlayer insulating film 23 and the upper surface of the liner insulating film 22 is formed by CVD. Then, an opening H4a corresponding to the position where the capacitive contact plug CC is formed is provided in the mask film 51 by photolithography and dry etching. In the present embodiment, the planar shape of the opening H4a is a square in which the width in the x direction and the width in the y direction are both equal to the F value (40 nm). Since the space width Y _S between the adjacent bit lines BL is 24 nm, the opening H4a overlaps a part of the liner insulating film 22 in plan view. Each opening H4a is formed at a position overlapping the element isolation insulating film 5 and one of the active regions K1 and K3 in plan view.

Next, the interlayer insulating film 23 exposed on the bottom surface of the opening H4a is removed by anisotropic dry etching, thereby forming an opening H4b as shown in FIG. The liner insulating film 22 formed on the upper surface of the interlayer insulating film 12 is exposed at the bottom surface of the opening H4b. Further, the liner insulating film 22 and the interlayer insulating film 23 are exposed on the side surface of the opening H4b. This etching is performed by a so-called SAC (Self Alignment Contact) method for a portion where the liner insulating film 22 is exposed on the side surface of the opening H4b. In this etching, hexafluoro-1,3-butadiene (C ₄ F ₆ ) with a flow rate of 25 sccm and oxygen (O ₂ ) with a flow rate of 25 sccm are used as source gases, the source power is 1700 W, the bias power is 3000 W, and the stage It is preferable that the temperature is 30 ° C. and the pressure is 30 mTorr. The selectivity between the silicon oxide film and the silicon nitride film in the etching performed under this condition (= silicon oxide film etching rate / silicon nitride film etching rate) is 20.

  As understood from comparison between FIG. 15 and FIG. 16, not only the silicon oxide film but also the silicon nitride film is etched to a small extent by the above etching. More specifically, first, the thickness of the mask film 51 is decreased by 7.5 nm from 20 nm to 12.5 nm. Further, the inclined portions (partial liner insulating films 22aa and 22ae) generated in the liner insulating film 22 are etched from the respective upper surfaces. As a result, as shown in FIG. 16, a part of the partial liner insulating film 22aa is 7%. The partial liner insulating film 22ac is lowered by .5 nm, and the position of the partial liner insulating film 22ae is lowered by 7.5 nm.

  The lowered partial liner insulating film 22ae is located at a position lower than the upper end of the sidewall insulating film 21, but the liner insulating film 22 has a film thickness (10 nm) of the sidewall insulating film 21 (5 nm). Therefore, the side wall insulating film 21 is not exposed in the opening H4b by the etching.

Next, the liner insulating film 22 exposed on the bottom surface of the opening H4b is removed by anisotropic dry etching, thereby forming the opening H4c as shown in FIG. The side surface in the y direction of the opening H4c is configured by the liner insulating film 22, and the side surface in the x direction is configured by the interlayer insulating film 23. The bottom surface of the opening H4c is composed of the interlayer insulating film 12 and the buried insulating film 13 depending on the position of the opening H4c. This etching uses trifluoromethane (CHF ₃ ) with a flow rate of 80 sccm, oxygen (O ₂ ) with a flow rate of 20 sccm, and argon (Ar) with a flow rate of 150 sccm as source gases, a source power of 1700 W, a bias power of 3000 W, and a stage temperature. It is preferable to carry out under the conditions of 30 ° C. and a pressure of 30 mTorr.

  The etching is performed to remove the liner insulating film 22 made of a silicon nitride film having a thickness of 10 nm. Therefore, the film thickness of the mask film 51 is reduced by 10 nm from 12.5 nm to 2.5 nm. Further, the positions of the partial liner insulating films 22ac and 22ae are lowered by 10 nm. Even by this etching, the thickness (10 nm) of the liner insulating film 22 is larger than the thickness (5 nm) of the sidewall insulating film 21, so that the sidewall insulating film 21 is not exposed in the opening H4c.

  Next, the interlayer insulating film 12 exposed on the bottom surface of the opening H4c is removed by anisotropic dry etching, thereby completing the contact hole H4 as shown in FIG. Here, the opening H4c is extended into the interlayer insulating film 12 by etching the interlayer insulating film 12 made of a silicon oxide film by the SAC method using the liner insulating film 22 made of a silicon nitride film as a mask. The side surface of the contact hole H4 is composed of the liner insulating film 22, the interlayer insulating films 12 and 23, and the buried insulating film 13 depending on the position of the contact hole H4. Further, the impurity diffusion layer 6 and the element isolation insulating film 5 are exposed on the bottom surface of the contact hole H4. This etching is preferably performed under the same conditions as when the interlayer insulating film 23 exposed on the bottom surface of the opening H4a is removed. In this case, the selection ratio between the silicon oxide film and the silicon nitride film is 20 as described above.

  When the interlayer insulating film 12 made of a silicon oxide film having a thickness of 50 nm is removed under the above conditions, the silicon nitride film for 2.5 nm is etched. Therefore, since the mask film 51 having the remaining thickness of 2.5 nm is completely removed, in the region other than the region where the contact hole H4 is formed, as illustrated in FIG. Is exposed. Further, the positions of the partial liner insulating films 22ac and 22ae are further lowered by 2.5 nm. This etching also prevents the sidewall insulating film 21 from being exposed in the contact hole H4 because the film thickness (10 nm) of the liner insulating film 22 is larger than the film thickness (5 nm) of the sidewall insulating film 21.

  Here, if the upper end of the sidewall insulating film 21 is at a higher position, the sidewall insulating film 21 may be exposed in the contact hole H4 as a result of etching as described above. Hereinafter, this will be described in detail with reference to FIG.

  In the example shown in FIG. 20, the upper end 21 a of the sidewall insulating film 21 is positioned at the same height as the upper surface of the mask film 20 as shown in FIG. Therefore, the distance Z1 from the upper surface of the mask film 20 to the upper end 21a of the sidewall insulating film 21 is 0 nm. Further, the inclined portion corresponding to the partial liner insulating film 22ae is not formed.

  In this case, when the openings H4a, H4b, H4c and the contact hole H4 are sequentially formed by proceeding the etching similar to the above, as shown in the region X of FIGS. A part of the liner insulating film 22 formed on the surface of the film 21 becomes extremely thin. Therefore, the sidewall insulating film 21 is exposed in the opening only by slightly shifting the position of the opening H4a. Since the contact hole H4 is formed by etching with a high selectivity with respect to the silicon oxide film, the exposed sidewall insulating film 21 is greatly shaved, making it difficult to maintain the quality of the semiconductor device 1. Specifically, when the constituent material of the capacitor contact plug CC enters a recess formed by the side wall insulating film 21 being scraped, the bit line BL and the capacitor contact plug CC, or the capacitor contact plug CC adjacent in the x direction. There is an increased risk of occurrence of a short circuit between each other. In the present embodiment, as shown in FIG. 12, the upper end 21a of the sidewall insulating film 21 is separated from the upper surface of the mask film 20 to some extent (specifically, the distance Z1 is set to 20 nm). In addition, a part of the liner insulating film 22 is prevented from being extremely thin. Therefore, the occurrence of the short circuit as described above is avoided, so that the quality of the semiconductor device 1 can be maintained.

Returning to the description of the manufacturing method of the semiconductor device 1. After the contact hole H4 is formed, a silicon nitride film having a film thickness of 5 nm is formed by thermal CVD and further etched back, so that the inner surface of the contact hole H4 is covered as shown in FIG. direction of thickness _{Y 30} to form a side wall insulating film 30 is 5 nm. Subsequently, a silicon film containing phosphorus is deposited inside the contact hole H4 by a thermal CVD method. Then, by etching back the silicon film, the lower contact plug 31 made of the silicon film is left only at the bottom of the contact hole H4. In this step, phosphorus diffuses into the impurity diffusion layer 6 exposed at the bottom surface of the contact hole H4, and the impurity diffusion layer 8 (impurity diffusion layers 8 _A and 8 _B ) that contacts the lower surface of the lower contact plug 31 on the upper surface. Is formed. As described above, the impurity diffusion layers 8 _A and 8 _B function as the other controlled electrode (source or drain) of each of the cell transistors Tr _A and Tr _B.

  Subsequently, an intervening layer (not shown) made of cobalt silicide (CoSi) is formed on the upper surface of the lower contact plug 31 by sputtering, and then a tungsten film is formed to fill the contact hole H4 by CVD. Then, the upper contact plug 32 is embedded in the contact hole H4 by performing planarization until the upper surfaces of the interlayer insulating film 23 and the liner insulating film 22 are exposed by CMP. As a result, the capacitor contact plug CC constituted by the laminated film of the lower contact plug 31 and the upper contact plug 32 is formed. Thereafter, as shown in FIG. 1, the memory element SN and the metal wiring 47 are formed, and the protective film 48 is further formed, whereby the semiconductor device 1 is completed.

  As described above, according to the method for manufacturing the semiconductor device 1 according to the present embodiment, the sidewall insulating film 21 having a relatively small relative dielectric constant is interposed between the bit line BL and the capacitor contact plug CC. It becomes possible. Therefore, as described above, in the semiconductor device 1 that has been miniaturized, it is possible to reduce the parasitic capacitance generated between the bit line BL extending in the horizontal direction and the capacitor contact plug CC extending in the vertical direction. Become.

  Here, a decrease in parasitic capacitance will be described with specific numerical values.

In the semiconductor device 1, as shown in FIG. 2, a sidewall insulating film 21 having a film thickness Y ₂₁ (= 5 nm) and a film thickness Y _22af (= 10 nm) are provided between the adjacent bit line BL and the capacitor contact plug CC. The liner insulating film 22 and the sidewall insulating film 30 with a film thickness Y ₃₀ (= 5 nm) are insulated. Therefore, if the relative dielectric constant ε _sio of the silicon oxide film is 3.9, the relative dielectric constant ε _sin of the silicon nitride film is 7.0, and the vacuum dielectric constant is ε ₀ , the adjacent bit line BL and the capacitor contact plug CC parasitic capacitance Cb1 in per unit area between is calculated as 0.29Ipushiron ₀ as shown in the following equation (1).
Cb1 = 1 / (1 / ( ε sin × ε 0 / (Y 30 + Y 22af)) + 1 / (ε sio × ε 0 / Y 21)) = 1 / (1 / (7.0 × ε 0 / (5 + 10 )) + 1 / (3.9 × ε ₀ /5))≈0.29ε ₀ (1)

On the other hand, if the sidewall insulating film 30 is a silicon nitride film, the parasitic capacitance Cb2 per unit area between the adjacent bit line BL and the capacitive contact plug CC is expressed by the following equation (2). It is calculated as 0.35Ipushiron ₀ as shown in).
Cb2 = 1 / (1 / ( ε sin × ε 0 / (Y 30 + Y 22af + Y 21)) = 7.0 × ε 0 /(5+10+5)=0.35ε 0 ··· (2)

  As is apparent from the above calculation results, the parasitic capacitance Cb1 is 17% smaller than the parasitic capacitance Cb2. Therefore, according to the semiconductor device 1 according to the present embodiment, it can be said that the parasitic capacitance between the adjacent bit line BL and the capacitive contact plug CC can be reduced by 17%.

The specific reduction amount of the parasitic capacitance varies depending on the film thickness Y ₃₀ of the sidewall insulating film 30, the film thickness Y _22af of the liner insulating film 22, and the film thickness Y ₂₁ of the sidewall insulating film 21. In any case, in the semiconductor device 1 according to the present embodiment, the sidewall insulating film 30 is composed of a silicon oxide film having a relative dielectric constant smaller than that of the silicon nitride film. In comparison, parasitic capacitance can be reduced.

  Next, a semiconductor device 1 according to a second embodiment of the present invention will be described with reference to FIG. The semiconductor device 1 according to the present embodiment is the first in that a stacked film of a sidewall insulating film 35 that is a silicon nitride film and a sidewall insulating film 36 that is a silicon oxide film is used instead of the sidewall insulating film 30. Unlike the semiconductor device 1 according to the first embodiment, the other points are the same as those of the semiconductor device 1 according to the first embodiment. Therefore, the same reference numerals are given to the same components as those of the semiconductor device 1 according to the first embodiment, and the following description will be made focusing on differences from the semiconductor device 1 according to the first embodiment.

  In this embodiment, after providing the contact hole H4, a silicon nitride film having a thickness of 3 nm is first formed by a thermal CVD method, and further etched back to cover the inner surface of the contact hole H4. A sidewall insulating film 35 having a thickness in the y direction of 3 nm is formed. Subsequently, a sidewall oxide film 36 having a thickness of 2 nm in the y direction is formed so as to cover the surface of the sidewall insulation film 35 by forming a silicon oxide film having a thickness of 2 nm and further performing etch back. Form. The total thickness of the sidewall insulating films 35 and 36 is 5 nm, which is the same as that of the sidewall insulating film 30 in the first embodiment.

  According to the semiconductor device 1 according to the present embodiment, the parasitic capacitance between the bit line BL and the capacitive contact plug CC is further increased by providing the sidewall insulating film 36 than in the semiconductor device 1 according to the first embodiment. It becomes possible to reduce.

In the present embodiment, the sidewall insulating film 36 is a silicon oxide film (SiO ₂ ). However, like the sidewall insulating film 21, a film having a low relative dielectric constant other than the silicon oxide film, for example, a fluorine-containing silicon oxide film The sidewall insulating film 36 can also be constituted by (SiOF, relative dielectric constant: about 3.5), a carbon-containing silicon oxide film (SiOC, relative dielectric constant: 3.0), or the like.

  The preferred embodiments of the present invention have been described above, but the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. Needless to say, it is included in the range.

DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 Semiconductor substrate 3 Sacrificial film 4 Mask film 5 Element isolation insulating films 6-8 Impurity diffusion layer 10 Gate insulating films 12, 23, 41, 45, 60 Interlayer insulating film 13 Buried insulating film 20 Mask film 21, 30, 35, 36 Side wall insulating film 21a Upper ends 22, 22a to 22c of side wall insulating film 21 Liner insulating films 22aa to 22af Partial liner insulating film 31 Lower contact plug 32 Upper contact plug 40 Stopper film 42 Lower electrode 43 Capacitive insulating film 44 Upper electrode 46 Contact plug 47 Metal wiring 48 Protective film 50, 51 Mask film BL Bit line BLC Bit line contact plug BLS Bit line structure BLSa to BLSc Partial CC capacitor bit plug CCa to CCc Capacity contact plug of bit line structure BLS CC part H1 Element isolation trench H2 Gate electrode trench H3 Bit contact opening H4 Contact hole H4a to H4c Opening H5 Cylinder hole K, K1 to K3 Active region SN Memory element Tr Cell transistor WL Word line

Claims (20)

A first wiring formed to extend along the first plane;
A second wiring formed to extend in a direction intersecting the first plane;
An insulating film disposed so as to separate the first wiring and the second wiring;
The insulating film is
A first insulating film having a relatively small relative dielectric constant and covering a side surface of the first wiring;
And a second insulating film having a relatively large relative dielectric constant and covering a side surface of the first wiring with the first insulating film interposed therebetween. The first insulating film is a silicon oxide film;
The semiconductor device according to claim 1, wherein the second insulating film is a silicon nitride film. An interlayer insulating film covering the first wiring;
The semiconductor device according to claim 1, wherein the second wiring is formed in a through hole that penetrates the interlayer insulating film. The semiconductor device according to claim 3, further comprising a third insulating film that covers an inner surface of the through hole. The semiconductor device according to claim 4, wherein the third insulating film is a silicon nitride film. The semiconductor device according to claim 4, further comprising a fourth insulating film that covers an inner surface of the through-hole through the third insulating film. The semiconductor device according to claim 6, wherein the fourth insulating film is a silicon oxide film. A plurality of the first wirings formed in parallel to each other;
The semiconductor device according to claim 1, wherein the second wiring is formed so as to pass between two adjacent first wirings. The first plane is a plane parallel to the main surface of the semiconductor substrate;
The semiconductor device includes:
A cell transistor having first and second impurity diffusion layers embedded in the main surface,
A storage element formed above the plurality of first wirings;
Each of the plurality of first wirings is a bit line;
One of the plurality of first wirings is in contact with the first impurity diffusion layer on a lower surface,
The semiconductor device according to claim 8, wherein the second wiring is a contact plug that connects the second impurity diffusion layer and the memory element. A plurality of first wirings each extending along a first plane parallel to the main surface of the semiconductor substrate and formed in parallel with each other;
A mask film covering an upper surface of each of the plurality of first wirings;
A second wiring that extends in a direction intersecting with the first plane and is formed so as to pass between two adjacent first wirings;
An insulating film disposed so as to separate the first wiring and the second wiring;
The insulating film is
A first insulating film having a relatively small relative dielectric constant and covering a side surface of the first wiring;
A second insulating film having a relatively large relative dielectric constant and covering a side surface of the first wiring via the first insulating film,
The semiconductor device according to claim 1, wherein the first insulating film is formed such that an upper end thereof is located at a position lower than an upper surface of the mask film. The first insulating film is a silicon oxide film;
The semiconductor device according to claim 10, wherein the second insulating film is a silicon nitride film. A cell transistor having first and second impurity diffusion layers embedded in the main surface,
A storage element formed above the plurality of first wirings;
Each of the plurality of first wirings is a bit line;
One of the plurality of first wirings is in contact with the first impurity diffusion layer on a lower surface,
The semiconductor device according to claim 10, wherein the second wiring is a contact plug that connects the impurity diffusion layer and the memory element. An isolation insulating film for element isolation that divides a plurality of active regions arranged in a first direction parallel to the main surface into the main surface by being embedded in the main surface of the semiconductor substrate;
Each of the plurality of active regions is divided into first to third active regions in order from one end side in a second direction parallel to the main surface and perpendicular to the first direction, respectively. Two fourth wires extending in the direction;
A plurality of first wirings extending in the first direction corresponding to each of the plurality of active regions and electrically connected to the second active region corresponding to the lower surface;
Extending between the two adjacent first wirings corresponding to each of the plurality of active regions in a third direction orthogonal to the first and second directions, and corresponding at the bottom surface A plurality of second wirings electrically connected to the first active region;
The two first wirings adjacent to each other corresponding to each of the plurality of active regions extend in the third direction and are electrically connected to the corresponding third active region on the lower surface. A plurality of third wirings,
An insulating film disposed to separate the plurality of first wirings from the plurality of second and third wirings;
The insulating film is
A first insulating film having a relatively low dielectric constant and covering a side surface of each of the plurality of first wirings;
And a second insulating film having a relatively large relative dielectric constant and covering a side surface of each of the plurality of first wirings via the first insulating film. The first insulating film is a silicon oxide film;
The semiconductor device according to claim 13, wherein the second insulating film is a silicon nitride film. An impurity diffusion layer is formed in the first to third active regions of each of the plurality of active regions,
The impurity diffusion layer provided corresponding to each of the plurality of active regions and formed in the corresponding first active region is used as one controlled electrode, and is formed in the corresponding second active region. A plurality of first cells having the impurity diffusion layer as the other controlled electrode and the fourth wiring located between the corresponding first active region and the corresponding second active region as the control electrode A transistor,
The impurity diffusion layer provided corresponding to each of the plurality of active regions and formed in the corresponding third active region is used as one controlled electrode, and is formed in the corresponding second active region. A plurality of second cells having the impurity diffusion layer as the other controlled electrode and the fourth wiring located between the corresponding third active region and the corresponding second active region as the control electrode A transistor,
A first storage element provided corresponding to each of the plurality of active regions and connected to the second wiring corresponding to the lower surface;
The semiconductor device according to claim 13, further comprising: a second storage element provided corresponding to each of the plurality of active regions and connected to the third wiring corresponding to the lower surface. apparatus. Forming a first wiring whose upper surface is covered with a mask film;
A first insulating film having a relatively small relative dielectric constant is formed and etched back to cover a part of the side surface of the mask film and the side surface of the first wiring with the first insulating film. Process,
After forming the first insulating film, a second insulating film having a relatively large relative dielectric constant is formed and etched back, thereby exposing the exposed surface of the first insulating film to the second insulating film. A step of covering with an insulating film;
An interlayer insulating film is formed with a thickness that fills a region between the first wiring and the wiring structure including the first and second insulating films, and the interlayer is formed until the upper surface of the wiring structure is exposed. Flattening the upper surface of the insulating film;
Providing a first through hole in the interlayer insulating film;
Forming a second wiring separated from the first wiring by the first and second insulating films by embedding a conductive film in the first through-hole. A method for manufacturing a semiconductor device. The first insulating film is a silicon oxide film;
The method of manufacturing a semiconductor device according to claim 16, wherein the second insulating film is a silicon nitride film. Burying an element isolation insulating film in the main surface of the semiconductor substrate to partition an active region in the main surface;
Dividing the active region into first to third active regions by embedding two fourth wires parallel to each other in the main surface;
Forming an impurity diffusion layer in each of the first to third active regions by implanting impurities into the main surface,
The first wiring is formed so as to be electrically connected to the impurity diffusion layer formed in the second active region on a lower surface,
The first through hole is formed so that the first active region is exposed on a bottom surface, whereby the second wiring is formed on the bottom surface with the impurity diffusion layer formed in the first active region. The method for manufacturing a semiconductor device according to claim 16, wherein the semiconductor device is electrically connected. Providing a second through hole in the interlayer insulating film;
Forming a third wiring separated from the first wiring by the first and second insulating films by embedding a conductive film in the second through-hole,
The second through hole is formed so that the third active region is exposed on a bottom surface, whereby the third wiring is formed on the lower surface with the impurity diffusion layer formed in the third active region. The method for manufacturing a semiconductor device according to claim 18, wherein the semiconductor device is electrically connected. In the step of forming the first wiring, a plurality of the first wirings are formed so as to be parallel to each other,
20. The semiconductor device manufacturing method according to claim 16, wherein the first through hole is formed so as to pass between two adjacent first wirings. Method.

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