JP2016072353A - Group iii nitride semiconductor device and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a group III nitride semiconductor device having a super junction structure; and provide a manufacturing method of the group III nitride semiconductor device.SOLUTION: A group III nitride semiconductor device 2 includes as a group III nitride semiconductor structure 20: a plurality of first 1p semiconductor regions 21ap each having a first crystal orientation and a p-type conductivity type; and a first 2n semiconductor regions 21bn which are arranged among the first 1p semiconductor regions 21ap and adjacent to the first 1p semiconductor regions 21ap and has a second crystal orientation different from the first crystal orientation and an n-type conductivity type. The first 1p semiconductor regions 21ap and the first 2n semiconductor regions 21bn include p/n regions 21pn which lie from one principal surface 21m to another principal surface 21n, and further include a Schottky electrode 30 which is arranged on the one principal surface 21m side of the p/n regions 21pn and electrically connected to at least some of the first 1p semiconductor regions 21ap and forms Schottky contact with the first 2n semiconductor regions 21bn.SELECTED DRAWING: Figure 5

Description

  The present invention relates to a group III nitride semiconductor device and a manufacturing method thereof, and more particularly to a group III nitride semiconductor device having a super junction structure and a manufacturing method thereof.

  From the viewpoint of forming a semiconductor device having a high breakdown voltage and a low on-resistance, a semiconductor device having a super junction structure has been proposed.

  For example, Japanese Unexamined Patent Application Publication No. 2007-042997 (Patent Document 1) discloses a semiconductor substrate, a first surface that is a surface on the semiconductor substrate side, and a second surface that is a surface opposite to the first surface. An impurity region layer made of a semiconductor and an electrode formed on the impurity region layer, wherein the impurity region layer includes a first conductivity type first impurity region that reaches the first surface from the second surface; A second conductivity type second impurity region which is disposed adjacent to the first impurity region and sandwiching the first impurity region and extending from the second surface toward the first surface is formed; Discloses a semiconductor device in Schottky contact with a first impurity region and electrically connected to a second impurity region, and a method for manufacturing the same.

  Japanese Patent Laying-Open No. 2011-003919 (Patent Document 2) discloses a first conductivity type substrate made of a semiconductor, a first conductivity type semiconductor layer formed on the substrate, and a first conductivity type semiconductor layer. And a second conductivity type semiconductor region that is connected to the electrode and protrudes from the first conductivity type semiconductor layer, the second conductivity type semiconductor region being different from the first conductivity type. The region includes a low impurity region having a lower concentration of the second conductivity type impurity in the boundary region with the first conductivity type semiconductor layer than the region in the second conductivity type semiconductor region adjacent to the boundary region. A semiconductor device and a manufacturing method thereof are disclosed.

JP 2007-042997 A JP 2011-003919 A

  In the semiconductor device disclosed in Japanese Patent Laying-Open No. 2007-042997 (Patent Document 1), a first conductivity type is formed on a semiconductor substrate when forming a first impurity region and a second impurity region as impurity regions of a semiconductor such as SiC. The impurity layer is formed, a groove is formed across the region to be the first impurity region, and a second conductivity type impurity layer is formed in the groove to form the second impurity region. For this reason, such a semiconductor device has a problem that the manufacturing efficiency is low and the manufacturing cost is high.

  In the semiconductor device disclosed in Japanese Patent Application Laid-Open No. 2011-003919 (Patent Document 2), when a first conductive type semiconductor layer and a second conductive type semiconductor region are formed as a semiconductor such as SiC, a first semiconductor made of semiconductor is used. A first conductivity type semiconductor layer is formed on a conductivity type substrate, and ions are implanted into the first conductivity type semiconductor layer to form a second conductivity type semiconductor region. However, the group III nitride semiconductor layer has a problem that it is difficult to switch from the first conductivity type (for example, n-type) to the second conductivity type (for example, p-type) by ion implantation.

  Accordingly, it is an object of the present invention to provide a group III nitride semiconductor device having a super junction structure and a method for manufacturing the same by solving the above problems.

  A group III nitride semiconductor device according to an aspect of the present invention includes, as a group III nitride semiconductor structure, a plurality of first 1p semiconductor regions having a first crystal orientation and a p-type conductivity, A first 2n semiconductor region having a second crystal orientation different from the first crystal orientation and an n-type conductivity type disposed between and adjacent to the first 1p semiconductor region; Including a p / n region in which the first 1p semiconductor region and the first 2n semiconductor region exist from one main surface to another main surface, and is disposed on one main surface side of the p / n region, And a Schottky electrode that is electrically connected to at least a part of the 1p semiconductor region and is in Schottky contact with the first 2n semiconductor region.

  A method for manufacturing a group III nitride semiconductor device according to another aspect of the present invention includes: a plurality of first 1p semiconductor regions having a first crystal orientation and a p-type conductivity type; A first 2n semiconductor region having a second crystal orientation and an n-type conductivity different from the first crystal orientation disposed between and adjacent to the first 1p semiconductor region; Forming a group III nitride semiconductor structure including a p / n region including a first 1p semiconductor region and a first 2n semiconductor region extending from one main surface to another main surface; and p / n Forming a Schottky electrode electrically connected to at least a part of the first 1p semiconductor region and in Schottky contact with the first 2n semiconductor region on one main surface side of the region.

  According to the above, a group III nitride semiconductor device having a super junction structure and a method for manufacturing the same can be provided.

It is a schematic sectional drawing which shows the 1st example of the group III nitride semiconductor device concerning a certain form of this invention. It is a schematic sectional drawing which shows the 2nd example of the group III nitride semiconductor device concerning a form with this invention. It is a schematic sectional drawing which shows the 3rd example of the group III nitride semiconductor device concerning a certain form of this invention. It is a schematic sectional drawing which shows the 4th example of the group III nitride semiconductor device concerning a form with this invention. It is a schematic sectional drawing which shows the 5th example of the group III nitride semiconductor device concerning a form with this invention. It is a schematic sectional drawing which shows an example of the manufacturing method of the group III nitride semiconductor device concerning another form of this invention. It is a schematic sectional drawing which shows an example of the manufacturing method of the electroconductive board | substrate used in the manufacturing method of the group III nitride semiconductor device of this invention. It is a schematic sectional drawing which shows another example of the manufacturing method of the group III nitride semiconductor device concerning another form of this invention. It is a schematic sectional drawing which shows an example of the manufacturing method of the composite substrate used in the manufacturing method of the group III nitride semiconductor device of this invention. It is a schematic sectional drawing which shows another example of the manufacturing method of the group III nitride semiconductor device concerning another form of this invention.

<Description of Embodiment of the Present Invention>
A group III nitride semiconductor device according to an embodiment of the present invention includes, as a group III nitride semiconductor structure, a plurality of first 1p semiconductor regions having a first crystal orientation and a p-type conductivity, A first 2n semiconductor region having a second crystal orientation different from the first crystal orientation and an n-type conductivity type disposed between and adjacent to the first 1p semiconductor region; The first 1p semiconductor region and the first 2n semiconductor region include a p / n region existing from one main surface to another main surface, and are disposed on the one main surface side of the p / n region, It further includes a Schottky electrode that is electrically connected to at least a portion of the first 1p semiconductor region and is in Schottky contact with the first 2n semiconductor region.

  Since the group III nitride semiconductor device of the present embodiment includes a super junction structure formed by the first 1p semiconductor region and the first 2n semiconductor region, the breakdown voltage can be increased.

  In the group III nitride semiconductor device of the present embodiment, the group III nitride semiconductor structure is disposed on the other main surface side of the p / n region, and is disposed in contact with the first 1p semiconductor region. A second 1n semiconductor region having a crystal orientation and an n-type conductivity type, and disposed in contact with and between the second 1n semiconductor region and adjacent to the second 1n semiconductor region A second 2n semiconductor region having a second crystal orientation and an n-type conductivity, wherein the second 1n semiconductor region exists from one main surface to another main surface and An n / n region in which the 2n semiconductor region exists at least on one main surface side can be further included. Such a III-nitride semiconductor device includes a super junction structure formed by the first 1p semiconductor region, the first 2n semiconductor region, the second 2n semiconductor region, and the second 1n semiconductor region, so that the withstand voltage is reduced. Can be high.

  The group III nitride semiconductor device of this embodiment can further include a conductive substrate. Since the group III nitride semiconductor device includes a conductive substrate, an increase in on-resistance can be suppressed.

  The group III nitride semiconductor device of the present embodiment can further include a mask disposed on a part of the conductive substrate. Since the III-nitride semiconductor device includes a mask disposed on a part of the conductive substrate, the first 1p semiconductor region, the first 2n semiconductor region, the second 2n semiconductor region, The super junction structure formed with the 2 1n semiconductor region is efficiently formed.

  In the group III nitride semiconductor device of this embodiment, the second crystal orientation can increase oxygen uptake in the group III nitride semiconductor structure as compared to the first crystal orientation. In such a group III nitride semiconductor device, the second crystal orientation has a larger oxygen uptake in the group III nitride semiconductor structure than the first crystal orientation. Even if the body is formed, a super junction structure formed of at least the first 1p semiconductor region and the first 2n semiconductor region can be included in the group III nitride semiconductor structure, and the breakdown voltage can be increased.

  A method for manufacturing a group III nitride semiconductor device according to another embodiment of the present invention includes: a plurality of first 1p semiconductor regions having a first crystal orientation and a p-type conductivity type; A first 2n semiconductor region having a second crystal orientation different from the first crystal orientation and an n-type conductivity type disposed between and adjacent to the first 1p semiconductor region; Forming a group III nitride semiconductor structure including a p / n region in which the first 1p semiconductor region and the first 2n semiconductor region exist from one main surface to another main surface, and p / forming a Schottky electrode electrically connected to at least a part of the first 1p semiconductor region and in Schottky contact with the first 2n semiconductor region on one main surface side of the n region.

  In the method of manufacturing a group III nitride semiconductor device according to the present embodiment, a group III nitride semiconductor device having a high breakdown voltage is formed in order to form a super junction structure formed by the first 1p semiconductor region and the first 2n semiconductor region. Can be obtained.

  In the method for manufacturing a group III nitride semiconductor device according to the present embodiment, the group III nitride semiconductor structure is disposed on the other main surface side of the p / n region and is disposed in contact with the first 1p semiconductor region. A second 1n semiconductor region having a crystal orientation of 1 and an n-type conductivity, in contact with the first 2n semiconductor region, and between and adjacent to the second 1n semiconductor region And a second 2n semiconductor region having a second crystal orientation and an n-type conductivity, wherein the second 1n semiconductor region exists from one main surface to another main surface and The 2n semiconductor region of 2 may further include an n / n region existing on at least one main surface side. Such a method for manufacturing a group III nitride semiconductor device forms a super junction structure formed by a first 1p semiconductor region, a first 2n semiconductor region, a second 2n semiconductor region, and a second 1n semiconductor region. Therefore, a group III nitride semiconductor device having a high breakdown voltage can be obtained.

  Here, the step of forming the group III nitride semiconductor structure is arranged on the substrate between the second 1n semiconductor region and the second 1n semiconductor region and adjacent to the second 1n semiconductor region. N / n in which the second 1n semiconductor region exists from one main surface to another main surface and the second 2n semiconductor region exists at least on the one main surface side. An n / n region forming sub-process for forming a region, a first 1p semiconductor region disposed on one main surface side of the n / n region in contact with the second 1n semiconductor region, and a second 2n semiconductor region And a first 2n semiconductor region disposed between and adjacent to the first 1p semiconductor region, the first 1p semiconductor region and the first 1p semiconductor region Forming a p / n region in which the 2n semiconductor region exists from one main surface to another main surface / A n region forming substep may include. Thereby, a super junction structure formed by the first 1p semiconductor region, the first 2n semiconductor region, the second 2n semiconductor region, and the second 1n semiconductor region can be efficiently formed.

  In the group III nitride semiconductor device manufacturing method of the present embodiment, in the step of forming the group III nitride semiconductor structure, oxygen is incorporated into the group III nitride semiconductor structure, and the second crystal orientation is Compared with the crystal orientation of 1, the oxygen uptake in the group III nitride semiconductor structure can be increased. Such a Group III nitride semiconductor device manufacturing method obtains a Group III nitride semiconductor device having a high breakdown voltage, which forms a super junction structure formed of at least a first 1p semiconductor region and a first 2n semiconductor region. Can do.

  The method for manufacturing a group III nitride semiconductor device of this embodiment may further include a step of forming a mask on a part of the substrate before the step of forming the group III nitride semiconductor structure. In such a method of manufacturing a group III nitride semiconductor device, a super junction structure formed of at least a first 1p semiconductor region and a first 2n semiconductor region is formed by forming a mask on a part of a substrate. Since it can be formed efficiently, a Group III nitride semiconductor device with a high breakdown voltage can be obtained.

  In the group III nitride semiconductor device manufacturing method of the present embodiment, the substrate can be a conductive substrate. In such a method for manufacturing a group III nitride semiconductor device, a group III nitride semiconductor device 2 in which an increase in on-resistance is suppressed can be obtained by using a conductive substrate as the substrate.

<Details of Embodiment of the Present Invention>
The group III nitride semiconductor device 2 described in FIGS. 1 to 6 does not reflect actual dimensions, but from the viewpoint of displaying the structure in an easy-to-understand manner, the substrate 1, the bonding substrate 1B, and the composite substrate 1C (supports) Compared to the thickness of the substrate 11, the bonding film 12 and the conductive film 10f) and the conductive substrate 10, the group III nitride semiconductor structure 20 (first 1p semiconductor region 21ap, first 2n semiconductor region 21bn, second 2 1n semiconductor region 22an and second 2n semiconductor region 22bn), Schottky electrode 30 and ohmic electrode 40 are greatly emphasized.

[Embodiment 1: Group III nitride semiconductor device]
With reference to FIGS. 1-5, the group III nitride semiconductor device 2 of this embodiment is a group III nitride semiconductor structure 20 having a plurality of first crystal orientations and a p-type conductivity type. A second crystal orientation different from the first crystal orientation disposed between the first 1p semiconductor region 21ap and the first 1p semiconductor region 21ap and adjacent to the first 1p semiconductor region 21ap, and n-type conductivity P / n region in which the first 1p semiconductor region 21ap and the first 2n semiconductor region 21bn exist from one main surface 21m to another main surface 21n. 21 pn, disposed on one main surface 21 m side of the p / n region 21 pn, electrically connected to at least a part of the first 1p semiconductor region 21 ap and in Schottky contact with the first 2n semiconductor region 21 bn. Further comprising a hotkey electrode.

  Since the group III nitride semiconductor device 2 of this embodiment includes a super junction structure formed by the first 1p semiconductor region 21ap and the first 2n semiconductor region 21bn, the breakdown voltage can be increased.

Here, the p-type carrier concentration of the first 1p semiconductor region 21ap (referred to as the concentration obtained by subtracting the donor concentration from the acceptor concentration, hereinafter the same) is not particularly limited, but from the viewpoint of forming an appropriate depletion layer, it is 1 X10 ¹⁶ m ⁻³ or more and 3 × 10 ¹⁷ cm ⁻³ or less is preferable, and 5 × 10 ¹⁶ m ⁻³ or more and 1 × 10 ¹⁷ cm ⁻³ or less is more preferable. Further, the n-type carrier concentration of the first 2n semiconductor region 21bn (referred to as the concentration obtained by subtracting the acceptor concentration from the donor concentration, the same shall apply hereinafter) is not particularly limited. 1 × 10 ¹⁵ cm ⁻³ or more and 1 × 10 ¹⁶ cm ⁻³ or less is preferable and 4 × 10 ¹⁵ cm ⁻³ or more and 8 × 10 ¹⁵ cm ⁻³ or less is more preferable from the viewpoint of lowering the on-resistance of the physical semiconductor device. . The Schottky electrode 30 is not particularly limited as long as it is electrically connected to at least a part of the first 1p semiconductor region 21ap and is in Schottky contact with the first 2n semiconductor region 21bn. A Ni / Au electrode etc. are mentioned.

  3 to 5, in group III nitride semiconductor device 2 of the present embodiment, group III nitride semiconductor structure 20 is arranged on the other main surface 21n side of p / n region 21pn, and A second 1n semiconductor region 22an having a first crystal orientation and an n-type conductivity type disposed in contact with one 1p semiconductor region 21ap; and a second 1n semiconductor region 21bn in contact with the first 2n semiconductor region 21bn. A second 2n semiconductor region 22bn having a second crystal orientation and an n-type conductivity type disposed between and adjacent to the second 1n semiconductor region 22an; The n / n region 22nn can be further included in which the 1n semiconductor region 22an exists from one main surface 22m to the other main surface 22n and the second 2n semiconductor region 22bn exists at least on the one main surface 22m side. The group III nitride semiconductor device 2 has a super junction structure formed by a first 1p semiconductor region 21ap, a first 2n semiconductor region 21bn, a second 2n semiconductor region 22bn, and a second 1n semiconductor region 22an. Therefore, the breakdown voltage can be increased.

Here, the n-type carrier concentration of the second 1n semiconductor region 21an (referred to as the concentration obtained by subtracting the acceptor concentration from the donor concentration, the same shall apply hereinafter) is not particularly limited, but is compatible with both high breakdown voltage and low on-resistance. From the viewpoint, 5 × 10 ¹⁷ cm ⁻³ or more and 5 × 10 ¹⁸ cm ⁻³ or less is preferable, and 1 × 10 ¹⁸ cm ⁻³ or more and 3 × 10 ¹⁸ cm ⁻³ or less is more preferable. Further, the n-type carrier concentration of the second 2n semiconductor region 22bn (referred to as the concentration obtained by subtracting the acceptor concentration from the donor concentration, the same shall apply hereinafter) is not particularly limited. From 5 × 10 ¹⁷ cm ^{−3 to} 5 × 10 ¹⁸ cm ⁻³ is preferable, and from 1 × 10 ¹⁸ cm ^{−3 to} 3 × 10 ¹⁸ cm ⁻³ is more preferable.

  Referring to FIGS. 2, 4, and 5, the group III nitride semiconductor device of this embodiment can further include a conductive substrate 10. Since the group III nitride semiconductor device 2 includes the conductive substrate 10, an increase in on-resistance can be suppressed.

Referring to FIG. 5, group III nitride semiconductor device 2 of the present embodiment may further include a mask 15 disposed on a part of conductive substrate 10. Since the group III nitride semiconductor device 2 includes the mask 15 disposed on a part of the conductive substrate 10, the first 1p semiconductor region 21ap, the first 2n semiconductor region 21bn, and the second A super junction structure formed by the 2n semiconductor region 22bn and the second 1n semiconductor region 22an is efficiently formed. The mask 15 is not particularly limited, but is preferably formed of SiO ₂ , SiN _x or the like from the viewpoint of forming the second 2n semiconductor region 22bn thereon.

  1 to 5, in the group III nitride semiconductor device 2 of the present embodiment, the second crystal orientation is oxygen in the group III nitride semiconductor structure 20 as compared to the first crystal orientation. Can be increased. In such a group III nitride semiconductor device 2, since the second crystal orientation has a larger oxygen uptake in the group III nitride semiconductor structure 20 than the first crystal orientation, at least the first 1p semiconductor region 21 ap and the second crystal orientation The super junction structure formed with one 2n semiconductor region 21bn can be included, and the breakdown voltage can be increased.

Referring to FIGS. 1 to 5, in group III nitride semiconductor device 2 of the present embodiment, width Wn of first 2n semiconductor region 21bn viewed from the one main surface 21m side maintains a reverse breakdown voltage. From the viewpoint of forming the depletion layer without gaps, it is preferably not more than twice the maximum depletion layer width Xn _max of the first 2n semiconductor region 21bn defined by the following formula (1).

In equation (1), ε is the dielectric constant of the group III nitride semiconductor, q is the elementary charge, N _a is the acceptor concentration of the first 1p semiconductor region 21ap, and N _d is the donor concentration of the first 2n semiconductor region 21bn. , Φ _B is a built-in potential, and V _b is a maximum voltage to be applied.

  1 to 5, in the group III nitride semiconductor device 2 of the present embodiment, the thickness Tp of the first 1p semiconductor region 21ap is equal to the first 1p semiconductor region 21ap. From the viewpoint of obtaining the effect of expanding the depletion layer of the 2n semiconductor region 21bn, the depletion layer width Xn of the first 2n semiconductor region 21bn by the Schottky electrode 30 defined by the following formula (2) is preferable.

In Equation (2), ε is the dielectric constant of the group III nitride semiconductor, q is the elementary charge, N _d is the donor concentration of the first 2n semiconductor region 21bn, Φ _B is the built-in potential, and V _b is the maximum voltage to be applied. It is.

  1 to 5, in the group III nitride semiconductor device 2 of the present embodiment, the first crystal orientation is not particularly limited, but the first 1p semiconductor region 21ap and the second 1n semiconductor region are not limited. From the viewpoint of improving the quality of 22an, it is in the [0001] direction (c-axis direction), that is, one main surface 21m of the first 1p semiconductor region 21ap and one main surface 22m of the second 1n semiconductor region 22an are ( (0001) plane (c-plane). The second crystal orientation is not particularly limited as long as the second crystal orientation is different from the first crystal orientation, but the first 2n semiconductor region 21bn having high quality together with the first 1p semiconductor region 21ap and the second 1n semiconductor region 22an. From the viewpoint of obtaining the second 2n semiconductor region 22bn, it is in the [000-1] direction (-c-axis direction), that is, one main surface 21m of the first 2n semiconductor region 21bn and the second 2n semiconductor region 22bn. Is preferably (000-1) plane (-c plane).

  1 to 5, the group III nitride semiconductor device 2 of the present embodiment is in ohmic contact with at least the first 2n semiconductor region 21bn or the second 2n semiconductor region 22bn from the viewpoint of reducing the on-resistance. Alternatively, it is preferable to include an ohmic electrode 40 that is in ohmic contact with the conductive substrate 10 that is electrically connected to at least one of the second 2n semiconductor region 22bn and the second 1n semiconductor region 22an. The ohmic electrode 40 is not particularly limited as long as it is in ohmic contact with the first 2n semiconductor region 21bn, the second 2n semiconductor region 22bn, or the conductive substrate 10. The Ti electrode, Al electrode, Ti / Pt / Al electrode Al / Ti / Au electrodes, Ti / Al / Ti / Au electrodes, and the like.

(First example)
Referring to FIG. 1, a first example of a group III nitride semiconductor device 2 of the present embodiment includes a plurality of group III nitride semiconductor structures 20 having a first crystal orientation and a p-type conductivity type. A second crystal orientation different from the first crystal orientation disposed between the first 1p semiconductor region 21ap and the first 1p semiconductor region 21ap and adjacent to the first 1p semiconductor region 21ap; P / n including a first 2n semiconductor region 21bn having a conductivity type, wherein the first 1p semiconductor region 21ap and the first 2n semiconductor region 21b exist from one main surface 21m to another main surface 21n. Region 21pn is included.

  The group III nitride semiconductor device 2 of the first example is further arranged on the one main surface 21m side of the p / n region 21pn and is electrically connected to at least a part of the first 1p semiconductor region 21ap. Schottky electrode 30 in Schottky contact with the 2n semiconductor region 21bn, and the first 2n semiconductor disposed on the other main surface 21n side of the p / n region 21pn and electrically connected to the first 1p semiconductor region 21ap And an ohmic electrode 40 in ohmic contact with the region 21bn.

(Second example)
Referring to FIG. 2, a second example of group III nitride semiconductor device 2 of the present embodiment includes a plurality of group III nitride semiconductor structures 20 having a first crystal orientation and a p-type conductivity type. A second crystal orientation different from the first crystal orientation disposed between the first 1p semiconductor region 21ap and the first 1p semiconductor region 21ap and adjacent to the first 1p semiconductor region 21ap; P / n including a first 2n semiconductor region 21bn having a conductivity type, wherein the first 1p semiconductor region 21ap and the first 2n semiconductor region 21b exist from one main surface 21m to another main surface 21n. Region 21pn is included.

  The group III nitride semiconductor device 2 of the second example is also arranged on the other main surface 21n side of the p / n region 21pn and is electrically connected to the first 1p semiconductor region 21ap and the first 2n semiconductor region 21bn. A conductive substrate 10 is included. The group III nitride semiconductor device 2 of the second example is further arranged on the one main surface 21m side of the p / n region 21pn, and is electrically connected to at least a part of the first 1p semiconductor region 21ap. The Schottky electrode 30 that is in Schottky contact with the 2n semiconductor region 21bn and the ohmic electrode 40 that is in ohmic contact with the conductive substrate 10 are included.

  Referring to FIGS. 1 and 2, group III nitride semiconductor device 2 of the first and second examples includes first 1p semiconductor region 21ap and first 2n semiconductor located in p / n region 21pn. Since the super junction structure formed by the region 21bn is included, the breakdown voltage can be increased.

(Third example)
Referring to FIG. 3, a third example of group III nitride semiconductor device 2 of the present embodiment includes a plurality of group III nitride semiconductor structures 20 having a first crystal orientation and a p-type conductivity type. A second crystal orientation different from the first crystal orientation disposed between the first 1p semiconductor region 21ap and the first 1p semiconductor region 21ap and adjacent to the first 1p semiconductor region 21ap; P / n region including a first 2n semiconductor region 21bn having a conductivity type, wherein the first 1p semiconductor region 21ap and the first 2n semiconductor region 21bn exist from one main surface 21m to another main surface 21n. 21pn and a second 1n semiconductor which is arranged on the other main surface 21n side of p / n region 21pn and has a first crystal orientation and an n-type conductivity type arranged in contact with first 1p semiconductor region 21ap Region 22an and the first a second crystal orientation arranged in contact with n semiconductor region 21bn, between second 1n semiconductor region 22an and adjacent to second 1n semiconductor region 22an and having an n-type conductivity type; 2n semiconductor region 22bn, and n / n region 22nn in which the second 1n semiconductor region 22an and the second 2n semiconductor region 22bn exist from one main surface 22m to another main surface 22n.

  The group III nitride semiconductor device 2 of the third example is further arranged on the one main surface 21m side of the p / n region 21pn, and is electrically connected to at least a part of the first 1p semiconductor region 21ap. Schottky electrode 30 that is in Schottky contact with the 2n semiconductor region 21bn and ohmic contact with the second 1n semiconductor region 22an and the second 2n semiconductor region 22bn disposed on the other main surface 22n side of the n / n region 22nn. And an ohmic electrode 40.

(Fourth example)
Referring to FIG. 4, a fourth example of group III nitride semiconductor device 2 of the present embodiment includes a plurality of group III nitride semiconductor structures 20 having a first crystal orientation and a p-type conductivity type. A second crystal orientation different from the first crystal orientation disposed between the first 1p semiconductor region 21ap and the first 1p semiconductor region 21ap and adjacent to the first 1p semiconductor region 21ap; P / n region including a first 2n semiconductor region 21bn having a conductivity type, wherein the first 1p semiconductor region 21ap and the first 2n semiconductor region 21bn exist from one main surface 21m to another main surface 21n. 21pn and a second 1n semiconductor which is arranged on the other main surface 21n side of p / n region 21pn and has a first crystal orientation and an n-type conductivity type arranged in contact with first 1p semiconductor region 21ap Region 22an and the first a second crystal orientation arranged in contact with n semiconductor region 21bn, between second 1n semiconductor region 22an and adjacent to second 1n semiconductor region 22an and having an n-type conductivity type; 2n semiconductor region 22bn, and n / n region 22nn in which the second 1n semiconductor region 22an and the second 2n semiconductor region 22bn exist from one main surface 22m to another main surface 22n.

  The group III nitride semiconductor device 2 of the fourth example is also disposed on the other main surface 22n side of the n / n region 22nn and is electrically connected to the second 1n semiconductor region 22an and the second 2n semiconductor region 22bn. A conductive substrate 10 is included. The group III nitride semiconductor device 2 of the fourth example is further arranged on the one main surface 21m side of the p / n region 21pn, and is electrically connected to at least a part of the first 1p semiconductor region 21ap and the first The Schottky electrode 30 that is in Schottky contact with the 2n semiconductor region 21bn and the ohmic electrode 40 that is in ohmic contact with the conductive substrate 10 are included.

(Fifth example)
Referring to FIG. 5, a fifth example of group III nitride semiconductor device 2 of the present embodiment includes a plurality of group III nitride semiconductor structures 20 having a first crystal orientation and a p-type conductivity type. A second crystal orientation different from the first crystal orientation disposed between the first 1p semiconductor region 21ap and the first 1p semiconductor region 21ap and adjacent to the first 1p semiconductor region 21ap; P / n region including a first 2n semiconductor region 21bn having a conductivity type, wherein the first 1p semiconductor region 21ap and the first 2n semiconductor region 21bn exist from one main surface 21m to another main surface 21n. 21pn and a second 1n having a first crystal orientation and an n-type conductivity type arranged on the other main surface 21n side of the p / n region 21pn and in contact with the first 1p semiconductor region 21ap Semiconductor region 22an and first A second crystal orientation and an n-type conductivity type disposed in contact with and adjacent to the 2n semiconductor region 21bn and between the second 1n semiconductor region 22an and adjacent to the second 1n semiconductor region 22an; A 2n semiconductor region 22bn and a mask 15 disposed in contact with the second 2n semiconductor region 22bn and between the second 1n semiconductor region 22an and adjacent to the second 1n semiconductor region 22an. 1n semiconductor region 22an exists from one main surface 22m to another main surface 22n, the second 2n semiconductor region 22bn exists on the one main surface 22m side, and mask 15 exists on the other main surface 22n side. / N region 22nn.

  The group III nitride semiconductor device 2 of the fifth example also includes a conductive substrate 10 disposed on the other main surface 22n side of the n / n region 22nn and electrically connected to the second 1n semiconductor region 22an. The group III nitride semiconductor device 2 of the fifth example is further arranged on the one main surface 21m side of the p / n region 21pn and is electrically connected to at least a part of the first 1p semiconductor region 21ap. The Schottky electrode 30 that is in Schottky contact with the 2n semiconductor region 21bn and the ohmic electrode 40 that is in ohmic contact with the conductive substrate 10 are included.

  Referring to FIGS. 3 to 5, group III nitride semiconductor device 2 of the third to fifth examples includes first 1p semiconductor region 21 ap and first 2n semiconductor located in p / n region 21 pn. Since the super junction structure is formed by the region 21bn, the second 2n semiconductor region 22bn and the second 1n semiconductor region 22an located in the n / n region 22nn, the breakdown voltage is increased and the on-resistance is further increased. Can be lowered.

[Embodiment 2: Manufacturing Method of Group III Nitride Semiconductor Device]
Referring to FIG. 6, in the method for manufacturing a group III nitride semiconductor device of the present embodiment, a plurality of first 1p semiconductor regions 21ap having a first crystal orientation and a p-type conductivity type are formed on substrate 1. And a second crystal orientation different from the first crystal orientation disposed between and adjacent to the first 1p semiconductor region 21ap and an n-type conductivity type. 2n semiconductor region 21bn, and the first 1p semiconductor region 21ap and the first 2n semiconductor region 21bn include a p / n region 21pn that extends from one main surface 21m to another main surface 21n. And the first 1p semiconductor region of the group III nitride semiconductor structure 20 on the one main surface 21m side of the p / n region 21pn, and the step of forming the compound semiconductor structure 20 (FIGS. 6B to 6C) Electricity for at least part of 21ap Forming was and the Schottky electrode 30 to the Schottky contact with the first 2n semiconductor region 21bn connected includes (FIG 6 (D)), a.

  The manufacturing method of the group III nitride semiconductor device 2 of the present embodiment forms a super junction structure formed by the first 1p semiconductor region and the first 2n semiconductor region, so that the group III nitride semiconductor device has a high breakdown voltage. Can be obtained.

  In the method for manufacturing the group III nitride semiconductor device 2 according to the present embodiment, the group III nitride semiconductor structure 20 is disposed on the other main surface 21n side of the p / n region 21pn as shown in FIG. 6C. The second 1n semiconductor region 22an having the first crystal orientation and the n-type conductivity type disposed in contact with the first 1p semiconductor region 21ap, the first 2n semiconductor region 21bn and the second 1n semiconductor region 21bn A second 2n semiconductor region 22bn having a second crystal orientation and an n-type conductivity type disposed between and adjacent to the second 1n semiconductor region 22an, The second 1n semiconductor region 22an further includes an n / n region 22n that exists from one main surface 22m to another main surface 22n, and the second 2n semiconductor region 22bn exists at least on the one main surface 22m side. Kill. The manufacturing method of such a group III nitride semiconductor device 2 is a supermarket formed by a first 1p semiconductor region 21ap, a first 2n semiconductor region 21bn, a second 2n semiconductor region 22bn, and a second 1n semiconductor region 22an. Since the junction structure is formed, a group III nitride semiconductor device having a high breakdown voltage can be obtained.

  Here, referring to FIGS. 6B and 6C, the step of forming group III nitride semiconductor structure 20 includes forming second 1n semiconductor region 22an and second 1n semiconductor on substrate 1. A second 2n semiconductor region 22bn disposed between and adjacent to the second 1n semiconductor region 22an, and the second 1n semiconductor region 22an is changed from one main surface 22m to another main surface 22n. An n / n region formation sub-process (FIG. 6B) for forming an n / n region 22nn that exists over at least one main surface 22m, and the second 2n semiconductor region 22bn exists, The first 1p semiconductor region 21ap disposed in contact with the second 1n semiconductor region 22an and the first first 1p semiconductor in contact with the second 2n semiconductor region 22bn on one main surface 22m side of 22nn During the region 21ap A first 2n semiconductor region 21bn disposed adjacent to the first 1p semiconductor region 21ap, and the first 1p semiconductor region 21ap and the first 2n semiconductor region 21bn are separated from one main surface 21m to another main surface. And a p / n region forming sub-process (FIG. 6C) for forming a p / n region 21pn existing over 21n. As a result, a super junction structure formed by the first 1p semiconductor region 21ap, the first 2n semiconductor region 21bn, the second 2n semiconductor region 22bn, and the second 1n semiconductor region 22an can be efficiently formed. .

  Referring to FIG. 6, in the method of manufacturing group III nitride semiconductor device 2 of this embodiment, oxygen is taken into group III nitride semiconductor structure 20 in the step of forming group III nitride semiconductor structure 20. In addition, the second crystal orientation can increase oxygen uptake in the group III nitride semiconductor structure 20 as compared with the first crystal orientation. The manufacturing method of the group III nitride semiconductor device 2 includes a group III nitride semiconductor device having a high breakdown voltage that forms a super junction structure formed of at least the first 1p semiconductor region 21ap and the first 2n semiconductor region 21bn. 2 can be obtained.

  Referring to FIG. 6, in the method of manufacturing group III nitride semiconductor device 2 of the present embodiment, before the step of forming group III nitride semiconductor structure 20 (FIGS. 6B and 6C). The method may further include a step of forming the mask 15 on a part of the substrate 1 (FIG. 6A). In the method of manufacturing the group III nitride semiconductor device 2, the mask 15 is formed on a part of the substrate 1 to form at least the first 1p semiconductor region 21ap and the first 2n semiconductor region 21bn. Therefore, the group III nitride semiconductor device 2 having a high breakdown voltage can be obtained.

  Referring to FIG. 6, in the method for manufacturing group III nitride semiconductor device 2 of this embodiment, substrate 1 can be a conductive substrate. Such a method for manufacturing a group III nitride semiconductor device 2 can obtain a group III nitride semiconductor device 2 in which an increase in on-resistance is suppressed by using the substrate 1 as a conductive substrate.

  Here, the method of forming the group III nitride semiconductor structure 20, that is, the first 1p semiconductor region 21ap, the first 2n semiconductor region 21bn, the second 1n semiconductor region 22an, and the second 2n semiconductor region 22bn, Although there is no particular limitation, from the viewpoint of forming a high-quality group III nitride semiconductor structure 20, MOVPE (metal organic chemical vapor deposition) method, MBE (molecular beam growth) method and the like are preferable. The method for forming the Schottky electrode 30 is not particularly limited, and EB (electron beam) vapor deposition, resistance heating vapor deposition, and sputtering are preferable. The method for forming the ohmic electrode 40 is not particularly limited, and EB (electron beam) vapor deposition, resistance heating vapor deposition, and sputtering are preferable. The method for forming the mask 15 is not particularly limited, but from the viewpoint of forming the high-quality mask 15, a plasma CVD (chemical vapor deposition) method, a resistance heating vapor deposition method, or the like is preferable.

(Method for Producing Group III Nitride Semiconductor Device of Fifth Example)
Referring to FIG. 6, the manufacturing method of group III nitride semiconductor device 2 of the present embodiment is, for example, one main substrate 1 as a manufacturing method of group III nitride semiconductor device 2 of the fifth example of embodiment 1. A step of forming a mask 15 on a part of the surface 1m (FIG. 6A), and a group III nitride semiconductor structure 20 is formed on the main surface 1m of the substrate 1 where the mask 15 is partly formed. A step (FIGS. 6B and 6C), a step of forming the Schottky electrode 30 (FIG. 6D), and a step of forming an ohmic electrode (FIG. 6D).

(Process for forming a mask on a substrate)
First, referring to FIG. 6A, in the step of forming mask 15 on a part of main surface 1m of substrate 1, a SiO ₂ film is grown on substrate 1 by, for example, plasma CVD, A line-shaped resist having a width Wp and a pitch (Wp + Wn) is formed by photolithography, and the SiO ₂ film in a region where the resist is not formed is removed by RIE (reactive ion etching). By removing the resist, a line-shaped mask 15 having a width Wn and a pitch (Wn + Wp) is formed.

(Step of forming group III nitride semiconductor structure)
Next, with reference to FIGS. 6B and 6C, the step of forming group III nitride semiconductor structure 20 on one main surface 1m on which mask 15 of substrate 1 is partially formed includes A plurality of second 1n semiconductor regions 22an having one crystal orientation and n-type conductivity, and a second 1n semiconductor region 22an disposed between and adjacent to the second 1n semiconductor region 22an. A second 2n semiconductor region 22bn having a second crystal orientation different from the crystal orientation of 1 and an n-type conductivity, and the second 1n semiconductor region 22an is changed from one main surface 22m to another main surface 22n. An n / n region formation sub-process (FIG. 6B) for forming an n / n region 22nn that exists over at least one main surface 22m, and the second 2n semiconductor region 22bn exists, A second 1n semiconductor region on one main surface 22m side of 22nn Between the first 1p semiconductor region 21ap having the first crystal orientation and the p-type conductivity disposed in contact with 2an, and between the first 1p semiconductor region 21ap in contact with the second 2n semiconductor region 22bn And a second crystal orientation different from the first crystal orientation disposed adjacent to the first 1p semiconductor region 21ap and a first 2n semiconductor region 21bn having n-type conductivity, P / n region forming sub-process in which the 1p semiconductor region 21ap and the first 2n semiconductor region 21bn form a p / n region 21pn existing from one main surface 21m to another main surface 21n (FIG. 6C) And including.

  Referring to FIG. 6B, in the n / n region forming sub-step, on one main surface 1m (for example, (0001) surface) on which mask 15 of substrate 1 having the first crystal orientation is partially formed. Then, a group III nitride semiconductor is formed by the MOVPE method. Here, in the MOVPE method, by adding an n-type conductive impurity, a first crystal orientation (for example, one principal surface 22m is (0001) on the region where the mask 15 of the one principal surface 1m is not formed). When the second 1n semiconductor region 22an having the n-type conductivity type is formed, a second crystal orientation (for example, different from the first crystal orientation) is formed on the region of the substrate 1 where the mask 15 is formed. A second 2n semiconductor region 22bn having one principal surface 22m ((000-1) plane) and n-type conductivity is formed. Here, the second 2n semiconductor region 22bn is formed on the region of the main surface 1m of the substrate 1 where the mask 15 is formed. The main surface of the second crystal orientation is that of the first crystal orientation. This is probably because oxygen atoms serving as n-type conductive impurities are more easily taken into the semiconductor region than the main surface.

  In this manner, a plurality of second 1n semiconductor regions 22an having the first crystal orientation and n-type conductivity are adjacent to and adjacent to the second 1n semiconductor region 22an. And a second 2n semiconductor region 22bn having a second crystal orientation different from the first crystal orientation and n-type conductivity, and the second 1n semiconductor region 22an is formed from one main surface 22m. An n / n region 22nn is formed which exists over another main surface 22n and in which the second 2n semiconductor region 22bn is present on at least one main surface 22m side.

  Referring to FIG. 6C, in the p / n region forming sub-step, a group III nitride semiconductor is further formed on one main surface 22m of n / n region 22nn by, for example, MOVPE. Here, for example, by adding a p-type conductive impurity in the MOVPE method, a second 1n semiconductor region having a first crystal orientation (for example, one principal surface 22m is a (0001) plane) and an n-type conductivity type. When a first 1p semiconductor region 21ap having a first crystal orientation (for example, one main surface 21m is a (0001) plane) and a p-type conductivity is formed on 22an, a second crystal orientation (for example, one main surface) On the second 2n semiconductor region 22bn having the (000-1) plane) and the n-type conductivity type, the second crystal orientation (for example, one principal plane 21m is the (000-1) plane) and n A first 2n semiconductor region 21bn having a conductive type is formed. Even if the p-type conductive impurity is added, the first 2n semiconductor region 21bn is formed on the second 2n semiconductor region 22bn because the main surface of the second crystal orientation is the first crystal orientation. Compared to the main surface, oxygen atoms serving as n-type conductive impurities are easily taken into the semiconductor region, and an n-type conductive semiconductor region is formed on one main surface 22m of the second 2n semiconductor region 22bn. It is thought to be for this purpose.

  In this manner, the first 1p semiconductor region 21ap disposed in contact with the second 1n semiconductor region 22an and the second 2n semiconductor region 22bn are disposed on the one main surface 22m side of the n / n region 22nn. And a first 2n semiconductor region 21bn disposed between and adjacent to the first 1p semiconductor region 21ap, the first 1p semiconductor region 21ap and the first 1p semiconductor region 21ap A p / n region 21pn in which one 2n semiconductor region 21bn exists from one main surface 21m to another main surface 21n is formed. As described above, group III nitride semiconductor structure 20 including p / n region 21pn and n / n region 22nn is obtained.

(Step of forming Schottky electrode)
6D, in the step of forming Schottky electrode 30, group III nitride semiconductor structure 20 is formed on one main surface 21m side of p / n region 21pn by, for example, EB vapor deposition. A Schottky electrode 30 is formed which is electrically connected to at least part of the first 1p semiconductor region 21ap and is in Schottky contact with the first 2n semiconductor region 21bn.

(Process of forming ohmic electrode)
6D, in the step of forming the ohmic electrode 40, the ohmic electrode that is in ohmic contact with the conductive substrate 10 that is electrically connected to the second 1n semiconductor region 22an, for example, by an EB vapor deposition method. 40 is formed.

  As described above, the Group III nitride semiconductor device 2 of the fifth example of Embodiment 1 as shown in FIG. 5 is obtained.

  7 and 8, the group III nitride semiconductor of the second example and the fourth example of Embodiment 1 is used by using the conductive substrate 10 including the 1n semiconductor region 10an and the 2n semiconductor region 10bn. The device 2 can be manufactured. Further, referring to FIGS. 9 and 10, by using the composite substrate 1C including the conductive film 10f including the 1n semiconductor region 10an and the 2n semiconductor region 10bn, the first example and the third example of the first embodiment are used. The group III nitride semiconductor device 2 can be manufactured. Hereinafter, it demonstrates in order.

(Method of manufacturing conductive substrate including 1n semiconductor region and 2n semiconductor region)
Referring to FIG. 7, a method for manufacturing conductive substrate 10 including 1n semiconductor region 10an and 2n semiconductor region 10bn includes a step of forming mask 15 on substrate 1 (FIG. 7A), and a conductive body. A step of forming 10D (FIG. 7B) and a step of forming the conductive substrate 10 (FIG. 7C).

  First, referring to FIG. 7A, the step of forming mask 15 on substrate 1 is performed on one main surface 1m of substrate 1 in the method of manufacturing a group III nitride semiconductor device of the fifth example. This is the same as the step of forming the mask 15 on the part (FIG. 6A).

  Next, referring to FIG. 7B, in the step of forming the conductive body 10D, an HVPE (hydride vapor phase epitaxy) method is performed on one main surface 1m where the mask 15 is formed on a part of the substrate 1. Thus, a group III nitride semiconductor is formed. Here, in the HVPE method, by adding an n-type conductive impurity, a first crystal orientation (for example, one main surface 10m is (0001) on the region where the mask 15 of the one main surface 1m is not formed). When the 1n semiconductor region 10an having the n-type conductivity type is formed, a second crystal orientation (for example, one main surface) different from the first crystal orientation is formed on the region of the substrate 1 where the mask 15 is formed. A 2n semiconductor region 10bn having 10m (000-1) plane) and n-type conductivity is formed.

  In this way, the plurality of 1n semiconductor regions 10an having the first crystal orientation and n-type conductivity, and the first crystal disposed between and adjacent to the 1n semiconductor region 10an. 2n semiconductor region 10bn having a second crystal orientation different from the orientation and n-type conductivity, 1n semiconductor region 10an exists from one main surface 10m to another main surface 10n, and 2n semiconductor region 10bn Conductive body 10D present on at least one principal surface 10m side is obtained.

  Next, referring to FIGS. 7B and 7C, in the step of forming the conductive substrate 10, the conductive body 10D is cut out so as not to include the mask 15 in parallel to the one main surface 10m. The main surface 10m and the other main surface 10n are flattened. In this way, the plurality of 1n semiconductor regions 10an having the first crystal orientation and n-type conductivity, and the first crystal disposed between and adjacent to the 1n semiconductor region 10an. Including a 2n semiconductor region 10bn having a second crystal orientation different from the orientation and n-type conductivity, wherein the 1n semiconductor region 10an and the 2n semiconductor region 10bn exist from one main surface 10m to another main surface 10n. The conductive substrate 10 is obtained.

(Method for Producing Group III Nitride Semiconductor Device of Second Example)
Referring to FIG. 8, in the second example of the Group III nitride semiconductor device 2 of Embodiment 1, the method for preparing the conductive substrate 10 including the 1n semiconductor region 10an and the 2n semiconductor region 10bn is prepared (FIG. 8). (A)), the step of forming the group III nitride semiconductor structure 20 (FIG. 8B), the step of forming the Schottky electrode 30 (FIG. 8C), and the step of forming the ohmic electrode (FIG. 8C).

  Referring to FIG. 8A, the step of preparing the conductive substrate 10 including the 1n semiconductor region 10an and the 2n semiconductor region 10bn includes the above-described conductive substrate 10 including the 1n semiconductor region 10an and the 2n semiconductor region 10bn. This is the same as the manufacturing method (FIGS. 7A to 7C).

  Referring to FIG. 8B, in the step of forming group III nitride semiconductor structure 20, group III nitride semiconductor is formed on one main surface 10m of conductive substrate 10 by, for example, MOVPE. Here, for example, by adding a p-type conductive impurity in the MOVPE method, the 1n semiconductor region 10an having the first crystal orientation (for example, one principal surface 10m is the (0001) plane) and the n-type conductivity type is formed. When the first 1p semiconductor region 21ap having the first crystal orientation (for example, one principal surface 21m is the (0001) plane) and the p-type conductivity is formed, the second crystal orientation (for example, one principal surface 10m is On the 2n semiconductor region 10bn having the (000-1) plane) and the n-type conductivity type, the second crystal orientation (for example, one main surface 21m is the (000-1) plane) and the n-type conductivity type A first 2n semiconductor region 21bn is formed.

  In this manner, the first 1p semiconductor region 21ap disposed in contact with the 1n semiconductor region 10an and the 2n semiconductor region 10bn on the main surface 10m side of the conductive substrate 10 and the first first surface A first 2n semiconductor region 21bn disposed between and adjacent to the first 1p semiconductor region 21ap, and the first 1p semiconductor region 21ap and the first 2n semiconductor region 21bn Group III nitride semiconductor structure 20 including p / n region 21pn existing from one main surface 21m to another main surface 21n is obtained.

  Next, referring to FIG. 8C, the step of forming Schottky electrode 30 is the same as the step of forming Schottky electrode 30 in the method of manufacturing the group III nitride semiconductor device of the fifth example. is there. The step of forming the ohmic electrode 40 is the same as the step of forming the ohmic electrode 40 in the method of manufacturing the group III nitride semiconductor device of the fifth example.

  As described above, the Group III nitride semiconductor device 2 of the second example of Embodiment 1 as shown in FIG. 2 is obtained.

(Method for Manufacturing Group III Nitride Semiconductor Device of Fourth Example)
Referring to FIG. 8, in the fourth example of the Group III nitride semiconductor device 2 of the first embodiment, the method for preparing the conductive substrate 10 including the 1n semiconductor region 10an and the 2n semiconductor region 10bn (see FIG. 8). (A)), a step of forming group III nitride semiconductor structure 20 (FIGS. 8D and 8E), a step of forming Schottky electrode 30 (FIG. 8F), and an ohmic electrode Forming the step (FIG. 8F).

  Referring to FIG. 8A, the step of preparing the conductive substrate 10 including the 1n semiconductor region 10an and the 2n semiconductor region 10bn includes the above-described conductive substrate 10 including the 1n semiconductor region 10an and the 2n semiconductor region 10bn. This is the same as the manufacturing method (FIGS. 7A to 7C).

  Referring to FIG. 8D, in the step of forming group III nitride semiconductor structure 20, a group III nitride semiconductor is formed on one main surface 10m of conductive substrate 10 by, for example, MOVPE. Here, for example, by adding an n-type conductive impurity in the MOVPE method, on the 1n semiconductor region 10an having the first crystal orientation (for example, one principal surface 10m is the (0001) plane) and the n-type conductivity type. When the second 1n semiconductor region 22an having the first crystal orientation (for example, one principal surface 22m is the (0001) surface) and the n-type conductivity is formed, the second crystal orientation (for example, one principal surface 10m is (000-1) plane) and a second crystal orientation different from the first crystal orientation (for example, one principal surface 22m is the (000-1) plane) on the 2n semiconductor region 10bn having the n-type conductivity type. A second 2n semiconductor region 22bn having n-type conductivity is formed.

  In this manner, a plurality of second 1n semiconductor regions 22an having the first crystal orientation and n-type conductivity are adjacent to and adjacent to the second 1n semiconductor region 22an. And a second 2n semiconductor region 22bn having a second crystal orientation different from the first crystal orientation and n-type conductivity, the second 1n semiconductor region 22an and the second 2n semiconductor An n / n region 22nn in which a region exists from one main surface 22m to another main surface 22n is formed.

  Referring to FIG. 8E, in the step of forming group III nitride semiconductor structure 20, a group III nitride semiconductor is further formed on one main surface 22m of n / n region 22nn by, for example, MOVPE. To do. Here, for example, by adding a p-type conductive impurity in the MOVPE method, a second 1n semiconductor region having a first crystal orientation (for example, one principal surface 22m is a (0001) plane) and an n-type conductivity type. When a first 1p semiconductor region 21ap having a first crystal orientation (for example, one main surface 21m is a (0001) plane) and a p-type conductivity is formed on 22an, a second crystal orientation (for example, one main surface) On the second 2n semiconductor region 22bn having the (000-1) plane) and the n-type conductivity type, the second crystal orientation (for example, one principal plane 21m is the (000-1) plane) and n A first 2n semiconductor region 21bn having a conductive type is formed.

  In this manner, the first 1p semiconductor region 21ap disposed in contact with the second 1n semiconductor region 22an and the second 2n semiconductor region 22bn are disposed on the one main surface 22m side of the n / n region 22nn. And a first 2n semiconductor region 21bn disposed between and adjacent to the first 1p semiconductor region 21ap, the first 1p semiconductor region 21ap and the first 1p semiconductor region 21ap A p / n region 21pn in which one 2n semiconductor region 21bn exists from one main surface 21m to another main surface 21n is formed. As described above, group III nitride semiconductor structure 20 including p / n region 21pn and n / n region 22nn is obtained.

  Next, referring to FIG. 8F, the step of forming Schottky electrode 30 is the same as the step of forming Schottky electrode 30 in the method of manufacturing the group III nitride semiconductor device of the fifth example. is there. The step of forming the ohmic electrode 40 is the same as the step of forming the ohmic electrode 40 in the method of manufacturing the group III nitride semiconductor device of the fifth example.

  As described above, the Group III nitride semiconductor device 2 of the fourth example of Embodiment 1 as shown in FIG. 4 is obtained.

(Manufacturing method of composite substrate including conductive film including 1n semiconductor region and 2n semiconductor region)
Referring to FIG. 9, in the method of manufacturing composite substrate 1C including conductive film 10f including 1n semiconductor region 10an and 2n semiconductor region 10bn, a step of forming bonding film 12a on the main surface of support substrate 11 (FIG. 9 (A)), the bonding film 12b is formed on the main surface of the conductive substrate 10 including the 1n semiconductor region 10an and the 2n semiconductor region 10bn, and the inside of the conductive substrate 10 from the main surface side where the bonding film 12 is formed. The step of forming the ion implantation region 10i at a predetermined depth (FIG. 9B) and the step of forming the bonding substrate 1B by bonding the bonding film 12a and the bonding film 12b (FIG. 9C). And a step of forming the composite substrate 1C including the conductive film 10f by separating the conductive substrate 10 at the ion implantation region 10i (FIG. 9D).

First, referring to FIG. 9A, in the step of forming the bonding film 12a on the main surface (one main surface 11m) of the support substrate 11, the CVD (chemical vapor) is formed on the one main surface 11m of the support substrate 11. The bonding film 12a is formed by a phase deposition method, a sputtering method, or the like. The support substrate 11 is not particularly limited, and examples thereof include a silicon oxide substrate such as a SiO ₂ substrate, a metal oxide substrate such as a sapphire substrate, a composite oxide substrate such as a mullite substrate, and a metal substrate such as a molybdenum substrate. The bonding film 12a is not particularly limited, and examples thereof include a SiO ₂ film and a SiN _x film.

  9B, the step of forming the bonding film 12b on the main surface (another main surface 10n) of the conductive substrate 10 including the 1n semiconductor region 10an and the 2n semiconductor region 10bn includes the above-described bonding. This is the same as the step of forming the film 12a. Further, the step of forming the ion implantation region 10 i at a predetermined depth in the conductive substrate 10 from the main surface (another main surface 10 n) side on which the bonding film 12 is formed includes the other main surface on which the bonding film 12 is formed. This is done by implanting ions I from the 10n side. The ions I to be implanted are not particularly limited, but hydrogen ions, helium ions and the like having a small mass are preferable from the viewpoint of suppressing deterioration in the quality of the conductive substrate 10. The ion-implanted region 10i becomes brittle as compared to other regions by ion implantation. Here, any of the steps shown in FIGS. 9A and 9B may be performed first.

  Next, referring to FIG. 9C, the step of forming the bonding substrate 1B is performed by bonding the bonding film 12a and the bonding film 12b. The bonding film 12a and the bonding film 12b are integrated by bonding to form the bonding film 12, and the bonding substrate 1B in which the support substrate 11 and the conductive substrate 10 are bonded with the bonding film 12 interposed therebetween is obtained.

  Next, referring to FIG. 9D, the step of forming composite substrate 1C is performed by separating conductive substrate 10 of bonding substrate 1B by ion implantation region 10i. The conductive substrate 10 of the bonding substrate 1B is separated into the conductive film 10f bonded to the bonding film 12 and the remaining conductive substrate 10r in the ion implantation region 10i, thereby being electrically conductive with the support substrate 11. Thus, the composite substrate 1C bonded to the conductive film 10f with the bonding film 12 interposed therebetween is obtained. The conductive film 10f of the obtained composite substrate 1C has a 1n semiconductor region that exists from one main surface 10m to another main surface 10n (main surface bonded to the bonding film 12), similarly to the conductive substrate 10. 10an and 2n semiconductor region 10bn.

(Method for Producing Group III Nitride Semiconductor Device of First Example)
Referring to FIG. 10, in the first example of the group III nitride semiconductor device 2 of the first embodiment, a composite substrate 1C including a conductive film 10f including a 1n semiconductor region 10an and a 2n semiconductor region 10bn is prepared. A step of forming the group III nitride semiconductor structure 20 (FIG. 10B), and a step of removing at least the support substrate 11 and the bonding film 12 of the composite substrate 1C (FIG. 10A). 10 (C)), a step of forming the Schottky electrode 30 (FIG. 10D), and a step of forming the ohmic electrode (FIG. 10D).

  First, referring to FIG. 10A, the step of preparing the composite substrate 1C including the conductive film 10f including the 1n semiconductor region 10an and the 2n semiconductor region 10bn includes the above-described 1n semiconductor region 10an and 2n semiconductor region 10bn. This is the same as the method for manufacturing the composite substrate 1C including the conductive film 10f including (FIGS. 9A to 9D).

  Next, referring to FIG. 10B, the step of forming group III nitride semiconductor structure 20 (FIG. 10B) is performed in the method of manufacturing the group III nitride semiconductor device of the second example described above. This is similar to the step of forming the group III nitride semiconductor structure 20 (FIG. 8B).

  Next, referring to FIG. 10C, the step of removing at least support substrate 11 and bonding film 12 of composite substrate 1C is performed by at least one of cutting, grinding, polishing, and etching. From the viewpoint of enhancing the characteristics of the semiconductor device so that the group III nitride semiconductor structure 20 does not include the conductive film 10f, it is preferable to further remove the conductive film 10f of the composite substrate 1C. The removal of the conductive film 10f is not particularly limited, and is performed by at least one of cutting, grinding, polishing, and etching.

  Next, referring to FIG. 10D, the step of forming Schottky electrode 30 is the same as the step of forming Schottky electrode 30 in the method of manufacturing the group III nitride semiconductor device of the fifth example. is there. In the step of forming the ohmic electrode 40, the first 2n semiconductor region is electrically connected to the first 1p semiconductor region 21ap on the other main surface 21n side of the p / n region 21pn by, for example, EB vapor deposition. An ohmic electrode 40 is formed in ohmic contact with 21bn.

  As described above, the Group III nitride semiconductor device 2 of the first example of Embodiment 1 as shown in FIG. 1 is obtained.

(Method for Producing Group III Nitride Semiconductor Device of Third Example)
Referring to FIG. 10, in the third example of the group III nitride semiconductor device 2 of the first embodiment, a composite substrate 1C including a conductive film 10f including a 1n semiconductor region 10an and a 2n semiconductor region 10bn is prepared. The step of forming the group III nitride semiconductor structure 20 (FIGS. 10E and 10F), and removing at least the support substrate 11 and the bonding film 12 of the composite substrate 1C. A step (FIG. 10G) of forming, a step of forming the Schottky electrode 30 (FIG. 10H), and a step of forming an ohmic electrode (FIG. 10H).

  First, referring to FIG. 10A, the step of preparing the composite substrate 1C including the conductive film 10f including the 1n semiconductor region 10an and the 2n semiconductor region 10bn includes the above-described 1n semiconductor region 10an and 2n semiconductor region 10bn. This is the same as the method for manufacturing the composite substrate 1C including the conductive film 10f including (FIGS. 9A to 9D).

  Next, referring to FIGS. 10E and 10F, the step of forming group III nitride semiconductor structure 20 includes group III nitriding in the method for manufacturing a group III nitride semiconductor device of the fourth example described above. This is the same as the step of forming the physical semiconductor structure 20 (FIGS. 8D and 8F).

  Next, referring to FIG. 10G, the step of removing at least the support substrate 11 and the bonding film 12 of the composite substrate 1C is performed by the composite substrate 1C in the method for manufacturing a group III nitride semiconductor device of the first example described above. This is the same as the step of removing at least the support substrate 11 and the bonding film 12 (FIG. 10C).

  Next, referring to FIG. 10H, the step of forming Schottky electrode 30 is the same as the step of forming Schottky electrode 30 in the method of manufacturing the group III nitride semiconductor device of the fifth example. is there. Further, in the step of forming the ohmic electrode 40, ohmic contact with the second 1n semiconductor region 22an and the second 2n semiconductor region 22bn is performed on the other main surface 22n side of the n / n region 22pn by, for example, EB vapor deposition. The electrode 40 is formed.

  As described above, the group III nitride semiconductor device 2 of the third example of the first embodiment as shown in FIG. 3 is obtained. Note that, in the Group III nitride semiconductor device 2 of the third example, in the Group III nitride semiconductor device manufacturing method of the fifth example, a mask 15 is formed on a part of the substrate 1 as shown in FIG. After forming group III nitride semiconductor structure 20 including n / n region 22nn and p / n region 21pn on one main surface 1m, substrate 1 and mask 15 are removed, and one part of p / n region 21pn is formed. It can also be obtained by forming the Schottky electrode 30 on the main surface 21m side and forming the ohmic electrode 40 on the other main surface 22n side of the n / n region 22nn.

Example 1
1. Formation of Mask on Part of Substrate First, referring to FIG. 6A, as substrate 1, one main surface 1m is a (0001) plane, n-type carrier concentration is 3 × 10 ¹⁸ cm ⁻³ and thick. A conductive GaN substrate having a thickness of 300 μm was prepared. Next, a SiO ₂ film having a thickness of 1 μm was formed on the substrate 1 by plasma CVD. Next, a linear resist (not shown) having a width Wp of 5 μm and a pitch (Wp + Wn) of 10 μm was formed by photolithography. Then, by RIE, to remove the area where resist is not formed of the SiO ₂ film forming the line-shaped resist, a SiO ₂ film pitch (Wn + Wp) of 10μm shaped line width Wn is 5μm mask 15 was formed.

2. Formation of Group III Nitride Semiconductor Structure Next, referring to FIG. 6B, trimethylgallium as a source gas is formed by MOVPE on one main surface 1m having a mask 15 formed on a part of substrate 1. Using ammonia and silane, one main surface 22m, which is the second 1n semiconductor region 22an, is a (0001) plane on the region where the mask 15 is not formed, and the n-type carrier concentration is 3 × 10 ¹⁸ cm ^−3. An n-type GaN region having a thickness of 3 μm was formed. At this time, on the region where the mask 15 is formed, an oxygen atom which is an impurity, particularly an n-type conductive impurity, is largely taken in, and one main surface 22m which is the second 2n semiconductor region 22bn is (000-1). An n-type GaN region having an n-type carrier concentration of 1 × 10 ¹⁸ cm ⁻³ and a thickness of 3 μm was formed. Thus, an n / n region 22nn including the second 1n semiconductor region 22an and the second 2n semiconductor region 22bn was obtained.

Next, referring to FIG. 6C, the first main surface 22m of the second 1n semiconductor region 22an is formed by trimethylgallium, ammonia and cyclopentadienylmagnesium as source gases by the MOVPE method. One p-type GaN region having a main surface 21m of 1p semiconductor region 21ap of 1 and a (0001) plane, a p-type carrier concentration of 5 × 10 ¹⁷ cm ⁻³ and a thickness of 5 μm was formed. At this time, on one main surface 22m of the second 2n semiconductor region 22bn, oxygen atoms that are impurities, particularly n-type conductive impurities, are largely taken in, and one main surface 21m that is the first 2n semiconductor region 21bn is ( An n-type GaN region having a thickness of 5 μm and an n-type carrier concentration of 5 × 10 ¹⁶ cm ⁻³ was formed. Thus, a p / n region 21pn including the first 1a semiconductor region 21ap and the first 2n semiconductor region 21bn arranged on the one main surface 22m side of the n / n region 22nn was obtained.

  In this way, the first 1p semiconductor region 21ap and the first 2n semiconductor region 21bn included in the p / n region 21pn, and the second 2n semiconductor region 22bn and the second 1n included in the n / n region 22nn. A group III nitride semiconductor structure 20 having a super junction structure formed of the semiconductor region 22an was formed.

3. Formation of Schottky Electrode Next, referring to FIG. 6D, a one-side square surface having a thickness of 5 nm is formed on one main surface 21m side of the p / n region 21pn by lithography and EB vapor deposition. A Ni layer and a thickness of 30 nm are formed in this order, and annealed at 400 ° C., so that they are electrically connected to at least a part of the first 1p semiconductor region 21ap and are in Schottky contact with the first 2n semiconductor region 21bn. A Schottky electrode 30 was formed.

4). Formation of Ohmic Electrode Next, referring to FIG. 6D, EB deposition is performed on another main surface 1n opposite to one main surface 1m on which the group III nitride semiconductor structure 20 of the substrate 1 is formed. By forming a Ti layer having a thickness of 50 nm, a Pt layer having a thickness of 200 nm, and an Al layer having a thickness of 600 nm by this method, ohmic contact is made with the substrate 1 electrically connected to the second 1n semiconductor region 22an. An ohmic electrode 40 was formed.

  The group III nitride semiconductor device 2 which is an SBD (Schottky barrier diode) obtained as described above was measured for forward and reverse current-voltage characteristics using a voltage source and an ammeter. The on-resistance was 1 mΩ and the breakdown voltage was 2000 V, which was a high characteristic.

  It should be understood that the embodiments and examples disclosed herein are illustrative and non-restrictive in every respect. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

1 Substrate 1m, 10m, 21m, 22m One principal surface 1n, 10n, 21n, 22n Another principal surface 1B Bonded substrate 1C Composite substrate 2 Group III nitride semiconductor device 10, 10r Conductive substrate 10an 1n Semiconductor region 10bn 2n Semiconductor region 10f Conductive film 10i Ion implantation region 10D Conductive body 11 Support substrate 12, 12a, 12b Bonding film 15 Mask 20 Group III nitride semiconductor structure 21ap First 1p semiconductor region 21bn First 2n semiconductor region 21pn p / n region 22an second 1n semiconductor region 22bn second 2n semiconductor region 22nn n / n region 30 Schottky electrode 40 ohmic electrode.

Claims (11)

As a group III nitride semiconductor structure, a plurality of first 1p semiconductor regions having a first crystal orientation and a p-type conductivity type, and between the first 1p semiconductor regions and the first 1p semiconductor region A first 2n semiconductor region having a second crystal orientation different from the first crystal orientation and an n-type conductivity disposed adjacent to the region, the first 1p semiconductor region and The first 2n semiconductor region includes a p / n region existing from one main surface to another main surface;
A Schottky electrode disposed on one main surface side of the p / n region, electrically connected to at least a part of the first 1p semiconductor region and in Schottky contact with the first 2n semiconductor region; Group III nitride semiconductor device.   The group III nitride semiconductor structure is disposed on the other main surface side of the p / n region, and is arranged in contact with the first 1p semiconductor region, the first crystal orientation, and the n-type conductivity type. The second 1n semiconductor region having the first and second 2n semiconductor regions, and the second 1n semiconductor region disposed between and adjacent to the second 1n semiconductor region and adjacent to the second 1n semiconductor region A second 2n semiconductor region having a crystal orientation and an n-type conductivity, wherein the second 1n semiconductor region exists from one main surface to another main surface, and the second 2n semiconductor region The group III nitride semiconductor device according to claim 1, further comprising an n / n region in which at least one main surface is present.   The group III nitride semiconductor device according to claim 1, further comprising a conductive substrate.   The group III nitride semiconductor device according to claim 3, further comprising a mask disposed on a part of the conductive substrate.   The group III nitriding according to any one of claims 1 to 4, wherein the second crystal orientation has a larger oxygen uptake in the group III nitride semiconductor structure than the first crystal orientation. Semiconductor devices. A plurality of first 1p semiconductor regions having a first crystal orientation and a p-type conductivity on a substrate, and between and adjacent to the first 1p semiconductor region. A first 2n semiconductor region having a second crystal orientation different from the first crystal orientation and an n-type conductivity type, and the first 1p semiconductor region and the first 2n semiconductor Forming a group III nitride semiconductor structure including a p / n region in which a region exists from one main surface to another main surface;
Forming a Schottky electrode electrically connected to at least part of the first 1p semiconductor region and in Schottky contact with the first 2n semiconductor region on one main surface side of the p / n region; ,
A method for producing a group III nitride semiconductor device comprising:   The group III nitride semiconductor structure is disposed on another main surface side of the p / n region, and has the first crystal orientation disposed in contact with the first 1p semiconductor region and the n-type conductivity type. A second 1n semiconductor region, and the second crystal disposed in contact with and between the second 1n semiconductor region and adjacent to the second 1n semiconductor region. A second 2n semiconductor region having an orientation and an n-type conductivity type, wherein the second 1n semiconductor region exists from one main surface to another main surface, and the second 2n semiconductor region is The method for manufacturing a group III nitride semiconductor device according to claim 6, further comprising an n / n region present on at least one main surface side. Forming the group III nitride semiconductor structure,
On the substrate, the second 1n semiconductor region, and the second 2n semiconductor region disposed between and adjacent to the second 1n semiconductor region, An n / n region forming sub for forming an n / n region in which the second 1n semiconductor region exists from one main surface to another main surface and the second 2n semiconductor region exists on at least one main surface side. Process,
The first 1p semiconductor region disposed in contact with the second 1n semiconductor region on one main surface side of the n / n region, and in contact with the second 2n semiconductor region and the first first And the first 2n semiconductor region disposed between and adjacent to the first 1p semiconductor region, the first 1p semiconductor region and the first 2n semiconductor region A p / n region forming sub-process for forming a p / n region existing from one main surface to another main surface;
The manufacturing method of the group III nitride semiconductor device of Claim 7 containing these.   In the step of forming the group III nitride semiconductor structure, oxygen is incorporated into the group III nitride semiconductor structure, and the second crystal orientation is greater than the first crystal orientation. The method for manufacturing a group III nitride semiconductor device according to any one of claims 6 to 8, wherein oxygen incorporation into the oxide semiconductor structure is large.   The group III nitride semiconductor according to any one of claims 6 to 9, further comprising a step of forming a mask on a part of the substrate before the step of forming the group III nitride semiconductor structure. Device manufacturing method.   The method for manufacturing a group III nitride semiconductor device according to any one of claims 6 to 10, wherein the substrate is a conductive substrate.

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