JP2015135255A - Semiconductor test jig, measurement device, and test method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor test jig, a measurement device, and a test method using the measurement device with which it is possible to avoid current concentration in a specific portion of a vertical type semiconductor chip, and also to simultaneously measure electrical characteristics of a plurality of vertical type semiconductor chips.SOLUTION: The semiconductor test jig includes: a base made of an insulator; a frame body in which a plurality of frames made of an insulator are provided in lattice form and which is secured to the base so as to divide the base into a plurality of chip disposition parts; and a plurality of metal components buried in the base in such a way as to be insulated from each other. Each of the plurality of chip disposition parts has: a conductive part in which one of the plurality of metal components is exposed in a plan view; and an insulation part in which the base is exposed in the plan view. The frame body has a through-hole formed at a portion in contact with the insulation part for having the metal component exposed.

Description

  The present invention relates to a semiconductor test jig, a measurement apparatus, and a test method using the measurement apparatus used for testing a plurality of vertical semiconductor chips.

  Patent Document 1 discloses a semiconductor transport tray that can handle a plurality of IC packages collectively during a test, and an inspection apparatus that uses the semiconductor transport tray. An IC package to be inspected by the inspection apparatus of Patent Document 1 has a convex contact electrode on the bottom surface in which one or more bare chips cut out from a wafer are packaged.

JP 2006-292727 A

  In the inspection apparatus disclosed in Patent Document 1, it is not possible to measure the electrical characteristics of a vertical semiconductor chip in which a current flows in the vertical direction between the upper surface electrode and the lower surface electrode. A semiconductor test jig, a measuring device, and a semiconductor test jig capable of simultaneously measuring the electrical characteristics of a plurality of vertical semiconductor chips, while avoiding that the current concentrates on a specific portion of the vertical semiconductor chip and the vertical semiconductor chip becomes high temperature A test method using the measuring apparatus has been awaited.

  The present invention has been made to solve the above-described problems, and can prevent current from concentrating on a specific portion of a vertical semiconductor chip and simultaneously measure electrical characteristics of a plurality of vertical semiconductor chips. An object of the present invention is to provide a semiconductor test jig, a measuring apparatus, and a test method using the measuring apparatus.

  In the semiconductor test jig according to the invention of the present application, a base formed of an insulator and a plurality of frames formed of an insulator are provided in a lattice shape, and the base is divided into a plurality of chip installation portions. The frame fixed to the base, the plurality of metal parts embedded in the base so as to be insulated from each other, and the plurality of chip mounting portions are each of the plurality of metal parts in plan view. A through hole that exposes the metal part in a portion of the frame that is in contact with the insulating part. The conductive part has the conductive part from which the one metal part is exposed and the insulating part from which the base is exposed. It is characterized by that.

  The measuring apparatus according to the invention of the present application includes a base made of an insulator and a plurality of frames made of an insulator provided in a lattice shape, and the base is divided into a plurality of chip mounting portions. A frame fixed to the base and a plurality of metal parts embedded in the base so as to be insulated from each other, and the plurality of chip mounting portions are each of the plurality of metal parts in a plan view. A through portion that has a conductive portion where any one metal component is exposed and an insulating portion where the base is exposed, and exposes the metal component to a portion of the frame that is in contact with the insulating portion in plan view At least two vertical semiconductor chips among a semiconductor test jig in which holes are formed, a stage on which the semiconductor test jig is placed, and vertical semiconductor chips each installed on each of the plurality of chip installation portions And a measuring device for simultaneously measuring the above.

  In the test method according to the present invention, a base made of an insulator and a plurality of frames made of an insulator are provided in a lattice shape, and the base is divided into a plurality of chip mounting portions. A frame fixed to the base and a plurality of metal parts embedded in the base so as to be insulated from each other, and the plurality of chip mounting portions are each of the plurality of metal parts in a plan view. A vertical semiconductor chip having an upper surface electrode and a lower surface electrode is placed on the plurality of installation portions of a semiconductor test jig having a conductive portion where any one metal component is exposed and an insulating portion where the base is exposed. A step of bringing the lower surface electrode into contact with the conductive portion, a step of placing the semiconductor test jig on a stage, and exposing the metal part to a portion of the frame that contacts the insulating portion in plan view. The first probe is inserted into the through hole formed in the first through the first probe. While addressed to the genus parts, by applying a second probe to the upper surface electrode, characterized by comprising a step of measuring the electrical characteristics of the vertical semiconductor chip of the plurality, the.

  According to the present invention, since the metal parts in contact with the lower surface electrode of the vertical semiconductor chip are provided for each installation portion, it is possible to avoid current concentration on a specific portion of the vertical semiconductor chip, and for a plurality of vertical semiconductor chips. Electrical characteristics can be measured simultaneously.

1 is a plan view of a semiconductor test jig according to a first embodiment. It is sectional drawing in the II-II broken line of FIG. It is a perspective view of a stage. It is a perspective view of a measuring device. It is a figure which shows a vertical semiconductor chip. It is a figure which shows arrangement | positioning of the probe at the time of a measurement. FIG. 7 is a plan view of FIG. 6. It is a partial cross section figure of the semiconductor test jig concerning a modification. 6 is a plan view of a semiconductor test jig according to Embodiment 2. FIG. It is a partial top view of the semiconductor test jig concerning a modification. It is a partial top view of the semiconductor test jig | tool which concerns on another modification. It is a top view of the semiconductor test jig concerning Embodiment 3 of the present invention. It is sectional drawing in the XIII-XIII broken line of FIG. It is partial sectional drawing of a semiconductor test jig etc. at the time of measurement. FIG. 15 is a plan view of FIG. 14. FIG. 6 is a partial cross-sectional view of a semiconductor test jig and the like according to a fourth embodiment. FIG. 10 is a partial cross-sectional view of a semiconductor test jig and the like according to a fifth embodiment. FIG. 10 is a plan view of a semiconductor test jig according to a sixth embodiment. It is sectional drawing in the XIX-XIX broken line of FIG. FIG. 10 is a partial cross-sectional view of a semiconductor test jig and the like according to a seventh embodiment.

  A semiconductor test jig, a measuring apparatus, and a test method according to an embodiment of the present invention will be described with reference to the drawings. The same or corresponding components are denoted by the same reference numerals, and repeated description may be omitted.

Embodiment 1 FIG.
FIG. 1 is a plan view of a semiconductor test jig 10 according to Embodiment 1 of the present invention. The semiconductor test jig 10 includes a base 12 made of an insulator. A notch 12 a is formed at a corner of the base 12. Four holes 12 b are formed in the outer peripheral portion of the base 12. The notch 12a and the hole 12b are created by machining the base 12, for example. The cutout portion 12a and the four holes 12b are collectively referred to as an alignment portion.

  There is a frame 14 on the base 12. The frame 14 is formed integrally with the base 12. The frame body 14 divides the base 12 into a plurality of chip installation portions 20 by providing a plurality of frames formed of an insulator in a lattice shape. Specifically, since the frame body 14 includes 16 frames, 16 chip placement portions 20 are formed. One chip placement unit 20 is sized to accommodate one vertical semiconductor chip. A through hole 14 a is formed in the frame body 14. At least one through hole 14a is formed in each of the 16 frames.

  A plurality (four) of the metal parts 16 are formed in the chip installation part 20. The metal part 16 is made of, for example, aluminum or copper. The metal component 16 is connected by at least two chip placement portions of the plurality of chip placement portions 20. Specifically, one metal component 16 is provided in four chip placement portions 20 arranged in a direction parallel to the y direction.

  The shape and the like of the metal part 16 will be described with reference to FIG. 2 is a cross-sectional view taken along a broken line II-II in FIG. The plurality of metal parts 16 are embedded in the base 12 so as to be insulated from each other. Each of the plurality of chip placement portions 20 includes a conductive portion 22 where any one of the plurality of metal components 16 is exposed in plan view, and an insulating portion 24 where the base 12 is exposed. The conductive portion 22 and the insulating portion 24 form one flat surface.

  The conductive portion 22 occupies the left half of the chip placement portion 20, and the insulating portion 24 occupies the right half of the chip placement portion 20. If it defines in this way, although the base 12 will be exposed in the few area | regions of the electroconductive part 22, the exposed part of the slight base 12 is not an insulation part. The metal part may be exposed on the entire surface of the conductive portion 22 by removing the slight exposed portion of the base 12.

  It is desirable that the conductive portion 22 be made flat by removing burrs or protrusions by cleaning or polishing so as not to damage the vertical semiconductor chip.

  The through hole 14 a is formed in a portion of the frame body 14 that is in contact with the insulating portion 24. In other words, the through hole 14 a is formed in a straight line portion farthest from the metal part 16 among the four straight line portions constituting the frame of the frame body 14. The metal part 16 is exposed on the bottom surface of the through hole 14a. The metal component 16 has a shape having a portion exposed at the bottom surface of the through hole 14 a, a portion embedded in the base 12 immediately below the insulating portion 24, and a portion exposed at the conductive portion 22.

  Since a probe for passing a current is inserted into the through hole 14a, the through hole 14a is preferably formed in a substantially circular shape in plan view in the thickest portion of the frame body 14 from the viewpoint of preventing discharge. A slope is formed on the frame body 14 so as to surround the chip installation portion 20.

  Returning to the description of FIG. As described above, each of the plurality of chip placement units 20 includes the conductive portion 22 and the insulating portion 24. The boundary line between the conductive portion 22 and the insulating portion 24 is located at the center of each of the plurality of chip placement portions 20 so as to bisect each of the plurality of chip placement portions 20 in plan view.

  A method for manufacturing the semiconductor test jig 10 will be described. The semiconductor test jig 10 is produced by insert molding. Specifically, the base 12 and the frame body 14 are formed of resin around the metal component 16 inserted into the mold, and the metal component 16 and the base 12 and the frame body 14 are integrated. The semiconductor test jig 10 is produced. The semiconductor test jig 10 can be easily manufactured by insert molding in this way.

  FIG. 3 is a perspective view of the stage 30 on which the semiconductor test jig 10 is placed. The stage 30 includes a triangular projection 34 formed on a corner of the flat surface 32 in plan view, and four projections 36 formed on the flat surface 32 that are circular in plan view. The protrusion 34 extends longer than the protrusion 36.

  FIG. 4 is a perspective view of the measuring device 40. The measuring device 40 includes a probe card 42. The probe card 42 includes a first probe 42a and four second probes 42b shorter than the first probe 42a. The first probe 42a and the second probe 42b are referred to as a first probe group 42A.

  The probe card 42 includes a third probe 42c and four fourth probes 42d that are shorter than the third probe 42c. The third probe 42c and the fourth probe 42d are referred to as a second probe group 42B. The probe card 42 is fixed to the attachment portion 44. The semiconductor test jig 10, the stage 30, and the measuring device 40 constitute a measuring device.

  A test method according to Embodiment 1 of the present invention will be described. First, the vertical semiconductor chips 50 and 51 to be tested will be described with reference to FIG. The vertical semiconductor chips 50 and 51 are formed by dividing a semiconductor wafer by dicing or the like. The vertical semiconductor chip 50 includes a main body portion 50a, an upper surface electrode 50b formed on the upper surface side of the main body portion 50a, and a lower surface electrode 50c formed on the lower surface side of the main body portion 50a. The vertical semiconductor chip 50 is configured to pass a current in the vertical direction between the upper surface electrode 50b and the lower surface electrode 50c. The same applies to the vertical semiconductor chip 51.

  As an initial step, as shown in FIG. 5, vertical semiconductor chips are placed on the plurality of chip placement portions 20. Specifically, the vertical semiconductor chip 50 is placed on the chip installation unit 20 using the slope of the frame 14 as a guide for guiding the vertical semiconductor chip 50 to the chip installation unit 20. Accordingly, half of the lower surface electrode 50 c is in contact with the conductive portion 22, and the other half is in contact with the insulating portion 24. In this step, one vertical semiconductor chip is placed on each of the 16 chip placement units 20.

  Next, the semiconductor test jig 10 on which the vertical semiconductor chip is mounted is placed on the stage 30. At this time, the semiconductor test jig 10 is placed on a predetermined location of the stage 30 using the alignment portion of the semiconductor test jig 10. Specifically, first, the notch 12a is applied to the side surface of the projection 34 of the stage 30, and the direction of the semiconductor test jig 10 is determined. Thereafter, the semiconductor test jig 10 is brought close to the stage 30, and the protrusion 36 is inserted into the hole 12b. As described above, the semiconductor test jig 10 is placed on a predetermined location of the stage 30 using the alignment portion, so that the 16 vertical semiconductor chips are collectively positioned at the predetermined location. .

  Next, as shown in FIG. 6, while the first probe 42a is applied to the metal part 16 through the through hole 14a, the four second probes 42b are applied to the upper surface electrode 50b. While the third probe 42c is applied to another metal part 16 through another through hole 14a, the four fourth probes 42d are applied to the upper surface electrode 51b. Thereby, the lower surface electrode 50 c is connected to the first probe 42 a via the metal part 16, and the lower surface electrode 51 c is connected to the third probe 42 c via another metal part 16. In this way, the first probe group 42A is electrically connected to the vertical semiconductor chip 50, and the second probe group 42B is electrically connected to the vertical semiconductor chip 51.

  In this state, current is applied to the first probe 42a and the second probe 42b, current is applied to the third probe 42c and the fourth probe 42d, and the electrical characteristics of the two vertical semiconductor chips 50 and 51 are measured simultaneously. To do. The arrows in FIG. 6 indicate the direction of current flow. The current that has traveled from the first probe 42a to the metal part 16 travels to the boundary between the conductive part 22 and the insulating part 24 in the metal part 16 and flows from the periphery of the boundary to the lower electrode 50c. Then, a current flows from the lower surface electrode 50c to the second probe 42b via the upper surface electrode 50b. The same applies to the second probe group 42B side.

  FIG. 7 is a plan view of FIG. The two second probes 42 b are located immediately above the conductive portion 22, and the other two second probes 42 b are located immediately above the insulating portion 24. The shortest distance from the boundary line between the conductive part 22 and the insulating part 24 to the second probe 42b immediately above the conductive part 22 is substantially equal to the shortest distance from the boundary line to the second probe 42b immediately above the insulating part 24. That is, the current path length from the first probe 42a to the four second probes 42b is uniform. For this reason, the current indicated by the arrows is distributed almost evenly with respect to the four second probes 42b, so that the current distribution in the vertical semiconductor chip 50 is substantially uniform and the current is concentrated on a specific portion of the vertical semiconductor chip 50. Can be avoided. The same applies to the second probe group 42B side. Note that a current may flow in the direction opposite to the arrow in FIG.

  When the test of the vertical semiconductor chips 50 and 51 is finished, the stage 30 is separated from the measuring device 40. Then, 14 vertical semiconductor chips other than the vertical semiconductor chips 50 and 51 are tested in the same manner as described above. At this time, two vertical semiconductor chips to be measured simultaneously are selected so that current can flow through the two metal parts insulated by the base 12. The test is performed on all 16 vertical semiconductor chips, and the process ends.

  According to the semiconductor test jig 10 according to the first embodiment of the present invention, current flow between the metal parts can be prevented by flowing current through the two metal parts 16 insulated by the base 12. That is, it is possible to avoid that one of the two measurements performed simultaneously affects the other measurement. Therefore, the electrical characteristics of the two vertical semiconductor chips can be measured simultaneously and accurately.

  Since the semiconductor test jig 10 has four metal parts 16 insulated by the base 12, a current may be simultaneously supplied to these metal parts. That is, a maximum of four vertical semiconductor chips can be measured simultaneously. In this manner, at least two semiconductor chips among the vertical semiconductor chips installed one by one in each of the plurality of chip installation units 20 can be simultaneously and accurately measured.

  In addition, since a metal part is brought into contact with the lower surface electrode of the vertical semiconductor chip and a probe is brought into contact with the metal part, no current flows through the stage 30. Therefore, for example, the path length of the current flowing through the plurality of vertical semiconductor chips can be made shorter and uniform as compared with the case where current flows from the side surface of the stage to the lower electrode via the stage.

  As shown in FIG. 6, in the first embodiment of the present invention, the distance between the first probe 42a and the end of the vertical semiconductor chip 50 is short, and the distance between the third probe 42c and the vertical semiconductor chip 51 is short. In this case, there is a concern about the discharge between the probe and the vertical semiconductor chip. However, since the first probe 42a and the third probe 42c are covered with the frame body 14, the discharge can be suppressed.

  FIG. 8 is a partial cross-sectional view of a semiconductor test jig according to a modification. The bottom surface of the through hole 14a and the top surface of the conductive portion 22 are the same height. In this case, the difference in height between the tip position of the probe inserted into the through hole and the tip position of the probe applied to the upper surface electrode becomes equal to the thickness of the vertical semiconductor chip, so that the probe can be easily positioned.

  The base 12 and the frame body 14 are not particularly limited as long as they are insulators. For example, a resin such as a PPS material, a PEEK material, or a PES material can be used as the material. For example, when a high temperature test of 200 ° C. or higher is performed, or when a low temperature test is performed, it is desirable to create the base and the frame body 14 with an engineering plastic having heat resistance or cold resistance.

  The semiconductor test jig 10 was formed by insert molding. However, the frame and the base may be separately formed and assembled. In that case, a metal part and a base are first produced by insert molding. Thereafter, the frame body produced by injection molding or cutting is fixed to the base by a method such as screwing or fitting. Thus, if the frame and the base are separate parts, it is possible to replace the frame or the base where the problem has occurred, or to remove the frame and perform maintenance such as cleaning.

  When the frame and the base are formed separately, the metal part and the base may not be insert-molded, and a recess may be provided in the base and the metal part may be installed in the recess. In this case, in order to form the insulating portion, an insulator placed on the metal part is required. By forming the insulator integrally with the frame and fixing the frame to the base, Metal parts can be fixed to the base. In addition, you may form separately the part which forms an insulation part, and a frame.

  The number of chip placement portions 20 of the semiconductor test jig 10 is not limited to 16 and can be adjusted as appropriate. The alignment portion is not limited to the notch portion 12a and the hole 12b, and for example, a notch, a hole, a concave portion, or a convex portion can be used as appropriate. The semiconductor test jig 10 can be used not only for measuring the electrical characteristics of the vertical semiconductor chip but also for transporting the vertical semiconductor chip. It is good also as a structure which enlarges the opening diameter of the through-hole 14a and lets several probes, such as a laminated probe, pass through the through-hole 14a.

  The number of probes (second probe 42b or fourth probe 42d) applied to the upper surface electrode is not particularly limited as long as it is plural. However, in order to prevent the current in the vertical semiconductor chip from concentrating on a specific portion, at least one probe is disposed immediately above the conductive portion 22 and at least one probe is directly above the insulating portion 24. It is necessary to arrange. These modifications can also be applied to semiconductor test jigs, measuring apparatuses, and test methods according to the following embodiments.

  Since the semiconductor test jig, the measuring apparatus, and the test method according to the following embodiment have much in common with the first embodiment, the difference from the first embodiment will be mainly described.

Embodiment 2. FIG.
FIG. 9 is a plan view of the semiconductor test jig 100 according to Embodiment 2 of the present invention. One metal component 102 is provided for each of the plurality of chip placement portions 20. One metal part 102 is insulated from other metal parts 102 by the base 12. Thereby, it is possible to suppress the current flowing through the metal component 102 of one chip installation unit 20 from flowing into the metal component 102 of another chip installation unit 20. Therefore, all 16 vertical semiconductor chips can be measured simultaneously.

  FIG. 10 is a partial plan view of a semiconductor test jig according to a modification. The boundary line between the conductive portion 22 and the insulating portion 24 has a convex shape on the conductive portion 22 side. FIG. 10 also shows a vertical semiconductor chip and a probe. An upper surface electrode 50b and a gate electrode 50d are formed on the upper surface of the vertical semiconductor chip. The gate electrode 50d is formed in a portion close to the through hole in the vertical semiconductor chip. Generally, when a vertical semiconductor chip having a gate electrode is tested, current is concentrated in the vicinity of the gate electrode.

  In the second embodiment of the present invention, since the insulating portion 24 is convex toward the conductive portion 22, the path length of the current flowing through the second probe (neighboring probe) 42b close to the gate electrode 50d is from the gate electrode 50d. It becomes longer than the path length of the current flowing through the distant second probe (distant probe) 42b. Therefore, if only the current path length is considered, the current concentrates on the far probe. However, as described above, the current is more likely to flow in the near probe than in the far probe, so that the current density of the near probe and the far probe can be made almost equal.

  As long as the above characteristics are not lost, the planar shapes of the insulating portion and the conductive portion can be changed as appropriate. FIG. 11 is a partial plan view of a semiconductor test jig according to another modification. The boundary line between the conductive portion and the insulating portion has a convex shape on the insulating portion side. The gate electrode 50d is formed on the opposite side of the through hole 14a in the vertical semiconductor chip. Since the neighboring probe (the two second probes 42b on the left side) is farther from the boundary between the conductive portion 22 and the insulating portion 24 than the far probe (the two second probes 42b on the right side), the current flowing through the neighboring probe The path length is longer than the path length of the current flowing through the far probe. Therefore, if only the current path length is considered, the current concentrates on the far probe. However, since the current flows more easily in the near probe than in the far probe, the current density of the near probe and the far probe can be made substantially equal.

Embodiment 3 FIG.
FIG. 12 is a plan view of a semiconductor test jig 150 according to Embodiment 3 of the present invention. As metal parts provided in each of the plurality of chip placement units 20, there are a first metal part 152 and a second metal part 154 that is insulated from the first metal part 152 by the base 12. As a result, the conductive portion has a first conductive portion 22a where the first metal component 152 is exposed and a second conductive portion 22b where the second metal component 154 is exposed.

  As the through hole, a first through hole 14b and a second through hole 14c are formed in each of the plurality of frames. The first through hole 14b exposes the first metal part 152, and the second through hole 14c exposes the second metal part 154.

  13 is a cross-sectional view taken along the broken line XIII-XIII in FIG. The lower surface of the first metal component 152 is exposed. By fitting the convex portion 152a on the side surface of the first metal component 152 and the concave portion 12c on the side surface of the base 12, the first metal component 152 and the base 12 are assembled so that there is no displacement. The lower surface of the second metal part 154 is exposed in the same manner as the first metal part, and the second metal part 154 is fitted to the base in the same manner as the first metal part.

  As described above, since the semiconductor test jig 150 is formed by assembling parts, the design can be easily changed as compared with the case of insert molding, and the parts can be replaced when any part is defective. The method of fixing the metal parts (first metal part 152, second metal part 154) to the base 12 is not particularly limited. For example, a concave part is formed on the side surface of the metal part and a convex part is formed on the side surface of the base part. May be.

  FIG. 14 is a partial cross-sectional view of a semiconductor test jig or the like during measurement. Since the lower surfaces of the metal parts (the first metal part 152 and the second metal part 154) are exposed, the metal parts are in contact with the stage 30. At the time of measurement, the vertical semiconductor chip 50 is heated from the stage 30 through the metal part.

  FIG. 15 is a plan view of FIG. In FIG. 15, for convenience of explanation, the upper surface electrode 50b is indicated by a broken line. One first probe 42a is inserted into each of the first through hole 14b and the second through hole 14c. The four second probes 42b applied to the upper surface electrode 50b are respectively located immediately above the first conductive portion 22a, directly above the second conductive portion 22b, between the first conductive portion 22a and the first through hole 14b, It is located between the conductive part 22b and the second through hole 14c.

  The current flows from the first probe 42a inserted into the first through hole 14b to the two second probes via the first metal component 152 and the vertical semiconductor chip, and is inserted into the second through hole 14c. The first probe 42a flows to another two second probes via the second metal component 154 and the vertical semiconductor chip. As described above, by generating the current passing through the first metal component 152 and the current passing through the second metal component 154, the current distribution in the vertical semiconductor chip can be made uniform.

  The number of metal parts provided in one chip installation part and the number of through holes are not particularly limited.

Embodiment 4 FIG.
FIG. 16 is a partial cross-sectional view of a semiconductor test jig 200 and the like according to the fourth embodiment of the present invention. The lower surface of the metal component 202 is exposed immediately below the chip installation portion 20, but the lower surface of the base 12 is exposed immediately below the through hole 14a. As a result, the area of the exposed portion of the lower surface of the metal part 202 and the area of the lower surface electrode 50c of the vertical semiconductor chip 50 are substantially equal.

  When the metal part 202 is heated with the lower surface of the metal part 202 exposed, it is preferable to reduce the volume of the metal part 202 as much as possible in order to suppress heat conduction from the metal part 202 to the base 12 and the frame body 14. . In the fourth embodiment of the present invention, since the base 12 is exposed directly below the through hole 14a, the volume of the metal part can be reduced as compared with the case where the metal part is exposed immediately below the through hole 14a. . Therefore, heat conduction from the metal part 202 to the base 12 and the frame body 14 can be suppressed, and these thermal deformations can be prevented.

Embodiment 5 FIG.
FIG. 17 is a partial cross-sectional view of a semiconductor test jig 250 and the like according to the fifth embodiment of the present invention. The base 252 and the metal part 254 are fitted and fixed. The lower surface of the metal part 254 is below the lower surface of the base 252. That is, the Z coordinate of the lower surface of the metal part 254 is smaller than the Z coordinate of the lower surface of the base 252 by Z1. Thus, the stage serving as a heat source hits only the metal part 254 and does not hit the base 252. Therefore, heat conduction to the base and the frame can be suppressed.

  The semiconductor test jig 250 is assembled as follows. First, the base 252 and the metal part 254 are fitted and fixed. Next, an insulator 256 is provided in the recess of the metal part 254. The insulating portion 24 is formed by the insulator 256. Next, the frame body 258, a part of which is positioned on the insulator 256, is fixed to the base 252. Thereby, the insulator 256 can be fixed.

Embodiment 6 FIG.
FIG. 18 is a plan view of a semiconductor test jig 300 according to Embodiment 6 of the present invention. A metal part 302 is formed on the chip installation unit 20. Most of the chip setting part 20 is occupied by the conductive part 22 where the metal part 302 is exposed. There is an insulating portion 24 so as to surround the conductive portion 22.

  19 is a cross-sectional view taken along the broken line XIX-XIX in FIG. The metal part 302 is formed by integrally forming a first portion 302A, a second portion 302B, and a third portion 302C. The first portion 302A is a portion exposed on the bottom surface of the through hole 14a. The lower surface of the first portion 302A is also exposed. The second portion 302B is a portion formed on the first portion 302A with a width narrower than that of the first portion 302A. The third portion 302C is a portion formed on the second portion 302B with a width wider than that of the second portion 302B.

  The current at the time of the test proceeds from the portion exposed at the bottom surface of the through hole 14a of the first portion 302A to the first portion 302A in the X negative direction, and is induced by the second portion 302B directly below the center portion of the chip mounting portion. It reaches the vertical semiconductor chip via the three portions 302C. This current path makes the path length of the current flowing through each probe uniform, as in the embodiments so far. Furthermore, since most of the lower surface electrodes of the vertical semiconductor chip are in contact with the metal component 302, the temperature of the vertical semiconductor chip can be increased efficiently.

Embodiment 7 FIG.
FIG. 20 is a partial cross-sectional view of a semiconductor test jig 350 and the like according to the seventh embodiment of the present invention. A metal plate 352 is provided on the chip installation unit 20 so as to contact the conductive unit 22 and the insulating unit 24. In order to prevent the displacement between the metal plate 352 and the conductive portion 22, it is preferable that both are fitted and fixed with a fitting structure.

  The entire surface of the lower surface electrode 50 c of the vertical semiconductor chip 50 is in contact with the metal plate 352. Therefore, the vertical semiconductor chip 50 can be efficiently heated without complicating the shape of the metal part 354 as in the metal part 302 of FIG.

  A metal part having a complicated shape such as the metal part 302 shown in FIG. 19 is difficult to insert-mold. However, a metal part having a simple shape such as the metal part 354 shown in FIG. 20 is easy to insert-mold. Note that it is preferable to provide a conductive paste between the metal plate 352 and the conductive portion 22 and the insulating portion 24 to ensure electrical connection between the metal plate 352 and the conductive portion 22.

  A conductive spacer 356 is provided in the through hole 14a so as to contact the metal part 354 on the bottom surface of the through hole 14a. The Z coordinate of the upper surface of the spacer 356 matches the Z coordinate of the upper surface of the upper electrode 50b. Therefore, since the tip positions of the first probe and the second probe can be matched, the tip positions can be easily aligned.

  Similarly to the third portion 302C of FIG. 19, the metal plate 352 is in contact with most of the lower surface electrodes of the vertical semiconductor chip to increase the efficiency of heating. Accordingly, the metal plate 352 and the third portion 302C need to be in contact with more than half of the lower surface electrode, but are not necessarily in contact with the entire lower surface electrode.

  The features of the semiconductor test jig, the measurement apparatus, and the test method according to each embodiment described so far may be combined as appropriate.

  DESCRIPTION OF SYMBOLS 10 Semiconductor test jig | tool, 12 base, 14 frame, 14a through-hole, 14b 1st through-hole, 14c 2nd through-hole, 16 metal parts, 20 chip installation part, 22 electrically conductive part, 24 insulation part, 30 stage, 40 measuring instrument, 42a first probe, 42b second probe, 50 vertical semiconductor chip, 50b upper surface electrode, 50c lower surface electrode, 102 metal component, 152 first metal component, 154 second metal component, 202,254,302 metal Parts, 352 Metal plate, 356 Spacer

Claims (17)

A base formed of an insulator;
A plurality of frames formed of an insulator are provided in a lattice shape, and a frame body fixed to the base so as to divide the base into a plurality of chip installation portions;
A plurality of metal parts embedded in the base so as to be insulated from each other;
Each of the plurality of chip placement portions has a conductive portion in which any one of the plurality of metal components is exposed in plan view, and an insulating portion in which the base is exposed,
A through hole for exposing the metal part is formed in a portion of the frame that is in contact with the insulating portion.   2. The semiconductor test jig according to claim 1, wherein the metal parts are connected by at least two chip placement portions of the plurality of chip placement portions.   The semiconductor test jig according to claim 1, wherein each of the plurality of chip placement portions is provided with one metal part.   The boundary line between the conductive portion and the insulating portion is located at the center of each of the plurality of chip placement portions so as to bisect each of the plurality of chip placement portions in plan view. Item 4. The semiconductor test jig according to any one of Items 1 to 3.   The semiconductor test jig according to claim 1, wherein a boundary line between the conductive portion and the insulating portion has a convex shape toward the conductive portion.   The semiconductor test jig according to any one of claims 1 to 3, wherein a boundary line between the conductive portion and the insulating portion has a convex shape toward the insulating portion. The through hole has a first through hole and a second through hole in each of the plurality of frames.
As the metal parts provided in each of the plurality of chip installation portions, a first metal part and a second metal part insulated from the first metal part by the base,
The conductive part has a first conductive part from which the first metal part is exposed and a second conductive part from which the second metal part is exposed,
The first through hole exposes the first metal component;
The semiconductor test jig according to claim 1, wherein the second through hole exposes the second metal part.   The semiconductor test jig according to claim 1, wherein a lower surface of the metal part is exposed.   The semiconductor test jig according to claim 8, wherein a lower surface of the base is exposed immediately below the through hole.   10. The semiconductor test jig according to claim 8, wherein a lower surface of the metal part is located below a lower surface of the base. The metal part is
A first portion exposed on a bottom surface of the through hole;
A second portion formed on the first portion with a width narrower than the first portion;
The semiconductor test jig according to any one of claims 1 to 3, further comprising a third portion formed on the second portion with a width wider than the second portion. .   The semiconductor test jig according to claim 1, wherein the installation portion includes a metal plate provided so as to be in contact with the conductive portion and the insulating portion.   The semiconductor test jig according to claim 12, wherein a conductive paste is provided between the metal plate and the conductive portion and the insulating portion.   The semiconductor test jig according to claim 1, further comprising a conductive spacer provided in the through hole so as to be in contact with the metal part on a bottom surface of the through hole. .   The semiconductor test jig according to claim 1, wherein the base and the frame are integrally formed. A base formed of an insulator, a plurality of frames formed of an insulator are provided in a lattice shape, and a frame fixed to the base so as to divide the base into a plurality of chip installation portions; A plurality of metal parts embedded in the base so as to be insulated from each other, and each of the plurality of chip mounting portions exposes any one metal part of the plurality of metal parts in a plan view. A semiconductor test jig having a conductive portion and an insulating portion from which the base is exposed, wherein a through-hole exposing the metal part is formed in a portion of the frame that contacts the insulating portion in plan view When,
A stage on which the semiconductor test jig is placed;
A measuring device comprising: a measuring device that simultaneously measures at least two vertical semiconductor chips among the vertical semiconductor chips installed one by one in each of the plurality of chip installing portions. A base formed of an insulator, a plurality of frames formed of an insulator are provided in a lattice shape, and a frame fixed to the base so as to divide the base into a plurality of chip installation portions; A plurality of metal parts embedded in the base so as to be insulated from each other, and each of the plurality of chip mounting portions exposes any one metal part of the plurality of metal parts in a plan view. A vertical semiconductor chip having an upper surface electrode and a lower surface electrode is placed on the plurality of installation portions of the semiconductor test jig having a conductive portion and an insulating portion with the base exposed, and the lower surface electrode and the conductive portion are placed A step of contacting;
Placing the semiconductor test jig on a stage;
While the first probe is applied to the metal component through a through hole formed so as to expose the metal component in a portion of the frame that is in contact with the insulating portion in plan view, the second probe And a step of applying a probe to the upper surface electrode and measuring electrical characteristics of the plurality of vertical semiconductor chips.

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