JP2015179250A - 表示装置 - Google Patents
表示装置 Download PDFInfo
- Publication number
- JP2015179250A JP2015179250A JP2014234094A JP2014234094A JP2015179250A JP 2015179250 A JP2015179250 A JP 2015179250A JP 2014234094 A JP2014234094 A JP 2014234094A JP 2014234094 A JP2014234094 A JP 2014234094A JP 2015179250 A JP2015179250 A JP 2015179250A
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- Prior art keywords
- film
- oxide semiconductor
- insulating film
- pixel
- oxide
- Prior art date
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- 239000000758 substrate Substances 0.000 claims abstract description 97
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- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 description 1
- 229910001887 tin oxide Inorganic materials 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 229910052723 transition metal Inorganic materials 0.000 description 1
- LXEXBJXDGVGRAR-UHFFFAOYSA-N trichloro(trichlorosilyl)silane Chemical compound Cl[Si](Cl)(Cl)[Si](Cl)(Cl)Cl LXEXBJXDGVGRAR-UHFFFAOYSA-N 0.000 description 1
- MCULRUJILOGHCJ-UHFFFAOYSA-N triisobutylaluminium Chemical compound CC(C)C[Al](CC(C)C)CC(C)C MCULRUJILOGHCJ-UHFFFAOYSA-N 0.000 description 1
- 238000007738 vacuum evaporation Methods 0.000 description 1
- 230000008016 vaporization Effects 0.000 description 1
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Abstract
【解決手段】トランジスタは、基板上のゲート電極と、ゲート電極と重なる酸化物半導体膜と、酸化物半導体膜の一方の面に接するゲート絶縁膜と、酸化物半導体膜に接する一対の導電膜と、を有する。容量素子は、ゲート絶縁膜上であって、且つ一対の導電膜の一方と接する金属酸化物膜と、無機絶縁膜と、無機絶縁膜上の第1の透光性を有する導電膜と、を有する。画素電極は、第2の透光性を有する導電膜で形成され、且つ一対の導電膜の一方と接する。ゲート電極でもある第1のゲート線は、4つの副画素のうち、3つの副画素を選択するよう接続し、第2のゲート線は、残りの副画素を選択するとともに、次行の1つの副画素を選択するよう接続する。
【選択図】図1
Description
本実施の形態では、本発明の一態様である表示装置が有する画素の構成について図面を参照して説明する。
ここで、酸化物半導体で形成される膜(以下、酸化物半導体膜(OS)という。)及び酸化物導電体で形成される膜(以下、酸化物導電体膜(OC)という。)それぞれにおける、抵抗率の温度依存性について、図29を用いて説明する。図29において、横軸に測定温度を示し、縦軸に抵抗率を示す。また、酸化物半導体膜(OS)の測定結果を丸印で示し、酸化物導電体膜(OC)の測定結果を四角印で示す。
<変形例1>
図28(A)に示すトランジスタの変形例について、図28(C)を用いて説明する。本変形例に示すトランジスタ103dは、チャネル保護構造で形成されたトランジスタであることを特徴とする。
図28(A)乃至(C)に示す表示装置において、場合によっては、または、状況に応じて、例えば、導電膜319として、光を反射する機能を有する導電膜を用いて形成してもよい。または、導電膜319として、積層膜を用いて形成し、積層膜の少なくとも一つの膜として、光を反射する機能を有する導電膜を用いてもよい。光を反射する機能を有する導電膜の材料の一例としては、銀、アルミニウム、クロム、銅、タンタル、チタン、モリブデン、タングステンなどを用いることができる。または、導電膜319として、銀を用いて形成した膜の上下をITOで挟んだような積層膜を用いて形成してもよい。このような場合、反射型の表示装置、半透過型の表示装置、トップエミッション構造の発光装置などに、図28(A)乃至(C)に示す表示装置を適用することができる。
本実施の形態では、本発明の一態様である表示装置及びその作製方法について、具体的な構成を示す図面を参照して説明する。
本実施の形態では、実施の形態1と異なるトランジスタを有する液晶表示装置について、図11乃至図15を用いて説明する。
実施の形態3の図11に示す液晶表示装置は、駆動回路部のトランジスタとして、デュアルゲート構造のトランジスタを用いて作製されているが、図12に示すように、A−Bに示す駆動回路部にデュアルゲート構造のトランジスタ102aを有するとともに、C−Dに示す画素部にデュアルゲート構造のトランジスタ103aを用いてもよい。
実施の形態2または実施の形態3に示す液晶表示装置において、図13に示すように、駆動回路部に設けられたトランジスタ102aと重なる領域であって、且つ有機絶縁膜317上に、導電膜319と同時に形成された導電膜319bを設けてもよい。導電膜319bは、コモン電位、接地電位等の任意の電位とすることができる。デュアルゲート構造のトランジスタ102aと重なる導電膜319bを設けることで、トランジスタ102aのゲート電極として機能する導電膜316dに印加された電圧により発生する電界を導電膜319bが遮蔽することが可能である。この結果、該電界による液晶層321の配向不良を防ぐことができる。
実施の形態2または実施の形態3において、駆動回路部及び画素部に有機絶縁膜317を有する液晶表示装置を説明したが、図14に示すように、画素部にのみ有機絶縁膜317aを設けてもよい。
<変形例4>
実施の形態2及び実施の形態3に示すトランジスタ102、102a、103、103aにおいて、必要に応じて、酸化物半導体膜を積層構造とすることができる。ここでは、トランジスタ103を用いて説明する。
本実施の形態では、上記実施の形態で説明した表示装置に含まれているトランジスタにおいて、酸化物半導体膜に適用可能な一態様について説明する。
実施の形態2で述べたように、酸化物半導体膜を用いたトランジスタは、オフ状態における電流値(オフ電流値)を低く制御することができる。よって、画像信号等の電気信号の保持時間を長くすることができ、書き込み間隔も長く設定できる。
本実施の形態では、本発明の一態様の表示装置が適用された電子機器の構成例について説明する。また、本実施の形態では、本発明の一態様の表示装置を適用した表示モジュールについて、図21を用いて説明を行う。
13 画素
13_1 画素
13_2 画素
14 副画素
14B 副画素
14B_1 副画素
14B_2 副画素
14G 副画素
14G_1 副画素
14G_2 副画素
14R 副画素
14R_1 副画素
14R_2 副画素
14W_1 副画素
14W_2 副画素
16 信号線駆動回路
17 走査線
17_1 走査線
17_2 走査線
17_3 走査線
18 電位生成回路
19 容量線
25 信号線
25_1 信号線
25_2 信号線
25_3 信号線
31 液晶素子
41 発光素子
43 トランジスタ
45 トランジスタ
47 配線
49 配線
50 配線
51 ゲート絶縁膜
53 無機絶縁膜
53a 絶縁膜
70 電子銃室
72 光学系
74 試料室
76 光学系
78 カメラ
80 観察室
82 フィルム室
84 電子
88 物質
92 蛍光板
100 表示装置
102 トランジスタ
102a トランジスタ
103 トランジスタ
103a トランジスタ
103d トランジスタ
105 容量素子
302 基板
304a 導電膜
304b 導電膜
304c 導電膜
304d 導電膜
305 絶縁膜
306 絶縁膜
307 酸化物半導体膜
308a 酸化物半導体膜
308b 酸化物半導体膜
308c 金属酸化物膜
308d 酸化物半導体膜
308e 酸化物半導体膜
308f 金属酸化物膜
309 導電膜
310a 導電膜
310b 導電膜
310c 導電膜
310d 導電膜
310e 導電膜
310f 導電膜
310g 導電膜
310h 導電膜
310i 導電膜
310j 導電膜
311 絶縁膜
311a 絶縁膜
311b 絶縁膜
312 絶縁膜
312a 絶縁膜
312b 絶縁膜
313 絶縁膜
314 絶縁膜
315 導電膜
316a 導電膜
316b 導電膜
316d 導電膜
316e 導電膜
317 有機絶縁膜
317a 有機絶縁膜
318 導電膜
319 導電膜
319a 導電膜
319b 導電膜
320 配向膜
321 液晶層
322 液晶素子
336 多層膜
336a 酸化物半導体膜
336b 酸化物半導体膜
342 基板
344 遮光膜
346 有色膜
348 絶縁膜
350 導電膜
352 配向膜
362 開口部
364a 開口部
364b 開口部
364c 開口部
364d 開口部
371 有機樹脂膜
373 EL層
375 共通電極
1001 本体
1002 筐体
1003a 表示部
1003b 表示部
1004 キーボードボタン
1021 本体
1022 固定部
1023 表示部
1024 操作ボタン
1025 外部メモリスロット
1030 筐体
1031 筐体
1032 表示パネル
1033 スピーカー
1034 マイクロフォン
1035 操作キー
1036 ポインティングデバイス
1037 カメラ
1038 外部接続端子
1040 太陽電池
1041 外部メモリスロット
1050 テレビジョン装置
1051 筐体
1052 記憶媒体再生録画部
1053 表示部
1054 外部接続端子
1055 スタンド
1056 外部メモリ
8000 表示モジュール
8001 上部カバー
8002 下部カバー
8003 FPC
8004 タッチパネル
8005 FPC
8006 表示パネル
8007 バックライトユニット
8008 光源
8009 フレーム
8010 プリント基板
8011 バッテリー
Claims (7)
- 第1乃至第4の副画素を有する第1の画素、及び前記第1の画素の次行に設けられる第1乃至第4の副画素を有する第2の画素を有し、
前記第1の画素が有する前記第1乃至第3の副画素を選択するための信号を与える第1の配線と、
前記第1の画素が有する前記第4の副画素を選択するための第2の配線と、を有し、
前記第2の配線は、前記第2の画素が有する第4の副画素を選択するための配線であることを特徴とする表示装置。 - 第1乃至第4の副画素を有する第1の画素、及び前記第1の画素の次行に設けられる第1乃至第4の副画素を有する第2の画素を有し、
前記第1の画素が有する前記第1乃至第3の副画素を選択するための信号を与える第1の配線と、
前記第1の画素が有する前記第4の副画素を選択するための第2の配線と、
前記第2の画素が有する前記第1乃至第3の副画素を選択するための第3の配線と、を有し、
前記第2の配線は、前記第2の画素が有する第4の副画素を選択するための配線であることを特徴とする表示装置。 - 請求項1又は2において、前記第1の画素及び前記第2の画素が有する、前記第1乃至第4の副画素は、
基板上のトランジスタと、
前記トランジスタと接する無機絶縁膜と、
前記無機絶縁膜と接する有機絶縁膜と、
前記トランジスタと電気的に接続する容量素子と、
前記有機絶縁膜上に形成され、且つ前記トランジスタと電気的に接続する画素電極と、
を有し、
前記トランジスタは、前記基板上のゲート電極と、
前記ゲート電極と重なる酸化物半導体膜と、
前記酸化物半導体膜の一方の面に接するゲート絶縁膜と、
前記酸化物半導体膜に接する一対の導電膜と、を有し、
前記容量素子は、前記ゲート絶縁膜上であって、且つ前記一対の導電膜の一方と接する金属酸化物膜と、
前記無機絶縁膜と、
前記無機絶縁膜上の第1の透光性を有する導電膜と、を有し、
前記画素電極は、第2の透光性を有する導電膜で形成され、且つ前記一対の導電膜の一方と接することを特徴とする表示装置。 - 請求項1乃至3のいずれか一において、
前記無機絶縁膜は、前記酸化物半導体膜の他方の面に接する酸化物絶縁膜と、
前記酸化物絶縁膜に接する窒化物絶縁膜と、
を有すること特徴とする表示装置。 - 請求項1乃至4のいずれか一において、
前記金属酸化物膜は、前記窒化物絶縁膜に接して形成され、且つ前記酸化物半導体膜と同じ金属元素を含むことを特徴とする表示装置。 - 請求項1乃至5のいずれか一において、
前記酸化物半導体膜は、In−Ga酸化物、In−Zn酸化物、またはIn−M−Zn酸化物(MはAl、Ga、Y、Zr、Sn、La、Ce、Nd、Sn、またはHf)を有することを特徴とする表示装置。 - 請求項1乃至6のいずれか一において、
前記酸化物半導体膜は、第1の膜及び第2の膜を含む多層構造であり、
前記第1の膜は、前記第2の膜と金属元素の原子数比が異なることを特徴とする表示装置。
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JP2021144226A (ja) * | 2015-10-30 | 2021-09-24 | 株式会社半導体エネルギー研究所 | 表示装置 |
JP2017161521A (ja) * | 2016-03-04 | 2017-09-14 | 株式会社半導体エネルギー研究所 | 半導体装置、表示パネル、および電子機器 |
JP2018022061A (ja) * | 2016-08-04 | 2018-02-08 | 株式会社半導体エネルギー研究所 | 表示装置 |
US10276594B2 (en) | 2016-09-12 | 2019-04-30 | Semiconductor Energy Laboratory Co., Ltd. | Display device and electronic device |
JPWO2019087023A1 (ja) * | 2017-11-02 | 2020-12-17 | 株式会社半導体エネルギー研究所 | 表示装置および電子機器 |
CN111247580A (zh) * | 2017-11-02 | 2020-06-05 | 株式会社半导体能源研究所 | 显示装置以及电子设备 |
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US11189643B2 (en) | 2017-11-02 | 2021-11-30 | Semiconductor Energy Laboratory Co., Ltd. | Display device and electronic device |
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JP7177962B2 (ja) | 2017-11-02 | 2022-11-24 | 株式会社半導体エネルギー研究所 | 表示装置、電子機器 |
US11715740B2 (en) | 2017-11-02 | 2023-08-01 | Semiconductor Energy Laboratory Co., Ltd. | Display device and electronic device |
US11935897B2 (en) | 2017-11-02 | 2024-03-19 | Semiconductor Energy Laboratory Co., Ltd. | Display device and electronic device |
JP7477672B2 (ja) | 2017-11-02 | 2024-05-01 | 株式会社半導体エネルギー研究所 | 表示装置 |
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KR20150061578A (ko) | 2015-06-04 |
JP6753970B2 (ja) | 2020-09-09 |
TW201530744A (zh) | 2015-08-01 |
TWI675461B (zh) | 2019-10-21 |
KR102493175B1 (ko) | 2023-01-27 |
JP7498332B2 (ja) | 2024-06-11 |
JP2019117384A (ja) | 2019-07-18 |
JP2024116196A (ja) | 2024-08-27 |
TW201937712A (zh) | 2019-09-16 |
KR20210036899A (ko) | 2021-04-05 |
JP2022070929A (ja) | 2022-05-13 |
JP7265658B2 (ja) | 2023-04-26 |
JP6486660B2 (ja) | 2019-03-20 |
JP2023099018A (ja) | 2023-07-11 |
JP2021002044A (ja) | 2021-01-07 |
TWI703713B (zh) | 2020-09-01 |
KR102240809B1 (ko) | 2021-04-14 |
US20150144945A1 (en) | 2015-05-28 |
US9880437B2 (en) | 2018-01-30 |
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