JP2015056644A - Silicon carbide semiconductor device and silicon carbide semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a silicon carbide semiconductor device and a silicon carbide semiconductor device manufacturing method, which can inhibit increase in on-resistance of a MOSFET and reduce on-state voltage of an IGBT.SOLUTION: A vertical silicon carbide MOSFET comprises: an n type drift region 2 and a p type region 21, which are sequentially deposited on a surface of an ntype semiconductor substrate 1 composed of a silicon carbide; a ptype base region 3 selectively provided on a surface layer of the p type region 21; an n type region 6 which is provided inside the p type region 21 and pierces the p type region 21 to reach the n type drift region 2; a p type base region 4 deposited on the ptype base region 3 and the n type region 6; an ntype source region 7 and an n type region 5 which pierces the p type base region 4 to reach the n type region 6, selectively provided inside the p type base region 4; and a gate electrode 10 provided on surfaces across the n type region 5 to the ntype source region 7 via a gate insulation film 9.

Description

  The present invention relates to a silicon carbide semiconductor device and a method for manufacturing a silicon carbide semiconductor device.

  Silicon carbide (SiC) has features such as a wide band gap, a large electric field strength leading to dielectric breakdown, and a high thermal conductivity as compared with silicon (Si). In addition, silicon carbide has a sufficiently high bulk mobility (carrier mobility) compared to silicon, and the surface can be oxidized by thermal oxidation to form an insulating layer, similar to silicon. For this reason, silicon carbide is being put into practical use as a semiconductor material capable of producing (manufacturing) a power semiconductor device exceeding the limit of power semiconductor devices using silicon. Among various power semiconductor devices, in particular, an insulated gate semiconductor device such as an insulated gate field effect transistor (MOSFET) or an insulated gate bipolar transistor (IGBT) has been actively researched and developed. For example, MOSFETs are mainly used in a withstand voltage class of 10 kV or less, and IGBTs are considered promising in a withstand voltage class exceeding 10 kV.

In addition, in a semiconductor device using silicon carbide (hereinafter referred to as a silicon carbide semiconductor device), a p-type base region and an n-type drift region are less formed than in a semiconductor device using silicon due to the band gap of silicon carbide. The potential difference (built-in potential Vbi) naturally formed between the pn junctions is large. For this reason, when the impurity concentration of the p-type base region is a uniform impurity concentration corresponding to the threshold voltage of an appropriate element based on the design conditions, n from the pn junction between the p-type base region and the n-type drift region ^The depletion layer extending toward the ⁺⁺ type source region easily contacts (punch-through) the n ⁺⁺ type source region, and it is difficult to increase the breakdown voltage. Therefore, a p ⁺ type region having a higher impurity concentration than the p type base region is provided between the p type base region and the n type drift region as a prevention layer for preventing the p type base region from punching through. (See, for example, Patent Document 1 (FIGS. 4 and 17) and Patent Document 2 (FIGS. 1 and 2) below). A structure of a conventional silicon carbide semiconductor device having such a structure will be described by taking MOSFET as an example.

FIG. 14 is a cross sectional view showing a structure of a conventional silicon carbide semiconductor device. FIG. 14 schematically shows a half cell of the main part of the silicon carbide semiconductor device proposed in Patent Document 1 below. The actual overall structure of the silicon carbide semiconductor device is such that the configuration of the half cell shown in FIG. 14 is continuous with both ends thereof as axes of line symmetry (the same applies to FIGS. 15 and 16). As shown in FIG. 14, an n-type drift region 102 is deposited by epitaxial growth on the front surface of an n ⁺⁺ type semiconductor substrate 101 made of four-layer periodic hexagonal (4H) silicon carbide. A p ⁺ type base region 103a that is an ion implantation region is selectively provided on the surface layer of the n type drift region 102 opposite to the n ⁺⁺ type semiconductor substrate 101 side, and adjacent p ⁺ type bases are provided. An n-type region 106 is provided in a region sandwiched between the regions 103a. A p-type base region 104 is deposited on the surfaces of the p ⁺ -type base region 103a and the n-type region 106 by epitaxial growth.

Inside the p-type base region 104, an n-type region 105 that is an ion implantation region is selectively provided so as to penetrate the p-type base region 104 in the depth direction and reach the n-type region 106. Further, an n ⁺⁺ type source region 107 and a p ⁺⁺ type contact region 108 are selectively provided in the p type base region 104 apart from the n type region 105. From the surface of the n-type region 105, on the surface of the p-type base region 104 between the n-type region 105 and the n ^++- type source region 107, and a part of the n ^++- type source region 107 A gate electrode 110 is provided over the surface through a gate insulating film 109. Source electrode 111 is in contact with n ⁺⁺ type source region 107 and p ⁺⁺ type contact region 108 and is electrically insulated from gate electrode 110 by interlayer insulating film 113. A drain electrode 112 is provided on the back surface of the n ⁺⁺ type semiconductor substrate 101 serving as an n ⁺⁺ type drain region.

FIG. 15 shows a modified example in which the p ⁺ type base region 103a is a deposited layer in the above-described conventional silicon carbide semiconductor device of FIG. FIG. 15 is a cross sectional view showing a structure of another example of a conventional silicon carbide semiconductor device. FIG. 15 schematically shows a half cell of the main part of the silicon carbide semiconductor device proposed in Patent Document 2 below. In the conventional silicon carbide semiconductor device shown in FIG. 15, p ⁺ type base region 103b is deposited on the surface of n type drift region 102 opposite to the n ⁺⁺ type semiconductor substrate 101 side. Inside the p ⁺ -type base region 103b, as through the p ⁺ -type base region 103b in the depth direction reaching the n-type drift region 102, n-type region 106 is selectively provided in an ion implanted region ing. The structure of the conventional silicon carbide semiconductor device shown in FIG. 15 other than the p ⁺ type base region 103b is the same as that of the conventional silicon carbide semiconductor device shown in FIG.

In the planar silicon carbide semiconductor device having the planar gate structure as shown in FIGS. 14 and 15 described above, when a gate voltage (positive voltage) equal to or higher than the threshold voltage is applied to the gate electrode 110, Electrons are induced in the surface layer in the region immediately below the gate electrode 110, and an n-type inversion layer (channel) is formed. Then, electrons are injected from the n ⁺⁺ type source region 107 into the n type region 105 through the n type inversion layer. The electrons injected into the n-type region 105 reach the n ⁺⁺ type drain region (n ⁺⁺ type semiconductor substrate 101) through the n type region 106 and the n type drift region 102. Accordingly, the drain electrode 112 and the source electrode 111 are brought into conduction, and a current can flow from the drain electrode 112 to the source electrode 111.

As described above, the conventional silicon carbide semiconductor device shown in FIGS. 14 and 15 is a surface channel type in which a channel is formed on the interface side of p-type base region 104 with gate insulating film 109. As another silicon carbide semiconductor device, a buried channel in which an n-type region 114 (see FIG. 16) serving as a channel is provided between the gate insulating film 109 and the p ⁺ -type base region 103a in place of the p-type base region 104. (See, for example, Patent Document 3 (FIG. 46) and Patent Document 4 (FIG. 6) below). The structure of this buried channel type silicon carbide semiconductor device is shown in FIG. FIG. 16 is a cross-sectional view showing the structure of another example of a conventional semiconductor device.

As shown in FIG. 16, n-type region 114 serving as a channel is provided between gate insulating film 109 and n-type drift region 102, p ⁺ -type base region 103 a and n ⁺⁺ -type source region 107. . Configurations other than n-type region 114 of the conventional silicon carbide semiconductor device shown in FIG. 16 are the same as those of the conventional silicon carbide semiconductor device shown in FIG. In such a buried channel type silicon carbide semiconductor device, when no gate voltage is applied to the gate electrode 110, the n-type region 114 and the p ⁺ -type base region 103a and the MOS (metal-oxide film-semiconductor insulating layer) are formed. The gate is pinched off with the gate structure, and by increasing the gate voltage, a channel is first formed at a position away from the interface with the gate insulating film 109 in the n-type region 114.

Next, a conventional method for manufacturing a silicon carbide semiconductor device will be described by taking as an example the case of manufacturing (manufacturing) the silicon carbide semiconductor device shown in FIG. 17 to 20 are cross-sectional views showing states during the manufacture of the conventional silicon carbide semiconductor device. 17 to 20 show a main process (manufacturing process until the gate insulating film 109 is formed) corresponding to FIG. 5 of Patent Document 1 below. First, as shown in FIG. 17, an n type drift region 102 is epitaxially grown on the front surface of an n ⁺⁺ type semiconductor substrate (semiconductor wafer) 101 made of silicon carbide. Next, as shown in FIG. 18, aluminum (Al) is selectively ion-implanted into the n-type drift region 102 using an ion implantation mask, so that a p ⁺ -type base is formed on the surface layer of the n-type drift region 102. The region 103a is selectively formed. The depth and impurity concentration of the p ⁺ type base region 103a are, for example, about 0.5 μm and about 2 × 10 ¹⁸ / cm ³ , respectively.

Next, as shown in FIG. 19, the p-type base region 104 doped with aluminum is epitaxially grown on the surfaces of the n-type drift region 102 and the p ⁺ -type base region 103a. The depth and impurity concentration of the p-type base region 104 are, for example, about 0.5 μm and about 5 × 10 ¹⁵ / cm ³ , respectively. The epitaxial growth temperature of the p-type base region 104 is 1600 ° C., for example. Next, as shown in FIG. 20, phosphorus (P) is selectively ion-implanted into the p-type base region 104 using an ion implantation mask, so that an n ⁺⁺ -type source is formed inside the p-type base region 104. A region 107 is selectively formed. Next, by selectively ion-implanting aluminum into the p-type base region 104 using an ion implantation mask, the p ⁺⁺ type contact region 108 is selectively formed inside the p-type base region 104.

Nitrogen (N) is selectively ion-implanted into the p-type base region 104 using an ion implantation mask, so that the n-type drift region 102 is n-typed between adjacent p ⁺ -type base regions 103a. A mold region 106 is formed, and an n-type region 105 is selectively formed in the p-type base region 104 at a depth reaching the n-type region 106. Next, after a carbon cap layer is formed on the entire surface (exposed surface) of the wafer, each ion-implanted region is formed by annealing (heat treatment) for 30 minutes at a temperature lower than the epitaxial growth temperature of the p-type base region 104 (for example, 1500 ° C.). Activate. Next, after removing the carbon cap layer, the following steps are performed by a general method to form the gate insulating film 109, the gate electrode 110, the source electrode 111, the interlayer insulating film 113, the drain electrode 112, and the like. The silicon carbide semiconductor device shown in FIG. 14 is completed.

As another method for manufacturing a silicon carbide semiconductor device, a method has been proposed in which at least a lower layer portion in contact with the drift layer in the base region is formed on the drift layer by epitaxial growth (see, for example, Patent Document 5 below). .) Moreover, the following method is proposed as another manufacturing method of a silicon carbide semiconductor device. A p ⁺ region is formed by introducing p-type impurities into the p base by ion implantation. For example, the acceleration voltage and the dose amount in ion implantation are set so that the region including the bottom surface facing the n ⁺ SiC substrate in the p ⁺ region has a high concentration region containing a p-type impurity at a higher concentration than other regions. By controlling, a p ⁺ region is formed (see, for example, Patent Document 6 below).

  Next, a circuit using the above-described silicon carbide semiconductor device (silicon carbide MOSFET) shown in FIGS. 14 to 16 as a main switch of an inverter will be described. FIG. 21 is a circuit diagram showing a circuit configuration of a main part (for one phase) of a conventional inverter. In FIG. 21, for example, a half-bridge inverter circuit in which a silicon carbide MOSFET 121a serving as a main switch for the upper arm (high potential side) and a silicon carbide MOSFET 121b serving as a main switch for the lower arm (low potential side) are connected in series. Indicates. Schottky barrier diodes (SBD) 123a and 123b are connected in antiparallel to silicon carbide MOSFETs 121a and 121b, respectively. Control is performed so that silicon carbide MOSFET 121a and silicon carbide MOSFET 121b are not simultaneously turned on.

  When the lower arm silicon carbide MOSFET 121b is turned off and the drain voltage of the lower arm silicon carbide MOSFET 121b is higher than the power supply voltage due to the parasitic inductance of the circuit, the body diode 122a of the upper arm silicon carbide MOSFET 121a and the Schottky The barrier diode 123a is energized simultaneously. Generally, a Schottky barrier diode is provided so as to have a larger current capacity and a smaller forward voltage drop than a body diode of a silicon carbide MOSFET. Therefore, after the turn-off of lower arm silicon carbide MOSFET 121b is completed, current mainly flows through upper arm Schottky barrier diode 123a.

JP 2011-023757 A Special table 2004-036655 gazette JP 2010-239152 A JP 2011-254119 A JP 2008-210848 A JP 2009-194165 A

A. Galeccas, 2 others, Recombination-enhanced extension of stacking faults in 4H-SiC pin-dion under forward bias-in-situ ndiodes under forward bias), Applied Physics Letters, (USA), American Institute of Physics, American Institute of Physics, Vol. 81, July 29, 2002, p. 29. 883-885 A. Agarwal, 3 others, A New Degradation Mechanism in High-Voltage SiC Power MOSFETs (A New Degradation Mechanism in High Power SiC Power MOSFETs), I Triple E Electron Device Letters (IE) Device Letters), July 2007, Vol. 28, No. 7, p. 587-589 S. Harada, 5 others, 8.5-mΩ · cm 2 600-V double-epitaxial MOSFETs in 4H-SiC (8.5-mΩ · cm 2 600-V Double-Epitaxial MOSFETs in 4H-SiC ), I. Triple E Electron Device Letters, May 2004, Vol. 25, No. 5, p. 292-294

However, the silicon carbide MOSFET shown in FIGS. 14 to 16 has the following problems. When the pn junction between the p ⁺ type base region (denoted by reference numeral 103a in FIGS. 14 and 16 and reference numeral 103b in FIG. 15) and the n type drift region 102 is conducted in the forward direction, the p ⁺ type base region and Carrier recombination occurs in the n-type drift region 102. It has been reported that basal plane dislocations (BPD) in the p ⁺ type base region and the n type drift region 102 progress due to the energy released by the recombination of carriers, and stacking faults (SF) are formed. (For example, see Non-Patent Document 1 above). Further, due to the growth of stacking faults, the forward voltage characteristics are deteriorated (on voltage Von is increased) due to the increase in the resistance of the drift region particularly in a bipolar element such as a PiN diode or IGBT, and the on resistance Ron is increased in the MOSFET. (For example, refer to the non-patent document 2).

In addition, as a result of extensive research by the inventors, the following has been found. The dose amount of ion implantation for forming p ⁺ type base region 103a of the silicon carbide semiconductor device shown in FIG. 14 is, for example, 1 × 10 ¹⁴ / cm ² . When p ⁺ -type base region 103a of ion implantation for forming, in order to suppress the amorphous p ⁺ -type base region 103a, the substrate is heated to, for example, about 500 ° C. temperature. The activation rate of the p ⁺ type base region 103a immediately after the ion implantation has not been clarified, but the epitaxial growth temperature when the p type base region 104 is epitaxially grown on the p ⁺ type base region 103a is 1600 as described above. It is estimated that the epitaxial growth process of the p-type base region 104 also serves as an activation process of the p ⁺ -type base region 103a.

Annealing (heat treatment) for activating the n-type regions 105, 106, the n ⁺⁺ -type source region 107 and the p ⁺⁺ -type contact region 108 is performed at a temperature lower than the epitaxial growth temperature of the p-type base region 104. However, the activation rate of the p ⁺⁺ type contact region 108 is low at an annealing temperature lower than the epitaxial growth temperature of the p type base region 104. For example, in annealing at a temperature of about 1600 ° C., for example, aluminum ion-implanted to form the p ⁺⁺ type contact region 108 is activated only about 20% of the total dose, and the p ⁺⁺ type contact region is activated. 108 cannot be made low resistance. For this reason, when the time change rate dV _DS / dt of the drain-source voltage is large, the parasitic bipolar transistor may turn on and malfunction. The p ⁺⁺ -type contact region 108 to the low resistance is obtained to be higher than 1600 ° C. The annealing temperature to activate the p ⁺⁺ -type contact region 108, in this case, the following problems Arise.

FIG. 13 schematically shows a state of the source side pn junction (pn junction 117 between the p ⁺ -type base region 103a and the n-type drift region 102) during forward conduction in FIG. 14 during forward conduction. It is sectional drawing. When the annealing temperature for activating the p ⁺⁺ type contact region 108 is higher than 1600 ° C., the silicon carbide semiconductor is sufficiently prevented from becoming amorphous during ion implantation for forming the p ⁺ type base region 103a. Or the annealing temperature for activating the p ⁺⁺ type contact region 108 overlaps with the stable growth temperature (about 1700 ° C.) of the 3C—SiC phase. For this reason, as shown in FIG. 13, a polytype having a narrower band gap than p-type periodic hexagonal (4H) silicon carbide inside the p ⁺ -type base region 103a and on the interface side with the n-type drift region 102. A region (hereinafter referred to as a low polytype region) 119 in which (polymorphism) occurs is formed. In addition, a defect layer 120 is formed in the p ⁺ type base region 103a by ion implantation on the pn junction 117 side with the n type drift region 102.

In this manner, the low polytype region 119 and the defect layer 120 are formed inside the p ⁺ type base region 103a, so that the pn junction 117 between the p ⁺ type base region 103a and the n type drift region 102 is forward. , The end of a depletion layer (illustrated by a dotted line) 118 extending from the pn junction 117 between the p ⁺ type base region 103a and the n type drift region 102 becomes the low polytype region 119 and the defect layer 120. Contact. As a result, the built-in potential Vbi of the pn junction 117 between the p ⁺ type base region 103a and the n type drift region 102 is reduced. When such a silicon carbide semiconductor device is used as the main switch of the inverter shown in FIG. 21, for example, when the silicon carbide MOSFET of the opposite arm (for example, the silicon carbide MOSFET 121b of the lower arm) is turned off, the silicon carbide of the upper arm The current flowing through the body diode 122a of the MOSFET 121a increases and becomes conductive. This promotes the growth of basal plane dislocations in the p ⁺ -type base region 103a and the n-type drift region 102, and there is a problem that long-term reliability decreases, for example, the on-resistance Ron increases.

On the other hand, in the silicon carbide semiconductor device shown in FIG. 15, since p ⁺ type base region 103b is deposited by epitaxial growth, no low polytype region is generated inside p ⁺ type base region 103b. However, in order to keep the wafer surface flat, it is desirable to deposit the p ⁺ -type base region 103b over the entire surface of the n-type drift region 102. Then, in order to deposit the p ⁺ type base region 103b on the entire surface of the n type drift region 102, the n type region 106 is formed by removing a part of the p ⁺ type base region 103b by ion implantation of an n type impurity such as nitrogen. It is formed by reversing the mold (counter doping). For example, in the case of a 1200 V breakdown voltage class element, the impurity concentration of the n-type drift region 102 is about 5.0 × 10 ¹⁵ / cm ^{3 to} 1.2 × 10 ¹⁶ / cm ³ . The impurity concentration of the p ⁺ type base region 103b is 1.0 × 10 ¹⁸ / cm ³ . The impurity concentration of the n-type region 106 is on the order of 1.0 × 10 ¹⁶ / cm ³ .

When each region is formed with such an impurity concentration, the dose required for ion implantation for inverting the p ⁺ -type base region 103b to the n-type is about 100 times the net impurity concentration of the n-type region 106. It is difficult to control the impurity concentration of the n-type region 106. As a method for solving this problem, in Patent Document 1 and Non-Patent Document 3 described above, a groove that reaches the n-type drift region 102 through the p ⁺ -type base region 103b is formed by etching. It has been proposed to epitaxially grow the n-type region 106 therein. However, in this case, since the pn junction interface between the n-type region 106 and the p ⁺ -type base region 103b becomes an interface with the side wall of the epitaxial layer, the crystal defects near the side wall of the epitaxial layer cause the quality to deteriorate. Become. Further, the flatness of the wafer surface is impaired, leading to a decrease in the yield rate in the case of a power silicon carbide semiconductor device having a large active region area.

In the buried channel type silicon carbide semiconductor device shown in FIG. 16, when the element structure is a MOSFET as shown in the drawing, the p ⁺ type base region 103a is formed by ion implantation. Therefore, the silicon carbide semiconductor device shown in FIG. The same problem occurs. In the buried channel type silicon carbide semiconductor device shown in FIG. 16, when the element structure is IGBT, built-in potential Vbi of the pn junction between p ⁺ type base region 103a and n type drift region 102 is reduced. As a result, the energy barrier against minority carriers (holes) in the n-type drift region 102 is lowered, and the holes on the front surface side easily escape to the source electrode 111 via the p ⁺ -type base region 103a. For this reason, there is a problem that an effect of accumulating minority carriers in the n-type drift region 102 is lowered and the on-voltage Von is increased.

  The present invention provides a silicon carbide semiconductor device and a method for manufacturing a silicon carbide semiconductor device capable of suppressing an increase in on-resistance in an insulated gate field effect transistor in order to eliminate the above-described problems caused by the prior art. For the purpose. An object of the present invention is to provide a silicon carbide semiconductor device and a method for manufacturing the silicon carbide semiconductor device capable of reducing the on-voltage in an insulated gate bipolar transistor in order to eliminate the above-described problems caused by the prior art. .

  In order to solve the above-described problems and achieve the object of the present invention, a silicon carbide semiconductor device according to the present invention has the following characteristics. A first conductivity type drift region made of the first conductivity type silicon carbide semiconductor is provided. A first second conductivity type semiconductor region in which a second conductivity type silicon carbide semiconductor is deposited is provided on one surface of the first conductivity type drift region. The first second conductivity type impurity is selectively introduced into a surface layer of the first second conductivity type semiconductor region opposite to the first conductivity type drift region side. A second second conductivity type semiconductor region having a lower resistivity than the conductivity type semiconductor region is provided. A first first conductivity type semiconductor region that penetrates the first second conductivity type semiconductor region in the depth direction and reaches the first conductivity type drift region is provided. The second second conductive semiconductor on the surface of the second second conductive semiconductor region and the first first conductive semiconductor region opposite to the first conductive drift region side. There is provided a third second conductivity type semiconductor region in which a second conductivity type silicon carbide semiconductor having a higher resistivity than the region is deposited. A second first-conductivity-type semiconductor region that penetrates the third second-conductivity-type semiconductor region in the depth direction and reaches the first first-conductivity-type semiconductor region is provided. A first conductivity type source region having a resistivity lower than that of the first conductivity type drift region is selectively provided inside the third second conductivity type semiconductor region, apart from the second first conductivity type semiconductor region. Is provided. Sandwiched between the second first conductive type semiconductor region and the first conductive type source region on the surface of the second first conductive type semiconductor region and the third second conductive type semiconductor region. A gate electrode is provided on the surface of the part via a gate insulating film. A source electrode in contact with the first conductivity type source region and the third second conductivity type semiconductor region is provided. A first conductivity type drain region made of a first conductivity type silicon carbide semiconductor having a resistivity lower than that of the first conductivity type drift region is provided on the other surface of the first conductivity type drift region. A drain electrode in contact with the first conductivity type drain region is provided.

  In order to solve the above-described problems and achieve the object of the present invention, a silicon carbide semiconductor device according to the present invention has the following characteristics. A first conductivity type drift region made of the first conductivity type silicon carbide semiconductor is provided. A first second conductivity type semiconductor region in which a second conductivity type silicon carbide semiconductor is deposited is provided on one surface of the first conductivity type drift region. The first second conductivity type impurity is selectively introduced into a surface layer of the first second conductivity type semiconductor region opposite to the first conductivity type drift region side. A second second conductivity type semiconductor region having a lower resistivity than the conductivity type semiconductor region is provided. A first first conductivity type semiconductor region that penetrates the first second conductivity type semiconductor region in the depth direction and reaches the first conductivity type drift region is provided. The second second conductive semiconductor on the surface of the second second conductive semiconductor region and the first first conductive semiconductor region opposite to the first conductive drift region side. There is provided a third second conductivity type semiconductor region in which a second conductivity type silicon carbide semiconductor having a higher resistivity than the region is deposited. A second first-conductivity-type semiconductor region that penetrates the third second-conductivity-type semiconductor region in the depth direction and reaches the first first-conductivity-type semiconductor region is provided. A first conductivity type emitter region having a resistivity lower than that of the first conductivity type drift region is selectively provided in the third second conductivity type semiconductor region, apart from the second first conductivity type semiconductor region. Is provided. Sandwiched between the second first-conductivity-type semiconductor region and the first-conductivity-type emitter region on the surface of the second first-conductivity-type semiconductor region and the third second-conductivity-type semiconductor region A gate electrode is provided on the surface of the part via a gate insulating film. An emitter electrode in contact with the first conductivity type emitter region and the third second conductivity type semiconductor region is provided. A second conductivity type collector region made of a second conductivity type silicon carbide semiconductor is provided on the other surface of the first conductivity type drift region. A collector electrode in contact with the second conductivity type collector region is provided.

  In the silicon carbide semiconductor device according to the present invention as set forth in the invention described above, the first second conductivity type semiconductor region has a third direction in the depth direction across the second second conductivity type semiconductor region. It faces the two-conductivity type semiconductor region.

  In the silicon carbide semiconductor device according to the present invention as set forth in the invention described above, the first first conductivity type semiconductor region is provided apart from the second second conductivity type semiconductor region. The second conductivity type semiconductor region surrounds the first second conductivity type semiconductor region side and the first conductivity type drift region side of the second second conductivity type semiconductor region. .

  In the silicon carbide semiconductor device according to this invention, the thickness of the first second conductivity type semiconductor region is 0.3 μm or more than the thickness of the second second conductivity type semiconductor region. It is characterized by being thick.

  In the silicon carbide semiconductor device according to the present invention, in the above-described invention, the resistivity of the first second conductivity type semiconductor region is 100 times or more than the resistivity of the second second conductivity type semiconductor region. It is characterized by being expensive.

  In the silicon carbide semiconductor device according to the present invention, in the above-described invention, the first first conductivity type semiconductor region is selectively doped with a first conductivity type impurity inside the first second conductivity type semiconductor region. It is characterized by being introduced to.

  In the silicon carbide semiconductor device according to the present invention, in the above-described invention, the second first conductivity type semiconductor region is selectively doped with a first conductivity type impurity inside the third second conductivity type semiconductor region. It is characterized by being introduced to.

  According to the silicon carbide semiconductor device of the present invention, in the above-described invention, the second conductivity type contact region formed by selectively introducing a second conductivity type impurity into the third second conductivity type semiconductor region is provided. The source electrode may be in contact with the first conductivity type source region and the second conductivity type contact region.

  According to the silicon carbide semiconductor device of the present invention, in the above-described invention, the second conductivity type contact region formed by selectively introducing a second conductivity type impurity into the third second conductivity type semiconductor region is provided. Further, the emitter electrode is in contact with the first conductivity type emitter region and the second conductivity type contact region.

  In the silicon carbide semiconductor device according to the present invention, in the above-described invention, the resistivity is lower than that of the first conductivity type drift region between the second conductivity type collector region and the first conductivity type drift region. The semiconductor device further includes a first conductivity type buffer region.

  In order to solve the above-mentioned problems and achieve the object of the present invention, a method for manufacturing a silicon carbide semiconductor device according to the present invention has the following characteristics. First, a first step of depositing a first conductivity type drift region made of a silicon carbide semiconductor on the front surface of the first conductivity type silicon carbide semiconductor substrate is performed. Next, a second step of depositing a first second conductivity type semiconductor region made of a silicon carbide semiconductor on the first conductivity type drift region is performed. Next, a second conductivity type impurity is selectively introduced into the first second conductivity type semiconductor region, and a second second conductivity type semiconductor having a resistivity lower than that of the first second conductivity type semiconductor region. A third step of forming a region is performed. Next, a fourth step of forming a first first conductivity type semiconductor region that penetrates the first second conductivity type semiconductor region in the depth direction and reaches the first conductivity type drift region is performed. Next, on the second second conductivity type semiconductor region and the first first conductivity type semiconductor region, a second layer made of a silicon carbide semiconductor having a resistivity higher than that of the second second conductivity type semiconductor region. A fifth step of depositing the second conductive type semiconductor region 3 is performed. Next, a sixth step of selectively forming a first conductivity type source region having a resistivity lower than that of the first conductivity type drift region in the third second conductivity type semiconductor region is performed. Next, the second first which reaches the first first conductivity type semiconductor region away from the first conductivity type source region and penetrates the third second conductivity type semiconductor region in the depth direction. A seventh step of forming the conductive semiconductor region is performed. Next, on the surface of the second first conductivity type semiconductor region and the second first conductivity type semiconductor region and the first conductivity type source region of the third second conductivity type semiconductor region, An eighth step of forming a gate electrode on the surface of the portion sandwiched between the gate insulating film via the gate insulating film is performed. Next, a ninth step of forming a source electrode in contact with the first conductivity type source region and the third second conductivity type semiconductor region is performed. Next, a tenth step of forming a drain electrode in contact with the back surface of the first conductivity type silicon carbide semiconductor substrate is performed.

  In the method for manufacturing a silicon carbide semiconductor device according to the present invention, in the above-described invention, in the fourth step, the first conductivity type impurity is selectively introduced into the first second conductivity type semiconductor region. A first first conductivity type semiconductor region is formed.

  In the method for manufacturing a silicon carbide semiconductor device according to the present invention, in the above-described invention, in the seventh step, the first conductivity type impurity is selectively introduced into the third second conductivity type semiconductor region. A second first conductivity type semiconductor region is formed.

  In addition, the method for manufacturing a silicon carbide semiconductor device according to the present invention is introduced by the third step by the first heat treatment after the third step and the fourth step and before the fifth step in the above-described invention. The method further includes an eleventh step of activating the second conductivity type impurity and the first conductivity type impurity introduced in the fourth step.

  In addition, the method for manufacturing a silicon carbide semiconductor device according to the present invention is characterized in that, in the above-described invention, the first heat treatment is performed at a temperature of 1750 ° C. or higher and 1850 ° C. or lower in the eleventh step.

  The method for manufacturing a silicon carbide semiconductor device according to the present invention further has the following features in the above-described invention. In the sixth step, the first conductivity type source region is formed by selectively introducing a first conductivity type impurity into the third second conductivity type semiconductor region. Then, after the fifth step and before the eighth step, a twelfth step of forming a second conductivity type contact region by selectively introducing a second conductivity type impurity into the third second conductivity type semiconductor region. I do. After the sixth step and the twelfth step, the first conductivity type impurity introduced in the sixth step and the second impurity introduced in the twelfth step by a second heat treatment at a temperature lower than the temperature of the first heat treatment. A thirteenth step of activating the two conductivity type impurities is performed.

  In order to solve the above-mentioned problems and achieve the object of the present invention, a method for manufacturing a silicon carbide semiconductor device according to the present invention has the following characteristics. First, a first step of depositing a second conductivity type collector region made of a silicon carbide semiconductor on the front surface of the first conductivity type silicon carbide semiconductor substrate is performed. Next, a second step of depositing a first second conductivity type semiconductor region made of a silicon carbide semiconductor on the back surface of the first conductivity type silicon carbide semiconductor substrate is performed. Next, a second conductivity type impurity is selectively introduced into the first second conductivity type semiconductor region, and a second second conductivity type semiconductor having a resistivity lower than that of the first second conductivity type semiconductor region. A third step of forming a region is performed. Next, a fourth step of forming a first first conductivity type semiconductor region that penetrates the first second conductivity type semiconductor region in the depth direction and reaches the first conductivity type silicon carbide semiconductor substrate is performed. Next, on the second second conductivity type semiconductor region and the first first conductivity type semiconductor region, a second layer made of a silicon carbide semiconductor having a resistivity higher than that of the second second conductivity type semiconductor region. A fifth step of depositing the second conductive type semiconductor region 3 is performed. Next, a sixth step of selectively forming a first conductivity type emitter region having a resistivity lower than that of the first conductivity type silicon carbide semiconductor substrate in the third second conductivity type semiconductor region is performed. Next, the second first which reaches the first first conductivity type semiconductor region away from the first conductivity type emitter region and penetrates the third second conductivity type semiconductor region in the depth direction. A seventh step of forming the conductive semiconductor region is performed. Next, on the surface of the second first conductivity type semiconductor region and the second first conductivity type semiconductor region and the first conductivity type emitter region of the third second conductivity type semiconductor region, An eighth step of forming a gate electrode on the surface of the portion sandwiched between the gate insulating film via the gate insulating film is performed. Next, a ninth step of forming an emitter electrode in contact with the first conductivity type emitter region and the third second conductivity type semiconductor region is performed. Next, a tenth step of forming a collector electrode in contact with the second conductivity type collector region is performed.

  In the method for manufacturing a silicon carbide semiconductor device according to the present invention, in the above-described invention, in the fourth step, the first conductivity type impurity is selectively introduced into the first second conductivity type semiconductor region. A first first conductivity type semiconductor region is formed.

  In the method for manufacturing a silicon carbide semiconductor device according to the present invention, in the above-described invention, in the seventh step, the first conductivity type impurity is selectively introduced into the third second conductivity type semiconductor region. A second first conductivity type semiconductor region is formed.

  In addition, the method for manufacturing a silicon carbide semiconductor device according to the present invention is introduced by the third step by the first heat treatment after the third step and the fourth step and before the fifth step in the above-described invention. The method further includes an eleventh step of activating the second conductivity type impurity and the first conductivity type impurity introduced in the fourth step.

  In addition, the method for manufacturing a silicon carbide semiconductor device according to the present invention is characterized in that, in the above-described invention, the first heat treatment is performed at a temperature of 1750 ° C. or higher and 1850 ° C. or lower in the eleventh step.

  The method for manufacturing a silicon carbide semiconductor device according to the present invention further has the following features in the above-described invention. In the sixth step, the first conductivity type emitter region is formed by selectively introducing a first conductivity type impurity into the third second conductivity type semiconductor region. Then, after the fifth step and before the eighth step, a twelfth step of forming a second conductivity type contact region by selectively introducing a second conductivity type impurity into the third second conductivity type semiconductor region. I do. After the sixth step and the twelfth step, the first conductivity type impurity introduced in the sixth step and the second impurity introduced in the twelfth step by a second heat treatment at a temperature lower than the temperature of the first heat treatment. A thirteenth step of activating the two conductivity type impurities is performed.

  According to a method for manufacturing a silicon carbide semiconductor device according to the present invention, in the above-described invention, the first conductivity type silicon carbide semiconductor substrate includes a first conductivity type substrate made of a silicon carbide semiconductor, and the first conductivity type substrate. And a first conductivity type drift region in which a first conductivity type silicon carbide semiconductor having a higher resistivity than the first conductivity type substrate is deposited on the front surface, and in the first step, the first step The second conductivity type collector region is deposited on the one conductivity type drift region, and after the first step and before the second step, the first conductivity type silicon carbide semiconductor substrate is moved from the first conductivity type substrate side. Grinding is performed to expose the first conductivity type drift region.

  According to the method of manufacturing a silicon carbide semiconductor device according to the present invention, in the above-described invention, in the first step, the first conductivity type drift region has a lower resistivity than the first conductivity type drift region. The first conductivity type buffer region made of one conductivity type silicon carbide semiconductor is deposited, and then the second conductivity type collector region is deposited on the first conductivity type buffer region.

  According to the above-described invention, the first second conductivity type semiconductor region is deposited on the first conductivity type drift region, the second conductivity type impurity is introduced into the first second conductivity type semiconductor region, and the second conductivity type impurity is introduced. By forming the second second conductivity type semiconductor region, the second second conductivity type when the pn junction between the first second conductivity type semiconductor region and the first conductivity type drift region becomes conductive in the forward direction. The end portion of the depletion layer extending from the pn junction between the first second conductivity type semiconductor region and the first conductivity type drift region does not contact the low polytype region or the defect layer in the semiconductor region. For this reason, the built-in potential of the pn junction between the first second conductivity type semiconductor region and the first conductivity type drift region can be made substantially equal to the built-in potential determined by the band gap of silicon carbide.

  According to the silicon carbide semiconductor device and the method for manufacturing the silicon carbide semiconductor device according to the present invention, it is possible to suppress an increase in on-resistance in the insulated gate field effect transistor. According to the silicon carbide semiconductor device and the method for manufacturing the silicon carbide semiconductor device according to the present invention, there is an effect that the on-voltage can be lowered in the insulated gate bipolar transistor.

1 is a cross sectional view showing a structure of a silicon carbide semiconductor device according to a first embodiment. FIG. 2 is a cross sectional view schematically showing a state at the time of forward conduction of a pn junction on the source side of the silicon carbide semiconductor device of FIG. 1. It is sectional drawing which shows the state in the middle of manufacture of the silicon carbide semiconductor device concerning Embodiment 1. FIG. It is sectional drawing which shows the state in the middle of manufacture of the silicon carbide semiconductor device concerning Embodiment 1. FIG. It is sectional drawing which shows the state in the middle of manufacture of the silicon carbide semiconductor device concerning Embodiment 1. FIG. It is sectional drawing which shows the state in the middle of manufacture of the silicon carbide semiconductor device concerning Embodiment 1. FIG. It is sectional drawing which shows the state in the middle of manufacture of the silicon carbide semiconductor device concerning Embodiment 1. FIG. It is sectional drawing which shows the state in the middle of manufacture of the silicon carbide semiconductor device concerning Embodiment 1. FIG. 3 is a characteristic diagram showing electrical characteristics of the silicon carbide semiconductor device according to the first embodiment. FIG. FIG. 4 is a cross sectional view showing a structure of a silicon carbide semiconductor device according to a second embodiment. FIG. 7 is a cross sectional view showing a state in the middle of manufacture of the silicon carbide semiconductor device according to the second embodiment. FIG. 7 is a cross sectional view showing a state in the middle of manufacture of the silicon carbide semiconductor device according to the second embodiment. It is sectional drawing which shows typically the state at the time of the forward conduction | electrical_connection of the source side pn junction at the time of the forward conduction | electrical_connection of FIG. It is sectional drawing which shows the structure of the conventional silicon carbide semiconductor device. It is sectional drawing which shows the structure of another example of the conventional silicon carbide semiconductor device. It is sectional drawing which shows the structure of another example of the conventional silicon carbide semiconductor device. It is sectional drawing which shows the state in the middle of manufacture of the conventional silicon carbide semiconductor device. It is sectional drawing which shows the state in the middle of manufacture of the conventional silicon carbide semiconductor device. It is sectional drawing which shows the state in the middle of manufacture of the conventional silicon carbide semiconductor device. It is sectional drawing which shows the state in the middle of manufacture of the conventional silicon carbide semiconductor device. It is a circuit diagram which shows the circuit structure of the principal part (for 1 phase) of the conventional inverter.

  Exemplary embodiments of a silicon carbide semiconductor device and a method for manufacturing the silicon carbide semiconductor device according to the present invention will be explained below in detail with reference to the accompanying drawings. In the present specification and the accompanying drawings, it means that electrons or holes are majority carriers in layers and regions with n or p, respectively. Further, + and − attached to n and p mean that the impurity concentration is higher and lower than that of the layer or region where it is not attached. In the Miller index notation, “−” means a bar attached to the index immediately after that, and “−” is added before the index to indicate a negative index. Note that, in the following description of the embodiments and the accompanying drawings, the same reference numerals are given to the same components, and duplicate descriptions are omitted.

(Embodiment 1)
The structure of the silicon carbide semiconductor device according to the first embodiment will be described using a silicon carbide MOSFET having a planar gate structure as an example. FIG. 1 is a cross-sectional view showing the structure of the silicon carbide semiconductor device according to the first embodiment. FIG. 1 shows a half cell of a main part of the silicon carbide semiconductor device. The actual overall structure of the silicon carbide semiconductor device is such that the configuration of the half cell shown in FIG. 1 is continuous with both ends thereof as axes of line symmetry (the same applies to FIGS. 3 to 8 and 10 to 12). As shown in FIG. 1, in the silicon carbide semiconductor device according to the first embodiment, an n type drift region 2 made of, for example, an epitaxial layer is formed on the front surface of an n ⁺⁺ type semiconductor substrate 1 made of silicon carbide. Has been deposited. On the surface of the n type drift region 2 opposite to the n ⁺⁺ type semiconductor substrate 1 side, a p type region (first second conductivity type semiconductor region) 21 made of, for example, an epitaxial layer is deposited. Yes.

A p ⁺ type base region (second second conductivity type semiconductor region) 3 that is an ion implantation region is selectively provided on the surface layer of the p type region 21 opposite to the n type drift region 2 side. It has been. The p ⁺ type base region 3 is provided away from the pn junction between the p type region 21 and the n type drift region 2. An n-type region (first first conductivity type semiconductor region) 6 is provided in a region sandwiched between adjacent p-type regions 21. N-type region 6 is in contact with p-type region 21 and n-type drift region 2 and is provided apart from p ⁺ -type base region 3. That is, the p-type region 21 surrounds the p ⁺ -type base region 3 around the n-type region 6 side and the n-type drift region 2 side. On the surface of p-type region 21, p ⁺ -type base region 3 and n-type region 6 (surface opposite to the n-type drift region 2 side), for example, a p-type base region (third A second conductivity type semiconductor region) 4 is deposited. Inside the p-type base region 4, an n-type region (second first conductivity type semiconductor region) 5 that penetrates the p-type base region 4 in the depth direction and reaches the n-type region 6 is selectively provided. ing. The n-type regions 5 and 6 are adjacent in the depth direction and constitute a junction field effect transistor (JFET) region.

  Of the n-type regions 5 and 6 constituting the JFET region, the width of the n-type region 5 on the gate insulating film 9 side is preferably wider than the width of the n-type region 6 on the n-type drift region 2 side. The reason is that when a high voltage is applied between the drain and source by making the width of the n-type region 6 on the n-type drift region 2 side narrower than the width of the n-type region 5 on the gate insulating film 9 side. This is because the electric field around the gate insulating film 9 can be blocked by the n-type region 5, so that the electric field strength applied to the gate insulating film 9 can be reduced. On the other hand, since the width of the n-type region 6 on the n-type drift region 2 side is narrower than the width of the n-type region 5 on the gate insulating film 9 side, the n-type region 6 on the n-type drift region 2 side is easily depleted. . Therefore, in order to reduce the on-resistance Ron, it is preferable that the impurity concentration of the n-type region 6 on the n-type drift region 2 side is higher than the impurity concentration of the n-type region 5 on the gate insulating film 9 side.

In addition, an n ⁺⁺ type source region 7 and a p ⁺⁺ type contact region 8 that penetrate the p type base region 4 in the depth direction and reach the p ⁺ type base region 3 are selected inside the p type base region 4. Provided. The n ⁺⁺ type source region 7 is provided apart from the n type region 5. The p ⁺⁺ type contact region 8 is in contact with the n ⁺⁺ type source region 7 on the side opposite to the n type region 5 side. That is, the p ⁺ type base region 3 extends to the JFET region side with respect to the n ⁺⁺ type source region 7, and the p ⁺ type base region 4 includes the n ⁺⁺ type source region 7 and the n type region 5. A p ⁺ -type base region 3 is provided immediately below the sandwiched portion (on the n-type drift region 2 side). Since the p ⁺ type base region 3 is disposed immediately below the p type base region 4 (the portion sandwiched between the n ⁺⁺ type source region 7 and the n type region 5), the p type base region 4 is punched through. Can be suppressed.

From the n-type region 5 to the n ⁺⁺ -type source region 7, on the surface of the n-type region 5, and on the surface of the portion of the p-type base region 4 sandwiched between the n-type region 5 and the n ⁺⁺ -type source region 7 On the surface of a part of the n ^{+ +} type source region 7, a gate electrode 10 is provided via a gate insulating film 9. Source electrode 11 is connected to n ⁺⁺ type source region 7 and p ⁺⁺ type contact region 8 with low resistance, and is electrically insulated from gate electrode 10 by interlayer insulating film 13. A drain electrode 12 is provided on the back surface of the n ⁺⁺ type semiconductor substrate 1 serving as an n ⁺⁺ type drain region.

Next, when a gate voltage (positive voltage) higher than the threshold voltage is applied to the gate electrode 10 of the silicon carbide semiconductor device according to the first embodiment, the source side pn junction (p-type region 21 and n-type drift region 2). The state of the depletion layer extending from the pn junction between the two will be described. FIG. 2 is a cross sectional view schematically showing a state at the time of forward conduction of the pn junction on the source side of the silicon carbide semiconductor device of FIG. The basic operation of the MOSFET when conducting the pn junction 17 on the source side in the forward direction is the same as that of the conventional silicon carbide semiconductor device described above (see FIGS. 14 and 15), and thus the description thereof is omitted. As shown in FIG. 2, when activating the ion-implanted impurity for forming the p ⁺ -type base region 3 inside the p ⁺ -type base region 3, the carbonization of the four-layer periodic hexagonal crystal (4H) is performed. A region (low polytype region) 19 in which a polytype (crystal polymorph) having a narrower band gap than silicon is generated is formed. This is because, as will be described later, annealing for activating the ion-implanted impurities is performed at a temperature that overlaps, for example, the stable growth temperature (about 1700 ° C.) of the 3C—SiC phase.

Also, inside the p ⁺ -type base region 3, the defect layer 20 by ion implantation to form the p ⁺ -type base region 3 is formed. The defect layer 20 and the low polytype region 19 are provided with a p-type region 21 between the p ⁺ -type base region 3 and the n-type drift region 2, so that a pn junction (p-type region 21 on the source side) is provided. And a pn junction 17 between the n-type drift region 2 and the n-type drift region 2. For this reason, when the pn junction 17 on the source side is conducted in the forward direction, the end portion of the depletion layer (illustrated by a dotted line) 18 extending from the pn junction 17 on the source side contacts the defect layer 20 and the low polytype region 19. do not do. Therefore, the built-in potential Vbi of the source-side pn junction 17 is determined by the built-in potential due to the band gap of silicon carbide, and the source-side pn junction (p ⁺ -type base region and n-type drift region in the conventional silicon carbide semiconductor device) Between the built-in potential of the pn junction between the two.

Next, a method for manufacturing the silicon carbide semiconductor device according to the first embodiment will be described with reference to FIGS. 3 to 8 by taking as an example the case of manufacturing (manufacturing) a 1200 V breakdown voltage class silicon carbide MOSFET. FIGS. 3-8 is sectional drawing which shows the state in the middle of manufacture of the silicon carbide semiconductor device concerning Embodiment 1. FIGS. First, for example, as an initial substrate (wafer), the (0001) plane (so-called Si plane) or the (000-1) plane is inclined with respect to the crystal axis by, for example, about 4 ° to 8 ° (with an off angle). An n ⁺⁺ type semiconductor substrate 1 made of silicon carbide having a main surface as a surface is prepared. The n ⁺⁺ type semiconductor substrate 1 may be, for example, a four-layer periodic hexagonal (4H) silicon carbide single crystal substrate. The n ⁺⁺ type semiconductor substrate 1 is doped with an n type impurity such as nitrogen (N) so as to have an impurity concentration of about 5.0 × 10 ¹⁸ / cm ³ or more and 4.0 × 10 ¹⁹ / cm ³ or less, for example. Bulk substrate. The thickness of the n ⁺⁺ type semiconductor substrate 1 may be about 320 μm, for example.

Next, for example, the n ⁺⁺ type semiconductor substrate 1 is inserted into a growth furnace of a hot wall type epitaxial growth apparatus having a heat source on the side wall in the reaction furnace, and the temperature in the growth furnace is maintained at about 1600 ° C., for example. Next, hydrogen (H) gas is introduced into the growth furnace, and the surface of the n ⁺⁺ type semiconductor substrate 1 is cleaned by chemical etching with hydrogen gas. Next, monosilane (SiH ₄ ) gas and dimethyl methane (C ₃ H ₈ ) gas are introduced into the growth furnace as source gases, and, for example, 1.0 × on the front surface of the n ⁺⁺ type semiconductor substrate 1. An n buffer layer (not shown) doped with an n-type impurity such as nitrogen is epitaxially grown (deposited) so as to have an impurity concentration of about 10 ¹⁸ / cm ³ . The thickness of the n buffer layer may be, for example, about 0.5 μm or more and 1.0 μm.

Next, n-type impurities such as nitrogen are uniformly doped on the n buffer layer so that the impurity concentration is, for example, about 5.0 × 10 ¹⁵ / cm ³ or more and 1.2 × 10 ¹⁶ / cm ³ or less. The n-type drift region 2 is epitaxially grown with a thickness of, for example, about 10.0 μm or more and 12.0 μm or less. Further, on the n-type drift region 2, for example, a p-type impurity such as aluminum (Al) is added so as to have an impurity concentration of about 5.0 × 10 ¹⁵ / cm ³ or more and 1.0 × 10 ¹⁶ / cm ³ or less. The uniformly doped p-type region 21 is epitaxially grown. The impurity concentration of the p-type region 21 is preferably approximately the same as the impurity concentration of the n-type drift region 2. The thickness of the p-type region 21 is, for example, about 0.8 μm or more and about 1.0 μm, and is preferably about 0.3 μm or more thicker than the thickness of the p ⁺ -type base region 3. As a result, an epitaxial substrate (wafer) is formed in which n type drift region 2 and p type region 21 are sequentially deposited on the front surface of n ⁺⁺ type semiconductor substrate 1. The state up to here is shown in FIG.

Next, after forming an oxide film (not shown) on the p-type region 21 by the CVD (chemical vapor deposition) method, the oxide film is patterned by photolithography to form the p ⁺ -type base region 3 of the oxide film. The part corresponding to the region is removed. Next, for example, aluminum is ion-implanted into the p-type region 21 using the remaining oxide film as a mask to form the p ⁺ -type base region 3 in the surface layer of the p-type region 21. The resistivity of the p ⁺ type base region 3 is preferably set to be 100 times lower than the resistivity of the p type region 21. Specifically, the impurity concentration of the p ⁺ type base region 3 may be about 2.0 × 10 ¹⁸ / cm ³ , for example. In the ion implantation for forming the p ⁺ -type base region 3, for example, the acceleration energy is in the range of about 20 keV to 220 keV, and the total dose is 0.75 × 10 ¹⁴ / cm ^{2 to} 1.5 × 10 ^14. It is performed once or several times continuously so as to be about / cm ² or less. Further, at the time of ion implantation for forming the p ⁺ -type base region 3, in order to suppress the amorphization of the p ⁺ -type base region 3, a substrate temperature is maintained at a temperature for example of the order of 500 ° C. or higher 800 ° C. or less. Next, the remainder of the oxide film used as an ion implantation mask for forming the p ⁺ type base region 3 is removed. The state up to this point is shown in FIG.

Next, after forming an oxide film (not shown) on the p-type region 21 and the p ⁺ -type base region 3 by the CVD method, the oxide film is patterned by photolithography to form the n-type region 6 in the oxide film. The part corresponding to is removed. Next, an n-type impurity such as nitrogen is ion-implanted into the p-type region 21 using the remaining oxide film as a mask to form an n-type region 6 that penetrates the p-type region 21 and reaches the n-type drift region 2. The n-type region 6 is formed by inverting a part of the p-type region 21 to n-type by ion implantation of n-type impurities (counter doping). In the ion implantation for forming the n-type region 6, for example, the acceleration energy is set to about 150 keV to 400 keV and the dose is set to about 1.5 × 10 ¹² / cm ^{2 to} 3.5 × 10 ¹² / cm ^2. Also good. Further, at the time of ion implantation for forming the n-type region 6, the substrate temperature is maintained at a temperature of, for example, about 500 ° C. to 800 ° C. in order to suppress the amorphization of the n-type region 6. Instead of forming the n-type region 6 at this stage, the n-type region 5 and the n-type region 6 may be formed simultaneously when forming the n-type region 5 described later. Next, the remainder of the oxide film used as an ion implantation mask for forming the n-type region 6 is removed.

Next, a carbon cap layer (not shown) is formed on the entire wafer surface (exposed surface). This cap layer may be, for example, an amorphous carbon layer formed by sputtering, or a carbon layer having resistance to high temperatures formed by a method other than sputtering. Next, for example, annealing (heat treatment) is performed at a temperature of about 1750 ° C. or higher and about 1850 ° C. for 3 minutes by controlling the thermal load on the wafer at a predetermined temperature increase rate in an argon (Ar) atmosphere. By this annealing, the impurities ion-implanted for forming the p ⁺ -type base region 3 and the n-type region 6 are activated by 80% or more of the total dose. Next, after removing the cap layer by ashing, the wafer is cleaned. The state up to here is shown in FIG.

Without performing annealing for activating the p ⁺ type base region 3 and the n type region 6 at this stage, an n ⁺⁺ type source region 7, a p ⁺⁺ type contact region 8 and an n type region 5 described later are formed. In the annealing for activation, the p ⁺ type base region 3 and the n type region 6 may be activated together with the n ⁺⁺ type source region 7, the p ⁺⁺ type contact region 8 and the n type region 5.

Next, a wafer is inserted into the growth furnace of the hot wall type epitaxial growth apparatus, and the temperature in the growth furnace is maintained at about 1600 ° C., for example. Next, hydrogen gas is introduced into the growth furnace, and the wafer surface is cleaned by chemical etching with hydrogen gas. Next, monosilane gas and dimethylmethane gas are introduced into the growth furnace as a source gas, and a gas containing, for example, aluminum is introduced as an additive gas, so that a p-type base region is formed on the surfaces of the p ⁺ -type base region 3 and the n-type region 6. 4 is grown epitaxially. At this time, the p-type base region 4 is uniformly doped with a p-type impurity such as aluminum so that the impurity concentration is, for example, about 4.0 × 10 ¹⁵ / cm ³ or more and 2.0 × 10 ¹⁶ / cm ³ or less. To do. The thickness of the p-type base region 4 may be about 0.5 μm, for example. The state up to this point is shown in FIG.

Next, after forming an oxide film (not shown) on the p-type base region 4 by a deposition method or a thermal oxidation method, the oxide film is patterned by photolithography to form an n ⁺⁺ type source region 7 of the oxide film. The part corresponding to the region is removed. Next, using the remaining oxide film as a mask, an n-type impurity such as phosphorus (P) is ion-implanted into the p-type base region 4 to form an n ⁺⁺ type source region 7 inside the p-type base region 4. In the ion implantation for forming the n ⁺⁺ type source region 7, for example, the acceleration energy is in the range of about 40 keV to 250 keV, and the total dose is 3.0 × 10 ¹⁵ / cm ^{2 to} 5.0 × 10. ^{It is} performed once or a plurality of times continuously so as to be about ¹⁵ / cm ² or less. Further, at the time of ion implantation for forming the n ⁺⁺ type source region 7, in order to suppress the amorphization of n ⁺⁺ type source region 7, a substrate temperature is maintained at a temperature for example of the order of 500 ° C. or higher 800 ° C. or less . Next, the remainder of the oxide film used as an ion implantation mask for forming the n ⁺⁺ type source region 7 is removed.

Next, after forming an oxide film (not shown) on the p-type base region 4 and the n ⁺⁺ type source region 7 by a deposition method or a thermal oxidation method, the oxide film is patterned by photolithography, and the oxide film p. A portion corresponding to the formation region of the ⁺⁺ type contact region 8 is removed. Next, using the remaining oxide film as a mask, p-type impurities such as aluminum are ion-implanted into the p-type base region 4 to form a p ⁺⁺ type contact region 8 inside the p-type base region 4. In the ion implantation for forming the p ⁺⁺ type contact region 8, for example, the acceleration energy is in the range of about 20 keV to 220 keV, and the total dose is 3.0 × 10 ¹⁵ / cm ^{2 to} 5.0 × 10. ^{It is} performed once or a plurality of times continuously so as to be about ¹⁵ / cm ² or less. Further, at the time of ion implantation for forming the p ⁺⁺ type contact region 8, in order to suppress the amorphization of p ⁺⁺ type contact region 8, a substrate temperature is maintained at a temperature for example of the order of 500 ° C. or higher 800 ° C. or less . Next, the remainder of the oxide film used as an ion implantation mask for forming the p ⁺⁺ type contact region 8 is removed.

Next, after an oxide film (not shown) is formed on the p-type base region 4, the n ⁺⁺ type source region 7 and the p ⁺⁺ type contact region 8 by a deposition method or a thermal oxidation method, an oxide film is formed by photolithography. Patterning is performed to remove a portion of the oxide film corresponding to the formation region of the n-type region 5. Next, an n-type impurity such as nitrogen is ion-implanted into the p-type base region 4 using the remaining oxide film as a mask to form an n-type region 5 that reaches the n-type region 6 through the p-type base region 4. . The n-type region 5 is formed by inverting a part of the p-type base region 4 to n-type by ion implantation of n-type impurities (counter doping). In the ion implantation for forming the n-type region 5, for example, the acceleration energy is in the range of about 20 keV to 300 keV, and the total dose is 1.0 × 10 ¹² / cm ^{2 to} 2.0 × 10 ¹² / cm. Perform it once or several times continuously so that it is about ² or less. Further, at the time of ion implantation for forming the n-type region 5, the substrate temperature is maintained at a temperature of, for example, about 500 ° C. to 800 ° C. in order to suppress the amorphization of the n-type region 5. Next, the remainder of the oxide film used as an ion implantation mask for forming the n-type region 5 is removed.

Next, a carbon cap layer (not shown) is formed on the entire wafer surface (exposed surface). This cap layer may be, for example, an amorphous carbon layer formed by sputtering, or a carbon layer having resistance to high temperatures formed by a method other than sputtering. Next, for example, annealing (heat treatment) is performed at a temperature of about 1750 ° C. or higher and about 1850 ° C. for 3 minutes by controlling the thermal load on the wafer at a predetermined temperature increase rate in an argon (Ar) atmosphere. By this annealing, the ions implanted to form the n ⁺⁺ type source region 7, the p ⁺⁺ type contact region 8, and the n type region 5 are each activated by 80% or more of the total dose. Specifically, for example, the electrically active impurity concentration of the n ⁺⁺ type source region 7 is about 1.0 × 10 ²⁰ / cm ³ or more and 2.0 × 10 ²⁰ / cm ³ or less. The electrically active impurity concentration of the p ⁺⁺ type contact region 8 is about 0.5 × 10 ²⁰ / cm ^{3 to} 1.0 × 10 ²⁰ / cm ³ . The annealing for activating the n ⁺⁺ type source region 7, the p ⁺⁺ type contact region 8 and the n type region 5 is performed by setting the annealing temperature for activating the p ⁺ type base region 3 and the n type region 6. It should be done at a temperature not exceeding. Next, after removing the cap layer by ashing, the wafer is cleaned. The state up to this point is shown in FIG.

Next, the surface layer of the p-type base region 4, the n-type region 5, the n ⁺⁺ type source region 7 and the p ⁺⁺ type contact region 8 is thermally oxidized to form a gate insulating film 9 by thermal oxidation. The thickness of the gate insulating film 9 is preferably in the range of 80 nm to 150 nm, for example, based on the threshold voltage of the element. The thermal oxidation for forming the gate insulating film 9 is not particularly limited, but may be dry oxidation at a temperature of 1100 ° C. or higher and 1200 ° C. or lower in an oxygen (O ₂ ) atmosphere, for example. Next, for example, annealing is performed at a temperature of about 1300 ° C. in a nitrous oxide (N ₂ O) atmosphere or a nitric oxide (NO) atmosphere. Next, a polysilicon film doped with phosphorus at a high concentration is deposited on the gate insulating film 9 to a thickness of, for example, 0.3 μm or more and 0.6 μm or less. Next, a resist mask that covers a portion of the polysilicon film to be left as the gate electrode 10 is formed on the polysilicon film by photolithography. Next, the polysilicon film is etched by, for example, reactive ion etching or dry etching using the resist mask as a mask to form the gate electrode 10. Thereby, a MOS gate (insulated gate made of metal-oxide film-semiconductor) structure is formed on the wafer front surface (surface on the p-type region 21 side). Then, the resist mask is removed. The state up to this point is shown in FIG.

Next, an interlayer insulating film 13 covering the MOS gate structure is formed on the entire surface of the wafer with a thickness of 1 μm, for example. The interlayer insulating film 13 is, for example, a single layer film such as a BPSG (Boro Phospho Silicate Glass) film, a composite film in which an NSG (Nondoped Silicate Glass) film and a PSG (Phospho Silicate Glass) film are sequentially laminated from the wafer side, or a wafer. It may be a composite film in which an HTO (High Temperature Oxide) film and a BPSG film are sequentially laminated from the side. Next, the interlayer insulating film 13 is selectively removed by photolithography and etching, and a contact hole (not shown) exposing the gate electrode 10, and the n ⁺⁺ type source region 7 and the p ⁺⁺ type contact region 8 are exposed. Contact holes to be formed.

Next, the oxide film formed on the back surface of the wafer (the back surface of the n ⁺⁺ type semiconductor substrate 1) by the steps so far is removed. Next, a nickel (Ni) film (not shown) is deposited on the front surface of the wafer and the back surface of the wafer with a thickness of about 100 nm. Next, the nickel film is silicided by annealing for 2 minutes at a temperature of 950 ° C. or higher and 1000 ° C. or lower in an argon atmosphere to form a nickel silicide film. Thereby, an ohmic contact (electrical contact portion) between the silicon carbide semiconductor and the nickel silicide film is formed. By forming the nickel silicide film, the connection between the source electrode 11 and the n ⁺⁺ type source region 7 and the p ⁺⁺ type contact region 8 becomes low resistance. Next, an electrode pad formed by sequentially depositing, for example, a titanium nitride (TiN) film and an aluminum-silicon (AlSi) film is formed on the entire surface of the wafer so as to be embedded in each contact hole.

Next, the electrode pad is separated into a source pad and a gate pad by photolithography and etching. Next, a passivation film such as a silicon nitride film (Si ₃ N ₄ film) or a polyimide film is formed on the entire front surface of the wafer. Next, the passivation film is selectively removed by photolithography and etching to expose the source pad and the gate pad. Next, a titanium nitride film, a nickel film, and a silver (Ag) film are sequentially laminated on the entire back surface of the wafer, or a titanium nitride film, a nickel film, and a gold (Au) film are sequentially laminated. A metal laminated film is formed as the drain electrode 12. Thereafter, for example, the drain electrode 12 is sintered (sintered) at a temperature of 300 ° C. or higher and 400 ° C. or lower in a nitrogen atmosphere, whereby the silicon carbide semiconductor device shown in FIG. 1 is completed.

  FIG. 9 shows the results of verifying the body diode characteristics of a 1200 V breakdown voltage class silicon carbide MOSFET (hereinafter referred to as an example) manufactured (manufactured) according to the method for manufacturing the silicon carbide semiconductor device according to the first embodiment described above. FIG. 9 is a characteristic diagram showing electrical characteristics of the silicon carbide semiconductor device according to the first embodiment. For comparison, FIG. 9 shows a comparison of the body diode characteristics of a conventional silicon carbide MOSFET of 1200V breakdown voltage class (see FIG. 14, hereinafter referred to as a conventional example) and a Schottky barrier diode of 1200V breakdown voltage class (hereinafter referred to as SBD). The forward current-voltage (IV) characteristics are shown. The temperature during current and voltage measurement was room temperature (for example, 25 ° C.). The horizontal axis of FIG. 9 shows the source-drain voltage Vsd and the anode voltage Va of the SBD of the example and the conventional example. The vertical axis in FIG. 9 shows the source-drain current Isd and the anode current Ia of the SBD of the example and the conventional example.

As shown in FIG. 9, in the embodiment, the rising voltage of the body diode is 2.51V, which is higher than the rising voltage of 1.87V of the conventional example, and the difference from the rising voltage of SBD of 0.83V is higher than that of the conventional example. It was also confirmed that it can be increased. As described above, when the difference between the rising voltage of the body diode of the silicon carbide MOSFET and the rising voltage of the SBD is increased, for example, the silicon carbide MOSFETs 121a and 121b of the inverter shown in FIG. When the silicon carbide MOSFET of the opposite arm (for example, the silicon carbide MOSFET 121b of the lower arm) is turned off, the current flowing into the body diode 122a of the silicon carbide MOSFET 121a of the upper arm is reduced and the conduction is difficult. . For this reason, growth such as basal plane dislocation caused by carrier recombination in p ⁺ type base region 3, p type base region 4, p type region 21 and n type drift region 2 of upper arm silicon carbide MOSFET 121a is suppressed, An increase in the on-resistance Ron can be suppressed.

Further, by surrounding the p ⁺ type base region 3 on the n type region 6 side and the n type drift region 2 side by the p type region 21, the p type region 21, the n type drift region 2 and the n type which bear the breakdown voltage are surrounded. The occurrence of basal plane dislocations and low polytype regions 19 that are likely to occur in the conventional structure and the conventional process such as in Patent Documents 2 and 5 described above, for example, at the pn junction interface with the region 6 can be suppressed.

Further, when the JFET region sandwiched between the base regions is selectively formed by epitaxial growth as in Patent Document 5 (hereinafter referred to as selective epitaxial growth), the pn between the p ⁺ type base region 3 and the JFET region The junction interface becomes an interface with the sidewall of the epitaxial layer. In general, the interface with the epitaxial layer often has a low quality due to a shift in crystal orientation or the presence of facets on the surface of the epitaxial layer, and the yield rate may be reduced. Further, when the epitaxial layer is selectively formed by selective epitaxial growth, since the flatness of the wafer surface is impaired, it is necessary to remove the damaged layer on the wafer surface by mechanical polishing and wet etching after the selective epitaxial growth. For this reason, the process by selective epitaxial growth is not suitable when the thickness of the region formed by selective epitaxial growth is thin. In contrast, the present invention grows an epitaxial layer over the entire wafer surface, and does not include a step by selective epitaxial growth during the manufacturing process. For this reason, the present invention is suitable for forming a thin region, and does not cause a problem that the yield rate in the related art including a process by selective epitaxial growth is reduced. In addition, the present invention is particularly suitable for a planar gate structure with less undulation on the wafer surface.

In addition, when the conventional MOSFET structure using silicon is directly applied to a silicon carbide MOSFET as in Patent Document 6, even when no voltage is applied between the drain and the source (zero bias), silicon carbide is used. Due to this band gap, the width of the depletion layer formed at the pn junction on the source side becomes wider than when silicon is used. That is, since the p-type impurity concentration in the portion of the p-type base region sandwiched between the n-type inversion layer (channel) and the n-type drift region is low, the structure is easy to punch through. When the voltage applied between the drain and the source increases, the p-type base region easily punches through, and the breakdown voltage is lowered. On the other hand, in the present invention, since the p ⁺ type base region 3 is arranged immediately below the p type base region 4, punch-through of the p type base region 4 (channel) can be suppressed. .

As described above, according to the first embodiment, the p-type region is deposited by epitaxial growth on the n-type drift region, and the p ⁺ -type base region is formed by ion implantation inside the p-type region. When the source-side pn junction conducts in the forward direction, the end of the depletion layer extending from the source-side pn junction does not contact the low polytype region or the defect layer in the p ⁺ -type base region. For this reason, the built-in potential of the pn junction on the source side can be made substantially equal to the built-in potential determined by the band gap of silicon carbide, and can be made larger than the conventional structure. As a result, when the present invention is applied to, for example, a main switch of an inverter, the body diode of the silicon carbide MOSFET serving as the main switch can be made difficult to conduct, and an increase in on-resistance can be suppressed. Therefore, long-term reliability can be improved, leading to the spread of products using silicon carbide MOSFETs.

  Further, according to the first embodiment, the built-in potential of the source-side pn junction can be made larger than the built-in potential due to the band gap of silicon carbide, so that the source-side pn junction conducts in the reverse direction compared to the conventional structure. The leakage current can be reduced. Further, according to the first embodiment, by using silicon carbide as the semiconductor material, it is possible to achieve lower loss and higher efficiency than when silicon is used as the semiconductor material. In the case where a silicon carbide semiconductor device having a performance comparable to that of a semiconductor device using silicon is configured, the silicon carbide semiconductor device can be reduced in size.

Further, according to the first embodiment, the built-in potential of the pn junction on the source side does not depend on the ion implantation conditions and annealing conditions of the p ⁺ type base region. Therefore, the p ⁺ type base region and the JFET region are formed by ion implantation and annealing so that the p-type base region (channel) does not punch through without reducing the built-in potential of the pn junction on the source side. The n-type region on the gate insulating film side and the p ⁺⁺ type contact region can be optimized. Further, according to the first embodiment, the p-type base region and the n-type region that becomes the JFET region are formed by counter-doping into the p-type region, so that the JFET region is formed by counter-doping into the p ⁺ -type base region. Controllability of the impurity concentration in the JFET region can be improved as compared with the conventional structure (FIG. 15).

(Embodiment 2)
A structure of the silicon carbide semiconductor device according to the second embodiment will be described. FIG. 10 is a cross-sectional view showing the structure of the silicon carbide semiconductor device according to the second embodiment. The silicon carbide semiconductor device according to the second embodiment is obtained by applying the first embodiment to an IGBT. That is, the silicon carbide semiconductor device according to the second embodiment shown in FIG. 10 is a silicon carbide IGBT having a planar gate structure. Specifically, a p ⁺⁺ type collector region 31 is provided instead of the n ⁺⁺ type drain region, and an n ⁺ type buffer region 32 is provided between the p ⁺⁺ type collector region 31 and the n type drift region 2. It has been. Instead of the n ⁺⁺ type source region, the source electrode and the drain electrode, an n ⁺⁺ type emitter region 37, an emitter electrode 41 and a collector electrode 42 are provided, respectively. The other configuration of the silicon carbide semiconductor device according to the second embodiment is the same as that of the silicon carbide semiconductor device according to the first embodiment.

Next, a method for manufacturing the silicon carbide semiconductor device according to the second embodiment will be described with reference to FIGS. 11 and 12 are cross-sectional views illustrating a state in the middle of manufacturing the silicon carbide semiconductor device according to the second embodiment. First, since it is difficult to form a p-type semiconductor substrate, an n-type epitaxial layer is grown on the front surface of an n ⁺ -type substrate (first conductivity type substrate) made of, for example, silicon carbide as an initial substrate (wafer). A general n-type wafer is prepared. Next, the n ⁺ type buffer region 32 and the p ⁺⁺ type collector region 31 are epitaxially grown in order on the n type epitaxial layer by a general method. Next, after protecting the surface of the p ⁺⁺ type collector region 31, grinding is performed from the back side of the n ⁺ type substrate to the product thickness position as the silicon carbide IGBT. Thereby, for example, the n ⁺ -type substrate is completely removed, and the thickness of the n-type epitaxial layer becomes thinner than the initial thickness. Next, grinding damage on the grinding surface is removed by wet etching, for example. The n-type epitaxial layer remaining at this time becomes the n-type drift region 2. The thickness of the n-type drift region 2 depends on the withstand voltage determined based on the design conditions, but in the case of a withstand voltage class of 10 kV or more, which is advantageous to have an IGBT structure over the MOSFET structure, it is necessary to set the thickness to 130 μm or more. There is. The state up to this point is shown in FIG.

Next, the p-type region 21 is epitaxially grown on the n-type drift region 2 as in the first embodiment. Thus, an epitaxial substrate (wafer) is formed in which the p ⁺⁺ type collector region 31, the n ⁺ type buffer region 32, the n type drift region 2 and the p type region 21 are sequentially laminated. The state up to this point is shown in FIG. Next, as shown in FIGS. 4 to 8, the steps from the formation of the p ⁺ type base region 3 to the formation of the gate electrode 10 are performed in the same manner as in the first embodiment, and the wafer front surface (p type region) is formed. A MOS gate structure is formed on the surface 21 side. In the second embodiment, a p ⁺⁺ type collector region 31 and an n ⁺ type buffer region 32 are formed in place of the region indicated by reference numeral 1 in FIGS. The region indicated by reference numeral 7 in FIGS. 7 and 8 is an n ⁺⁺ type emitter region 37. Next, as in the first embodiment, an interlayer insulating film 13 is formed on the entire front surface of the wafer, contact holes are formed in the interlayer insulating film 13, and then the oxide film on the back surface of the wafer is removed.

Next, a nickel (Ni) film (not shown) is deposited with a thickness of about 100 nm on the front surface of the wafer (the surface on the MOS gate structure side). A titanium (Ti) film (not shown) is deposited to a thickness of about 100 nm on the wafer back surface (the surface of the p ⁺⁺ type collector region 31). Next, for example, the nickel film and the titanium film are silicided by annealing for 2 minutes at a temperature of 950 ° C. to 1000 ° C. in an argon atmosphere, a nickel silicide film is formed on the front surface of the wafer, and titanium is formed on the back surface of the wafer. A silicide film is formed. Thus, ohmic contacts (electrical contact portions) between the silicon carbide semiconductor and the nickel silicide film and between the silicon carbide semiconductor and the titanium silicide film are formed. By forming the nickel silicide layer, the connection between the emitter electrode 41 and the n ⁺⁺ type emitter region 37 and the p ⁺⁺ type contact region 8 becomes low resistance. Next, as in the first embodiment, an emitter pad, a gate pad, and a passivation film are formed on the front surface of the wafer, a collector electrode 42 is formed on the entire back surface of the wafer, and then the collector electrode 42 is sintered. Thus, the silicon carbide semiconductor device shown in FIG. 10 is completed.

Operation when the silicon carbide semiconductor device according to the second embodiment is switched from the off state to the on state is as follows. When a voltage higher than the threshold voltage is applied to the gate electrode 10 in a state where a voltage higher than the emitter potential is applied to the collector electrode 42 in the off state, the p-type base region 4 immediately below the gate electrode 10 is applied. The region is inverted to n-type to form an n-type inversion layer. Then, electrons are injected from the emitter electrode 41 into the n-type drift region 2 through the n ⁺⁺ -type emitter region 37, the n-type inversion layer and the n-type regions 5 and 6. When this electron injection occurs, the collector-side pn junction is forward-biased, so that holes that are minority carriers are injected from the p ⁺⁺ type collector region 31 into the n-type drift region 2. When holes are injected into the n-type drift region 2, the concentration of electrons as majority carriers increases in order to maintain the neutral conditions of carriers in the n-type drift region 2, and the resistance of the n-type drift region 2 decreases. Conductivity modulation occurs. At this time, the voltage drop due to the current flowing between the collector electrode 42 and the emitter electrode 41 is the on-voltage Von.

In the silicon carbide semiconductor device according to the second embodiment, the built-in potential Vbi of the pn junction (emitter side pn junction) between the p-type region 21 and the n-type drift region 2 is determined based on the operation principle of the IGBT. It is equal to the built-in potential determined by the band gap of the p ⁺ -type base region 3 and does not become small due to the presence of the polytype or defect layer inside the p ⁺ -type base region 3. Therefore, the energy barrier against minority carriers (holes) in the n-type drift region 2 is not reduced. For this reason, holes injected into the n-type drift region 2 from the collector side in the ON state are less likely to escape from the n-type drift region 2 to the p-type region 21 and the p ⁺ -type base region 3. As a result, holes can be accumulated on the p-type region 21 side of the n-type drift region 2 and conductivity modulation is promoted (resistance during current conduction is reduced), so that the on-voltage Von is reduced. Can do.

  As described above, according to the second embodiment, the same effect as that of the first embodiment can be obtained even when an IGBT is configured. Further, according to the second embodiment, the on-voltage can be reduced, so that conduction loss can be reduced.

As described above, the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit of the present invention. For example, the order and, inside the n ⁺⁺ type source region (or n ⁺⁺ type emitter of the p-type base region forming a p ⁺ -type base region and the JFET region inside the p-type region deposited on the n-type drift region The order of forming the (region), p ⁺⁺ type contact region and JFET region can be variously changed. The p ⁺ type base region provided on the n type drift region side of the p type base region and the p type region surrounding the p ⁺ type base region on the n type drift region side may be provided. The present invention can be applied to various MOS gate type silicon carbide semiconductor devices, for example, a silicon carbide semiconductor device having a trench gate structure. Further, the present invention can be applied to a wafer having any crystal plane orientation as a main surface. In each embodiment, the first conductivity type is n-type and the second conductivity type is p-type. However, in the present invention, the first conductivity type is p-type and the second conductivity type is n-type. It holds.

  As described above, the silicon carbide semiconductor device and the method for manufacturing the silicon carbide semiconductor device according to the present invention are useful for a power silicon carbide semiconductor device used for a main switch such as an inverter.

1 n ⁺⁺ type semiconductor substrate (n ⁺⁺ type drain region)
2 n-type drift region 3 p ⁺ type base region 4 p-type base region 5, 6 n-type region (JFET region)
7 n ⁺⁺ type source region 8 p ⁺⁺ type contact region 9 Gate insulating film 10 Gate electrode 11 Source electrode 12 Drain electrode 13 Interlayer insulating film 17 pn junction between p type region and n type drift region (pn junction on source side) )
19 Low polytype region 20 Defect layer 21 p-type region 31 p ^++- type collector region 32 n ⁺ -type buffer region 37 n ^++- type emitter region 41 emitter electrode 42 collector electrode

Claims (25)

A first conductivity type drift region made of a first conductivity type silicon carbide semiconductor;
A first second conductivity type semiconductor region in which a second conductivity type silicon carbide semiconductor is deposited on one surface of the first conductivity type drift region;
The first second conductivity type impurity is selectively introduced into a surface layer of the first second conductivity type semiconductor region opposite to the first conductivity type drift region side. A second second conductivity type semiconductor region having a lower resistivity than the conductivity type semiconductor region;
A first first conductivity type semiconductor region that penetrates through the first second conductivity type semiconductor region in a depth direction and reaches the first conductivity type drift region;
The second second conductive semiconductor on the surface of the second second conductive semiconductor region and the first first conductive semiconductor region opposite to the first conductive drift region side. A third second conductivity type semiconductor region in which a second conductivity type silicon carbide semiconductor having a higher resistivity than the region is deposited;
A second first conductivity type semiconductor region that penetrates the third second conductivity type semiconductor region in the depth direction and reaches the first first conductivity type semiconductor region;
A first conductivity having a lower resistivity than the first conductivity type drift region, which is selectively provided inside the third second conductivity type semiconductor region and apart from the second first conductivity type semiconductor region. Type source area;
Sandwiched between the second first conductive type semiconductor region and the first conductive type source region on the surface of the second first conductive type semiconductor region and the third second conductive type semiconductor region. A gate electrode provided on the surface of the part via a gate insulating film,
A source electrode in contact with the first conductivity type source region and the third second conductivity type semiconductor region;
A first conductivity type drain region made of a first conductivity type silicon carbide semiconductor having a lower resistivity than the first conductivity type drift region, provided on the other surface of the first conductivity type drift region;
A drain electrode in contact with the first conductivity type drain region;
A silicon carbide semiconductor device comprising: A first conductivity type drift region made of a first conductivity type silicon carbide semiconductor;
A first second conductivity type semiconductor region in which a second conductivity type silicon carbide semiconductor is deposited on one surface of the first conductivity type drift region;
The first second conductivity type impurity is selectively introduced into a surface layer of the first second conductivity type semiconductor region opposite to the first conductivity type drift region side. A second second conductivity type semiconductor region having a lower resistivity than the conductivity type semiconductor region;
A first first conductivity type semiconductor region that penetrates through the first second conductivity type semiconductor region in a depth direction and reaches the first conductivity type drift region;
The second second conductive semiconductor on the surface of the second second conductive semiconductor region and the first first conductive semiconductor region opposite to the first conductive drift region side. A third second conductivity type semiconductor region in which a second conductivity type silicon carbide semiconductor having a higher resistivity than the region is deposited;
A second first conductivity type semiconductor region that penetrates the third second conductivity type semiconductor region in the depth direction and reaches the first first conductivity type semiconductor region;
A first conductivity having a lower resistivity than the first conductivity type drift region, which is selectively provided inside the third second conductivity type semiconductor region and apart from the second first conductivity type semiconductor region. A mold emitter region;
Sandwiched between the second first-conductivity-type semiconductor region and the first-conductivity-type emitter region on the surface of the second first-conductivity-type semiconductor region and the third second-conductivity-type semiconductor region A gate electrode provided on the surface of the part via a gate insulating film,
An emitter electrode in contact with the first conductivity type emitter region and the third second conductivity type semiconductor region;
A second conductivity type collector region made of a second conductivity type silicon carbide semiconductor provided on the other surface of the first conductivity type drift region;
A collector electrode in contact with the second conductivity type collector region;
A silicon carbide semiconductor device comprising:   The first second conductivity type semiconductor region is opposed to the third second conductivity type semiconductor region in the depth direction with the second second conductivity type semiconductor region interposed therebetween. 2. The silicon carbide semiconductor device according to 2. The first first conductivity type semiconductor region is provided apart from the second second conductivity type semiconductor region,
The first second conductivity type semiconductor region surrounds the first second conductivity type semiconductor region side and the first conductivity type drift region side of the second second conductivity type semiconductor region. The silicon carbide semiconductor device according to claim 1, wherein the silicon carbide semiconductor device is a silicon carbide semiconductor device.   5. The thickness of the first second conductivity type semiconductor region is 0.3 μm or more thicker than the thickness of the second second conductivity type semiconductor region. The silicon carbide semiconductor device described.   6. The resistivity of the first second conductivity type semiconductor region is 100 times or more higher than the resistivity of the second second conductivity type semiconductor region. The silicon carbide semiconductor device described.   7. The first first conductivity type semiconductor region according to claim 1, wherein a first conductivity type impurity is selectively introduced into the first second conductivity type semiconductor region. The silicon carbide semiconductor device as described in any one.   8. The second first conductivity type semiconductor region, wherein a first conductivity type impurity is selectively introduced into the third second conductivity type semiconductor region. The silicon carbide semiconductor device as described in any one. A second conductivity type contact region in which a second conductivity type impurity is selectively introduced into the third second conductivity type semiconductor region;
The silicon carbide semiconductor device according to claim 1, wherein the source electrode is in contact with the first conductivity type source region and the second conductivity type contact region. A second conductivity type contact region in which a second conductivity type impurity is selectively introduced into the third second conductivity type semiconductor region;
The silicon carbide semiconductor device according to claim 2, wherein the emitter electrode is in contact with the first conductivity type emitter region and the second conductivity type contact region.   The first conductivity type buffer region having a lower resistivity than the first conductivity type drift region is further provided between the second conductivity type collector region and the first conductivity type drift region. Or the silicon carbide semiconductor device of 10. A first step of depositing a first conductivity type drift region made of a silicon carbide semiconductor on the front surface of the first conductivity type silicon carbide semiconductor substrate;
A second step of depositing a first second conductivity type semiconductor region made of a silicon carbide semiconductor on the first conductivity type drift region;
A second conductivity type impurity is selectively introduced into the first second conductivity type semiconductor region to form a second second conductivity type semiconductor region having a resistivity lower than that of the first second conductivity type semiconductor region. A third step to perform,
A fourth step of forming a first first conductivity type semiconductor region that penetrates the first second conductivity type semiconductor region in the depth direction and reaches the first conductivity type drift region;
A third third layer made of a silicon carbide semiconductor having a higher resistivity than the second second conductivity type semiconductor region is disposed on the second second conductivity type semiconductor region and the first first conductivity type semiconductor region. A fifth step of depositing a two-conductivity type semiconductor region;
A sixth step of selectively forming a first conductivity type source region having a resistivity lower than that of the first conductivity type drift region inside the third second conductivity type semiconductor region;
A second first conductivity type semiconductor that is separated from the first conductivity type source region and penetrates the third second conductivity type semiconductor region in the depth direction to reach the first first conductivity type semiconductor region. A seventh step of forming a region;
Sandwiched between the second first conductive type semiconductor region and the first conductive type source region on the surface of the second first conductive type semiconductor region and the third second conductive type semiconductor region. An eighth step of forming a gate electrode on the surface of the portion via a gate insulating film;
A ninth step of forming a source electrode in contact with the first conductivity type source region and the third second conductivity type semiconductor region;
A tenth step of forming a drain electrode in contact with the back surface of the first conductivity type silicon carbide semiconductor substrate;
The manufacturing method of the silicon carbide semiconductor device characterized by the above-mentioned.   13. The fourth step is characterized in that the first first conductivity type semiconductor region is formed by selectively introducing a first conductivity type impurity into the first second conductivity type semiconductor region. A method for manufacturing a silicon carbide semiconductor device according to claim 1.   13. The seventh step of forming the second first conductive semiconductor region by selectively introducing a first conductive impurity into the third second conductive semiconductor region in the seventh step. Or the manufacturing method of the silicon carbide semiconductor device of 13.   After the third step and the fourth step, and before the fifth step, the first conductivity type introduced by the third step and the first conductivity type introduced by the fourth step by the first heat treatment. The method for manufacturing a silicon carbide semiconductor device according to claim 12, further comprising an eleventh step of activating the impurities.   The method for manufacturing a silicon carbide semiconductor device according to claim 15, wherein in the eleventh step, the first heat treatment is performed at a temperature of 1750 ° C. or higher and 1850 ° C. or lower. In the sixth step, the first conductive type source region is formed by selectively introducing a first conductive type impurity into the third second conductive type semiconductor region,
A twelfth step of forming a second conductivity type contact region by selectively introducing a second conductivity type impurity into the third second conductivity type semiconductor region after the fifth step and before the eighth step;
After the sixth step and the twelfth step, the first conductivity type impurity introduced in the sixth step and the second impurity introduced in the twelfth step by a second heat treatment at a temperature lower than the temperature of the first heat treatment. A thirteenth step of activating two conductivity type impurities;
The method for manufacturing a silicon carbide semiconductor device according to claim 15, further comprising: A first step of depositing a second conductivity type collector region made of a silicon carbide semiconductor on the front surface of the first conductivity type silicon carbide semiconductor substrate;
A second step of depositing a first second conductivity type semiconductor region made of a silicon carbide semiconductor on the back surface of the first conductivity type silicon carbide semiconductor substrate;
A second conductivity type impurity is selectively introduced into the first second conductivity type semiconductor region to form a second second conductivity type semiconductor region having a resistivity lower than that of the first second conductivity type semiconductor region. A third step to perform,
A fourth step of forming a first first conductivity type semiconductor region that penetrates the first second conductivity type semiconductor region in a depth direction and reaches the first conductivity type silicon carbide semiconductor substrate;
A third third layer made of a silicon carbide semiconductor having a higher resistivity than the second second conductivity type semiconductor region is disposed on the second second conductivity type semiconductor region and the first first conductivity type semiconductor region. A fifth step of depositing a two-conductivity type semiconductor region;
A sixth step of selectively forming a first conductivity type emitter region having a resistivity lower than that of the first conductivity type silicon carbide semiconductor substrate in the third second conductivity type semiconductor region;
A second first conductivity type semiconductor that is separated from the first conductivity type emitter region and penetrates the third second conductivity type semiconductor region in the depth direction to reach the first first conductivity type semiconductor region. A seventh step of forming a region;
Sandwiched between the second first-conductivity-type semiconductor region and the first-conductivity-type emitter region on the surface of the second first-conductivity-type semiconductor region and the third second-conductivity-type semiconductor region An eighth step of forming a gate electrode on the surface of the portion via a gate insulating film;
A ninth step of forming an emitter electrode in contact with the first conductive type emitter region and the third second conductive type semiconductor region;
A tenth step of forming a collector electrode in contact with the second conductivity type collector region;
The manufacturing method of the silicon carbide semiconductor device characterized by the above-mentioned.   19. In the fourth step, the first first conductivity type semiconductor region is formed by selectively introducing a first conductivity type impurity into the first second conductivity type semiconductor region. A method for manufacturing a silicon carbide semiconductor device according to claim 1.   19. In the seventh step, the second first conductivity type semiconductor region is formed by selectively introducing a first conductivity type impurity into the third second conductivity type semiconductor region. Or a method for manufacturing a silicon carbide semiconductor device according to 19.   After the third step and the fourth step, and before the fifth step, the first conductivity type introduced by the third step and the first conductivity type introduced by the fourth step by the first heat treatment. The method for manufacturing a silicon carbide semiconductor device according to claim 18, further comprising an eleventh step of activating the impurities.   The method of manufacturing a silicon carbide semiconductor device according to claim 21, wherein in the eleventh step, the first heat treatment is performed at a temperature of 1750 ° C or higher and 1850 ° C or lower. In the sixth step, the first conductivity type emitter region is formed by selectively introducing a first conductivity type impurity into the third second conductivity type semiconductor region,
A twelfth step of forming a second conductivity type contact region by selectively introducing a second conductivity type impurity into the third second conductivity type semiconductor region after the fifth step and before the eighth step;
After the sixth step and the twelfth step, the first conductivity type impurity introduced in the sixth step and the second impurity introduced in the twelfth step by a second heat treatment at a temperature lower than the temperature of the first heat treatment. A thirteenth step of activating two conductivity type impurities;
The method for manufacturing a silicon carbide semiconductor device according to claim 21, further comprising: The first conductivity type silicon carbide semiconductor substrate is:
A first conductivity type substrate made of a silicon carbide semiconductor;
A first conductivity type drift region in which a first conductivity type silicon carbide semiconductor having a higher resistivity than the first conductivity type substrate is deposited on the front surface of the first conductivity type substrate;
In the first step, the second conductivity type collector region is deposited on the first conductivity type drift region,
After the first step and before the second step, the first conductivity type silicon carbide semiconductor substrate is ground from the first conductivity type substrate side to expose the first conductivity type drift region. The method for manufacturing a silicon carbide semiconductor device according to any one of claims 18 to 23.   In the first step, after depositing a first conductivity type buffer region made of a first conductivity type silicon carbide semiconductor having a resistivity lower than that of the first conductivity type drift region on the first conductivity type drift region, 25. The method of manufacturing a silicon carbide semiconductor device according to claim 24, wherein the second conductivity type collector region is deposited on the first conductivity type buffer region.

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