JP2014003384A - Frequency synchronization circuit and receiver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To ensure that, in a system having a plurality of transmitters and receivers connected thereto, frequency synchronization is performed even when discontinuity in phases of data signal occurs at transmitter switchover.SOLUTION: A frequency synchronization circuit relating to the present invention is included in one receiver 10 connected to a plurality of transmitters (not shown), in which a DEC 11 performs bit synchronization on a data signal in order to discriminate 0 and 1 of the data signal or a timestamp each time the data signal and the timestamp are input, whereby the data signal and the timestamp are received. After that, a timestamp read unit 16 reads out the value of a timestamp transmitted from each of the transmitters, and the transmission source of the timestamp is identified in the receiver 10. A time difference between a plurality of timestamps transmitted from the transmitters is measured, and a frequency difference detection unit 17 detects from the measurement result a difference in clock frequency between the transmitters and the receiver, whereby frequency synchronization is performed.

Description

  The present invention relates to a frequency synchronization circuit and a receiver that receive a time stamp.

  As a method of performing frequency synchronization in a conventional Ethernet (registered trademark) network, there is a frequency and bit synchronization method using Phase Locked Loop (PLL). FIG. 8 shows an example of a block diagram of a PLL that performs frequency synchronization and phase synchronization on a data string. The phase comparator 51 performs phase comparison between the data string and the divided internal clock, detects a phase error from the internal clock, and outputs an error signal having a pulse width proportional to the error. The filter 52 flattens an error signal having a pulse width proportional to the error and outputs it as a control signal having an amplitude proportional to the magnitude of the phase error. The Voltage Controlled Oscillator (VCO) 53 adjusts the frequency and phase of the internal clock to be output according to the input control signal. The frequency divider 54 changes the frequency by, for example, dividing the output internal clock to a frequency suitable for phase comparison. The clock output from the frequency divider 54 is input again to the phase comparator 51 for phase comparison. By a series of these loops, the frequency and phase of the internal clock are synchronized with the frequency and phase of the input data string.

  In the PLL, if the phase of the data string is constantly input to a series of loops and the frequency is constant, the feedback always operates stably and the synchronization can be performed stably. However, when discontinuity occurs in the phase even though the frequency of the data string is constant, the data string input to the phase comparator 51 and the frequency of the clock output from the frequency divider 54 are synchronized. In this case, the phase comparator 51 detects the phase shift, and the voltage for the phase synchronization is controlled in the VCO 53, so that the phase change occurs and the frequency shift occurs accordingly. There is a problem that the synchronization accuracy of the system deteriorates.

  As an example in which discontinuity occurs in the phase of the data string, for example, there is Wavelength Division Multiplexing (WDM) / Time Division Multiplexing (TDM) -PON which is considered as one candidate of the next generation PON.

  FIG. 9 shows one form of WDM / TDM-PON. There are a plurality of optical service units (OSUs) 95 corresponding to transmitters of downstream signals in an optical line terminal (OLT) 92 corresponding to a transmission / reception device in a central office, and branching is performed for each wavelength using a cyclic arrayed waveguide grating (AWG) 94. In this configuration, a data signal is transmitted to an optical network unit (ONU) 91 corresponding to a customer's device (for example, see Reference 1).

  In transmission of signals from the OLT 92 to the ONU 91 (hereinafter referred to as downlink transmission), there are a plurality of OSUs 95 corresponding to transmitters, each transmitting a data signal to the ONU 91 at a different wavelength. At this time, the operating frequency of all the OSUs 95 can be synchronized by operating all the OSUs 95 with a common clock. However, the transmission distance between the OSUs 95 and the ONUs 91 is different for each OSU 95, and transmission is performed at different wavelengths. For this reason, there is an influence of chromatic dispersion, and the propagation delay time of the data signal from each OSU 95 received by the ONU 91 is different, so that the phase of the data signal from each OSU 95 received by the ONU 91 does not necessarily match. Therefore, when the OSU 95 is switched, the frequency of the data string is constant, but the phase is discontinuous. For this reason, there is a problem that frequency synchronization and bit synchronization cannot be performed by the conventional PLL.

  Here, the problem that occurs when there is a discontinuity in the phase of the data stream has been described by taking WDM / TDM-PON downlink transmission as an example, but this problem involves transmitting a data stream between a plurality of transmitters and receivers. This is a problem that can generally occur as the transmitter switches.

  As another method of frequency synchronization, for example, there is a method of performing frequency synchronization using a time stamp such as Precision Time Protocol (PTP) (for example, see Reference 2). FIG. 10 shows exchange of time stamps when frequency synchronization is performed by PTP.

The master node stamps time stamps at times T ₁ and T ₂ of the master node at the time of transmission, and sends the respective time stamps to the slave nodes. The slave node stamps the time stamps T ₁ ′ and T ₂ ′ at the slave node at the time when the time stamps T ₁ and T ₂ are received. And the difference between T ₂ -T _1, the difference between _{T 2} '-T _1' to adjust the frequency of the internal clock to be equal.

  The above method is a frequency synchronization method that assumes that the propagation delay time of the signal between the master node and the slave node is always constant, and when the delay time between the master node and the slave node changes. In the slave node fluctuates at the time when the time stamp is received.

  When multiple transmitters corresponding to the master node are connected to the receiver corresponding to the slave node and the transmitter is switched, the signal propagation delay time with the receiver may be different for each transmitter as described above. There is a possibility that an error occurs in the synchronization accuracy in the frequency synchronization method.

  On the other hand, as a technique for performing bit synchronization for identifying 0 and 1 with respect to a data sequence having a discontinuous phase, Clock Recovery, which has been used to perform phase synchronization with an upstream data sequence of a PON, has been used. There is already a (CR) method, for example, Gated Oscillator.

  FIG. 11 shows an example of a circuit block diagram of the Gate Oscillator. In the NAND circuit, NAND is taken between Data and Data shifted in phase by 1/2 of the data time slot width T, and the rising or falling edge of the input data signal is detected. By inputting this edge to the ring oscillator, a clock that is phase-synchronized with the rising edge or falling edge of data can be generated.

Jun-ichi Kani, “Enabling Technologies for Future Scalable and Flexible WDM-PON and WDM / TDM-PON Systems”, IEEE Journal of Selected. 16, no. 5, 2010. IEEE Instrumentation and Measurement Society, “IEEE Standard for a Precise Clock Synchronization Protocol for Networked Measurement and Control E200.

  Using the CR method, bit synchronization is performed on a data sequence with a discontinuous phase to read the time stamp value, and when the phase of the data sequence is discontinuous, frequency synchronization is performed using the time stamp. There is a method to perform, but if multiple transmitters are connected to the receiver and the transmitter is switched, the delay time with the receiver may be different for each transmitter regardless of which method is used. As a result, there is a possibility that an error occurs in the synchronization accuracy in the frequency synchronization method using the time stamp described above, which has been a problem.

  The frequency synchronization circuit of the present invention includes a bit synchronization function for identifying a data signal transmitted from one or more transmitters, a function for reading a value of a time stamp transmitted from the transmitter, The function of detecting the frequency difference between the clock of the transmitter and the internal clock using the value and the reception time of each time stamp, and the frequency of the internal clock based on the detected frequency difference And a frequency function to be synchronized.

  The frequency synchronization circuit of the present invention further has a time stamp transmission source discriminating function, and in the function of detecting the frequency difference, a time stamp value of a plurality of time stamps output from the same transmitter is set. The frequency difference between the transmitter clock and the internal clock may be detected using the time difference and the time difference between the reception times of the time stamps.

  The frequency synchronization circuit of the present invention further has a time stamp transmission source discriminating function, and in the function of detecting the frequency difference, a time stamp value is calculated for a plurality of time stamps output from different transmitters. The difference in propagation delay due to the difference in the transmitter may be corrected to the time difference, and the frequency difference between the clock of the transmitter and the internal clock may be detected using the corrected time difference and the time difference between the reception times of each time stamp. .

  In the frequency synchronization circuit of the present invention, the bit synchronization function may be frequency-synchronized with an internal clock synchronized with a transmitter by the frequency synchronization function.

  In the frequency synchronization circuit of the present invention, the internal clock synchronized with the transmitter by the frequency synchronization function may be multiplied to a desired frequency and output to the outside of the receiver.

  In the frequency synchronization circuit of the present invention, in the function of detecting the frequency difference, the frequency difference may be continuously detected from the time difference of each of a plurality of time stamps sent at a predetermined interval, and the frequency deviation may be monitored. .

  In the frequency synchronization circuit of the present invention, in the function of detecting the frequency difference, the frequency of the internal clock may be controlled and synchronized again when a frequency shift is detected.

  The receiver of the present invention includes a phase synchronization unit that performs phase synchronization with a received data signal or time stamp, a transmission source determination unit that determines a transmission source of the received time stamp, and two transmissions transmitted from the transmitter. The time difference of the time stamp is measured with the clock of the transmitter and the reception clock, and the frequency difference detector that detects the frequency difference of the clock between the transmitter and the receiver from the result, and the frequency that controls the frequency of the clock of the receiver And a synchronization unit.

  The above inventions can be combined as much as possible.

  According to the present invention, in a system in which a plurality of transmitters and receivers are connected, frequency synchronization can be performed even when fluctuations occur in the delay time of a data signal when switching between transmitters.

An example of a block diagram of a receiver is shown. An example of a block diagram of DDS is shown. 2 is an example of a frequency synchronization method according to the first embodiment. 6 is a first example of a frequency synchronization method according to the second embodiment. It is a 2nd example of the frequency synchronization method which concerns on Embodiment 2. FIG. It is a 1st example of the frequency synchronization method which concerns on Embodiment 3. FIG. It is a 2nd example of the frequency synchronization method which concerns on Embodiment 3. FIG. An example of the block diagram of PLL is shown. One form of WDM / TDM-PON is shown. Time stamp exchange necessary for frequency synchronization in PTP is shown. An example of the block diagram of Gated Oscillator is shown.

  Embodiments of the present invention will be described with reference to the accompanying drawings. The embodiments described below are examples of the present invention, and the present invention is not limited to the following embodiments. In the present specification and drawings, the same reference numerals denote the same components.

  In the frequency synchronization circuit according to the present invention, in the connection of N (N is a natural number) transmitters and receivers, in order to identify data signals or time stamps 0 and 1 at the receiver, Bit synchronization is performed every time a data signal and a time stamp are input, thereby receiving the data signal and the time stamp. After that, the value of the time stamp transmitted from the transmitter is read, and the transmission source of the time stamp is determined by the receiver. The time difference between a plurality of time stamps transmitted from the transmitter is measured, and the frequency difference of the clock between the transmitter and the receiver is detected from the result, and frequency synchronization is performed.

  Here, when there are two or more time stamp transmission sources, the time difference is measured for a plurality of time stamps of the same transmission source, and the clock frequency difference between the transmitter and the receiver is calculated from the result. By measuring the delay time between each transmitter and receiver in advance, or by measuring the time difference for multiple time stamps of different transmission sources, by correcting the delay time, A method of measuring the frequency difference of the clock between the transmitter and the receiver may be used.

FIG. 1 is an example of a circuit block diagram of a receiver for carrying out the present invention.
The receiver 10 according to this embodiment includes a DEC 11 and a phase synchronization unit 22. The DEC 11 and the phase synchronization unit 22 function as a bit synchronization function for identifying a data signal transmitted from a transmitter (not shown). Data and a time stamp transmitted from a transmitter (not shown) are input to the phase synchronization unit 22. The phase synchronization unit 22 performs phase synchronization on the received data signal or time stamp. As the phase synchronization unit 22, for example, a gated oscillator can be used.

  Here, the phase synchronization unit 22 performs phase synchronization after a certain amount of time has elapsed when a phase discontinuity occurs in the data string or time stamp. The time required for this phase synchronization is preferably about several hundred ns. Using a phase-synchronized clock, a decoder (DEC) 11 composed of a D-Flip Flop identifies 0 or 1 of a data string or time stamp, and reception is started.

  The receiver 10 according to the present embodiment includes a general interface 12 and a data reading unit 13 in order to receive a data string. The data string is input to the data reading unit 13 via the general interface 12. The data reading unit 13 reads the data string and outputs it to the outside of the receiver 10.

  The receiver 10 according to the present embodiment includes a time stamp interface 14, a time stamp generation unit 15, a time stamp reading unit 16, a frequency difference detection unit 17, and a DDS 18. The time stamp interface 14 and the time stamp reading unit 16 function as a function for reading the value of the time stamp transmitted from the transmitter. The time stamp generation unit 15, the time stamp reading unit 16, and the frequency difference detection unit 17 function as a function of detecting a frequency difference. The DDS 18 functions as a frequency synchronization function that synchronizes the frequency of the internal clock 20 with the frequency of the transmitter.

  The receiver 10 receives two time stamps from the transmitter, and reads the time stamp values by the time stamp reading unit 16 through the time stamp interface 14. At the same time, the time stamp generation unit 15 generates a time stamp when the time stamp is received, and the time stamp reading unit 16 reads the time stamp generated by the time stamp generation unit 15. The time stamp reading unit 16 determines the transmission source of the time stamp and outputs a set of the transmission source and the time stamp value to the frequency difference detection unit 17.

  The frequency difference detection unit 17 calculates the difference between the two time stamps sent from the transmitter and the difference between the two time stamps generated by the time stamp generation unit 15, and calculates the difference between these differences, Detect frequency shift.

  The digital direct synthesizer (DDS) 18 is controlled using the frequency shift value detected by the frequency difference detection unit 17, and the output frequency of the DDS 18 is synchronized with the frequency of the clock of the transmitter. Here, the DDS 18 has a configuration as shown in FIG. 2, and by inputting a digital signal for controlling the output frequency from the frequency difference detection unit 17, the output frequency to the frequency dividers 19, 21, and 23 is digitally changed. It can be controlled.

  The DDS 18 includes, for example, an adder 31, a phase register 32, a sine wave table 33, a D / A converter 34, and an LPF 35. The adder 31 adds the detection result of the frequency difference detection unit 17 to the phase value from the phase register 32. The phase register 32 accumulates the output signal from the adder 31. The sine wave table 33 outputs a sine wave corresponding to the output signal from the phase register 32. The D / A converter 34 converts the sine wave from the sine wave table 33 into an analog signal. The LPF 35 flattens the output signal from the D / A converter 34.

  The output of the DDS 18 can be used as a reference clock for the counter 24 required for generating a time stamp in the receiver 10. At the same time, by inputting to the phase synchronization unit 22, the frequency of the clock output from the phase synchronization unit 22 can be synchronized with the data string. Further, the output clock of the DDS 18 may be output to the outside. When the DDS 18 is used as a reference clock in each block, if the frequency of the DDS 18 is different from the frequency desired as the reference clock of the block, the frequency is adjusted and input using the frequency dividers 19, 21, and 23. be able to.

(Embodiment 1)
FIG. 3 is an example of a frequency synchronization method according to the present embodiment. Hereinafter, the time stamp is denoted as TS.
In the present embodiment, the phase synchronization unit 22 first performs phase synchronization on the data string or TS. Thereafter, when phase discontinuity occurs, the phase synchronization unit 22 sequentially synchronizes the phases (S101).

  Thereafter, the process waits until a TS is received (S102). After receiving the TS (S103), the time stamp reading unit 16 reads the TS value and the TS transmission source (S104). Thereafter, the time stamp reading unit 16 reads the TS value in the receiver at the time of receiving the TS (S105).

  Thereafter, the time stamp reading unit 16 determines whether or not the TS has been received at least once in the past (S106), and if received, the difference between the TS values received the last two times in the past and the reception when the two TSs are received. The frequency difference detection unit 17 detects the frequency difference from the difference between the TS values in the device (S107). Thereafter, the DDS 18 performs frequency synchronization from the obtained frequency difference (S108).

(Embodiment 2)
4 and 5 are a first example and a second example of the frequency synchronization method according to the present embodiment.
These systems operate assuming TSs from a plurality of transmitters, unlike the first embodiment.
TSs input from different transmitters cannot detect an accurate frequency error simply by calculating a difference as shown in FIG. 3 due to a difference in propagation delay between the transmitter and the receiver.

  Therefore, in the first example of the frequency synchronization method according to the present embodiment shown in FIG. 4, the time stamp reading unit 16 determines whether or not the TS of the same transmission source has been received in the past instead of the above-described step S106 (S206). ) If the same transmission source TS is received, frequency synchronization is performed based on two TSs of the same transmission source. Since the same transmission source TS does not cause a change in propagation delay, an accurate frequency error can be detected.

  In the second example of the frequency synchronization method according to the present embodiment shown in FIG. 5, instead of the above-described step S107, based on the TS value received twice in the past and the TS value at the receiver when the two TSs are received. Furthermore, frequency difference detection is performed by correcting the difference in propagation delay due to the difference in transmitter (S307). Frequency synchronization is performed based on two TSs of different transmission sources, but the propagation delay between transmitters and receivers is measured in advance, and the difference in propagation delay is corrected to accurately detect the frequency difference.

(Embodiment 3)
6 and 7 are a first example and a second example of the frequency synchronization method according to the present embodiment.
In these methods, frequency error detection and synchronization are not completed once, but are continuously performed, which is different from the previous examples. Thereby, stable frequency error detection and synchronization can be performed for a long time.

  For example, in the first example of the frequency synchronization method according to the present embodiment illustrated in FIG. 6, the process proceeds to step S <b> 102 after executing step S <b> 107, and steps S <b> 102 to S <b> 107 are repeated.

  For example, in the second example of the frequency synchronization method according to the present embodiment illustrated in FIG. 7, the process proceeds to step S <b> 102 after executing step S <b> 108, and steps S <b> 102 to S <b> 108 are repeated.

  When multiple transmitters are connected to the receiver and the transmitter is switched by using the above-described method and apparatus, the delay time with the receiver may be different for each transmitter. Thus, in the frequency synchronization method using the time stamp described above, frequency synchronization can be achieved even when there is a possibility that an error occurs in the synchronization accuracy.

  The present invention can be applied to the information communication industry.

10: Receiver 11: DEC
12: General interface 13: Data reading unit 14: Time stamp interface 15: Time stamp generation unit 16: Time stamp reading unit 17: Frequency difference detection unit 18: DDS
19, 21, 23: Frequency divider 20: Internal clock 22: Phase synchronization unit 24: Counter 31: Adder 32: Phase register 33: Sine wave table 34: D / A converter 35: LPF
51: Phase comparator 52: Filter 53: VCO
54: Divider 91: ONU
92: OLT
93: Splitter 94: Circulating AWG
95: OSU

Claims (8)

A bit synchronization function for identifying data signals transmitted from one or more transmitters;
A function for reading a value of a time stamp transmitted from the transmitter;
A function of detecting a frequency difference between the clock of the transmitter and an internal clock using the value of each time stamp and the reception time of each time stamp;
Based on the detected frequency difference, a frequency synchronization function for synchronizing the frequency of the internal clock to the frequency of the transmitter;
A frequency synchronization circuit. It further has a function to determine the sender of the time stamp,
In the function of detecting the frequency difference, for a plurality of time stamps output from the same transmitter, using the time difference between the time stamp values and the time difference between the reception times of the time stamps, the clock of the transmitter and the internal time The frequency synchronization circuit according to claim 1, wherein a frequency difference with a clock is detected. It further has a function to determine the sender of the time stamp,
In the function of detecting the frequency difference, for a plurality of time stamps output from different transmitters, the difference in propagation delay due to the difference in the transmitter is corrected to the time difference between the time stamp values. 2. The frequency synchronization circuit according to claim 1, wherein a frequency difference between the clock of the transmitter and an internal clock is detected using a time difference between reception times of time stamps.   4. The frequency synchronization circuit according to claim 1, wherein the bit synchronization function is frequency-synchronized with an internal clock synchronized with a transmitter by the frequency synchronization function. 5.   5. The frequency synchronization circuit according to claim 1, wherein an internal clock synchronized with a transmitter by the frequency synchronization function is multiplied to a desired frequency and output to the outside of the receiver. In the function of detecting the frequency difference,
6. The frequency synchronization circuit according to claim 1, wherein a frequency difference is continuously detected from a time difference of each of a plurality of time stamps sent at a predetermined interval, and a frequency shift is monitored. In the function of detecting the frequency difference,
7. The frequency synchronization circuit according to claim 6, wherein when a frequency shift is detected, the frequency of the internal clock is controlled and re-synchronized. A phase synchronization unit that performs phase synchronization on the received data signal or time stamp, and
A transmission source determination unit for determining the transmission source of the received time stamp;
A frequency difference detector for measuring a time difference between two time stamps transmitted from the transmitter with a clock of the transmitter and a reception clock, and detecting a frequency difference of the clock between the transmitter and the receiver from the result;
A frequency synchronizer for controlling the frequency of the receiver clock;
A receiver comprising:

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