CN113852438A - Clock buckle plate, distributed system and clock synchronization method of distributed system - Google Patents
Clock buckle plate, distributed system and clock synchronization method of distributed system Download PDFInfo
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- CN113852438A CN113852438A CN202111106064.6A CN202111106064A CN113852438A CN 113852438 A CN113852438 A CN 113852438A CN 202111106064 A CN202111106064 A CN 202111106064A CN 113852438 A CN113852438 A CN 113852438A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0602—Systems characterised by the synchronising information used
- H04J3/0617—Systems characterised by the synchronising information used the synchronising signal being characterised by the frequency or phase
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0685—Clock or time synchronisation in a node; Intranode synchronisation
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Abstract
The embodiment of the application provides a clock buckle plate, a distributed system and a clock synchronization method of the distributed system, wherein the clock buckle plate comprises: a logic control module and a signal frequency adjusting module; the logic control module is used for receiving second clock signals sent by each service board and selecting target second clock signals from the received second clock signals; and the signal frequency adjusting module is used for adjusting the frequency of a third clock signal output to each service board according to the frequency of the target second clock signal and sending the third clock signal to each service board. The clock buckle plate adjusts the frequency of the third clock signal by using the second clock signal of the service board and sends the third clock signal to each service board, thereby realizing the same reference clock source of each service board and realizing the clock synchronization of each service board.
Description
Technical Field
The present application relates to the field of communications technologies, and in particular, to a clock buckle, a distributed system, and a distributed system clock synchronization method.
Background
With the rapid development of scientific technology, network clock synchronization technology is also continuously advanced and developed, in numerous communication systems, especially for wireless systems in telecommunication environment, in order to enable communication of each part in the system to normally operate and ensure good service quality, very strict requirements are imposed on clock synchronization, along with the continuous deepening of the IP (Internet Protocol) of mobile communication network and the evolution and development of third, fourth and fifth generation mobile communication technology, many network devices have strict requirements on network clock synchronization, and need to meet frequency synchronization while ensuring high precision, otherwise, coordination, management and control are difficult to carry out between communication systems. The clock synchronization has important significance for scenes with high bandwidth and higher real-time requirements.
The IEEE1588 protocol is widely applied and developed in the Field of communications, the message structure of the IEEE1588 protocol is relatively simple and easy to implement, and the IEEE1588 protocol has become the most common way for implementing synchronization between devices under the support of chips such as an FPGA (Field-Programmable Gate Array). The IEE1588 standard Protocol is also called PTP (precision Time Protocol), and the PTP mainly measures two variables during the process of Time synchronization, and checks the measurement of link delay for the measurement of Time deviation, and the measurement of the two variables is mainly completed by the measurement of the slave clock, and after the measurement is completed, the slave clock corrects itself according to the variables, thereby completing the synchronization between the master clock and the slave clock.
The PTP protocol can realize frequency synchronization (i.e., clock synchronization) and time synchronization, but the protocol does not explicitly define a frequency synchronization mechanism of a clock, and in related technologies, most PTP protocols are used to realize time synchronization, and frequency synchronization is ensured by devices themselves. In the related art, the PTP protocol only adjusts time synchronization, but only frequency synchronization is achieved between a master clock and a slave clock, and time synchronization is meaningful.
Disclosure of Invention
An object of the embodiments of the present application is to provide a clock buckle, a distributed system, and a clock synchronization method for a distributed system, so as to implement time synchronization. The specific technical scheme is as follows:
in a first aspect, an embodiment of the present application provides a clock buckle, including:
a logic control module and a signal frequency adjusting module;
the logic control module is used for receiving second clock signals sent by each service board and selecting target second clock signals from the received second clock signals;
and the signal frequency adjusting module is configured to adjust a frequency of a third clock signal output to each service board according to the frequency of the target second clock signal, and send the third clock signal to each service board.
In a possible implementation manner, the logic control module is specifically configured to: selecting at least two paths of target second clock signals from the received second clock signals, and sending the selected paths of target second clock signals to the signal frequency adjusting module;
the signal frequency adjusting module is configured to select one path of available target second clock signals from the paths of target second clock signals, adjust the frequency of a third clock signal output to each service board according to the frequency of the available target second clock signals, and send the third clock signal to each service board.
In one possible embodiment, the signal frequency adjustment module comprises a phase locked loop; the signal frequency adjustment module is specifically configured to: and inputting the target second clock signal into the phase-locked loop of the target second clock signal to obtain a third clock signal output by the phase-locked loop, and respectively sending the third clock signal to each service board.
In one possible implementation, the logic control module is further configured to: sending other second clock signals except the target second clock signal to the signal frequency adjusting module;
and the signal frequency adjusting module is also used for detecting the quality of the clock signal by using the other second clock signals to obtain a clock signal quality detection result.
In a possible implementation, the signal frequency adjustment module is further configured to: generating a fifth clock signal for clock interlocking and outputting the fifth clock signal to an interlocking clock buckle plate; and receiving a sixth clock signal which is sent by the interlocking clock buckle plate and is used for clock interlocking.
In a second aspect, an embodiment of the present application provides a distributed system, including:
a plurality of service boards and a clock buckle plate described in any of the present applications;
the service board is used for acquiring a first clock signal received by a designated port of the service board and sent by other equipment, performing frequency conversion on the first clock signal to obtain a second clock signal, and sending the second clock signal to the clock buckle plate; and carrying out frequency conversion on the received third clock signal to obtain a fourth clock signal, and using the fourth clock signal as a working clock signal of each port.
In a possible implementation, the service board is specifically configured to: selecting a designated port from each port of the device, wherein the designated port is a port for receiving clock signals sent by other equipment; under the condition that the designated port has a PHY chip, the service board acquires a first clock signal from the PHY chip of the designated port; and under the condition that the designated port has no PHY chip, the service board acquires a first clock signal from the MAC chip of the designated port.
In a possible implementation manner, the distributed system includes an active main control board and a standby main control board;
the main control board is provided with a first clock buckle plate, the standby main control board is provided with a second clock buckle plate, and the first clock buckle plate and the second clock buckle plate are mutually interlocked clock buckle plates;
under the condition that the main control board works normally, the first clock buckle plate sends a third clock signal to each service board;
and under the condition that the main control board is abnormal, the second clock buckle plate sends a third clock signal to each service board.
In a third aspect, an embodiment of the present application provides a distributed system clock synchronization method, which is applied to any one of the distributed systems described in the present application, and the method includes:
the method comprises the steps that a service board obtains a first clock signal sent by other equipment and received by a designated port of the service board;
the service board performs frequency conversion on the first clock signal to obtain a second clock signal, and sends the second clock signal to a clock buckle plate;
the clock buckle plate selects a target second clock signal from the received second clock signals;
the clock buckle plate adjusts the frequency of a third clock signal output to each service plate according to the frequency of the target second clock signal;
and the service board performs frequency conversion on the received third clock signal to obtain a fourth clock signal, and uses the fourth clock signal as a working clock signal of each port.
In a possible implementation manner, the acquiring, by the service board, the first clock signal sent by the other device and received by the designated port of the service board includes:
the service board selects a designated port from each port of the service board, wherein the designated port is an interface for receiving clock signals sent by other equipment;
under the condition that the designated port has a PHY chip, the service board acquires a first clock signal from the PHY chip of the designated port; and under the condition that the designated port has no PHY chip, the service board acquires a first clock signal from the MAC chip of the designated port.
In a possible implementation manner, the adjusting, by the clock buckle plate, the frequency of the third clock signal output to each service board according to the frequency of the target second clock signal includes:
and the clock buckle plate inputs the target second clock signal into a phase-locked loop of the clock buckle plate to obtain a third clock signal output by the phase-locked loop, and the third clock signal is respectively sent to each service board.
In one possible embodiment, the method further comprises:
and the clock buckle plate detects the quality of the clock signal by using other second clock signals except the target second clock signal to obtain a clock signal quality detection result.
The embodiment of the application has the following beneficial effects:
the clock buckle plate, the distributed system and the clock synchronization method of the distributed system provided by the embodiment of the application comprise: a logic control module and a signal frequency adjusting module; the logic control module is used for receiving second clock signals sent by each service board and selecting target second clock signals from the received second clock signals; and the signal frequency adjusting module is used for adjusting the frequency of a third clock signal output to each service board according to the frequency of the target second clock signal and sending the third clock signal to each service board. The clock buckle plate adjusts the frequency of the third clock signal by using the second clock signal of the service board and sends the third clock signal to each service board, thereby realizing the same reference clock source of each service board and realizing the clock synchronization of each service board. Of course, not all advantages described above need to be achieved at the same time in the practice of any one product or method of the present application.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art according to the drawings.
FIG. 1 is a first schematic diagram of a distributed system according to an embodiment of the present application;
FIG. 2 is a second schematic diagram of a distributed system according to an embodiment of the present application;
FIG. 3 is a first schematic view of a clock clasp plate according to an embodiment of the present application;
FIG. 4 is a second schematic view of a clock clasp plate according to an embodiment of the present application;
FIG. 5 is a third schematic diagram of a distributed system according to an embodiment of the present application;
fig. 6 is a schematic diagram of a distributed system clock synchronization method according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments that can be derived by one of ordinary skill in the art from the description herein are intended to be within the scope of the present disclosure.
An embodiment of the present application provides a distributed system, see fig. 1, including:
a plurality of business boards 101 and a clockwork board 102;
the service board 101 is configured to obtain a first clock signal received by a designated port of the service board, perform frequency conversion on the first clock signal to obtain a second clock signal, and send the second clock signal to the clock buckle; and carrying out frequency conversion on the received third clock signal to obtain a fourth clock signal, and using the fourth clock signal as a working clock signal of each port.
The clock buckle plate 102 is used for selecting a target second clock signal from the received second clock signals; the frequency of the third clock signal output to each service board 101 is adjusted according to the frequency of the target second clock signal.
The ports of the service board may be connected to other devices, the service board may include a plurality of ports, and for each port, the port may be connected to other devices or not, and specifically may be connected according to actual service requirements. Other devices herein may be clock testers or the like that may provide clock signals.
For a service board comprising a plurality of ports, according to default port sequencing, selecting a port with the top sequencing from all ports receiving clock signals sent by other equipment as a designated port; in one example, the ports may be sorted according to a default port, whether the ports receive clock information sent by other devices is sequentially detected, and a first detected port that receives clock information sent by other devices is used as a designated port.
The designated port may or may not include a PHY (Physical layer) chip. In a possible implementation, the service board is specifically configured to: selecting a designated port from each port of the device, wherein the designated port is a port for receiving clock signals sent by other equipment; under the condition that the designated port has a PHY chip, the service board acquires a first clock signal from the PHY chip of the designated port; in the case that the designated port has no PHY chip, the service board obtains a first clock signal from a MAC (Medium Access Control) chip of the designated port.
The PHY chip, also called physical interface transceiver, is a physical layer of the interface, and when transmitting data, the PHY chip receives the data transmitted by the MAC chip, then converts the parallel data into serial stream data, and then encodes the serial stream data according to the encoding rule of the physical layer, and converts the serial stream data into an analog signal for transmission, and the process of the PHY chip receiving data can be regarded as the reverse process of transmitting data. The MAC chip is mainly responsible for controlling a physical medium connected with a physical layer, when data is transmitted, the MAC chip firstly judges whether the data can be transmitted or not, if the data can be transmitted, the MAC chip adds control information to the data, and transmits the data and the control information to the physical layer in a specified format. When receiving data, the MAC chip firstly judges whether the received information has transmission errors, and if the received information has no errors, the MAC chip removes the control information.
The other devices may send the first clock signal to the service board through the port at a designated frequency, and the service board recovers the first clock signal from the PHY chip or the MAC chip of the port according to the frequency of the received first clock signal. And the service board performs frequency conversion on the first clock signal to obtain a second clock signal and sends the second clock signal to the clock buckle plate. The clock buckle plate receives second clock signals sent by one or more service boards, and selects at least one path of second clock signals to select a target second clock signal; and adjusting the frequency of the third clock signal output to each service board according to the frequency of the target second clock signal. And the service board performs frequency conversion on the received third clock signal to obtain a fourth clock signal, and uses the fourth clock signal as a working clock signal of each port.
The service board switches the local crystal oscillator into an on-line clock, that is, a third clock signal sent by the clock buckle is used as a reference clock source, and the service board generates a fourth clock signal to be provided to the MAC chip and/or the PHY chip through the synchronizer clock module according to the received third clock signal sent by the clock buckle and uses the fourth clock signal as a working clock signal of the MAC chip and/or the PHY chip. In one example, the synchronizer clock module may be an LMK05318 chip, and the LMK05318 chip is a high-performance network synchronizer clock module providing jitter removal, which can implement clock generation, advanced clock monitoring and failover.
In the embodiment of the application, each service board in the same distributed system takes the clock signal of the same clock buckle plate as a reference clock source, so that the reference clock sources of the service boards are the same, and the clock synchronization of the service boards is realized; and the clock signal received by the clock signal receiving module in the clock pinch plate is the clock signal of the service plate, a clock closed loop can be formed, and the clock signal is adjusted in a feedback mode, so that the clock synchronization precision is further improved.
In a possible implementation, referring to fig. 2, the distributed system includes an active main control board 103 and a standby main control board 104;
the main control board is provided with a first clock buckle plate 1021, the standby control board is provided with a second clock buckle plate 1022, and the first clock buckle plate 1021 and the second clock buckle plate 1022 are mutually interlocked clock buckle plates;
under the condition that the main control board 103 works normally, the first clock buckle 1021 sends a third clock signal to each service board 101;
when the main control board 103 is abnormal, the second clock buckle 1022 sends a third clock signal to each service board 101.
In one example, the first clock buckle plate and the second clock buckle plate can be connected through a coaxial cable; the coaxial cable has strong anti-interference performance and can prevent signal attenuation, and the first clock buckle plate and the second clock buckle plate are connected by the coaxial cable, so that the interactive clock signal between the first clock buckle plate and the second clock buckle plate can be ensured to be more accurate. In one example, the first clock buckle plate can also input BITS signals, the first clock buckle plate can also output BITS signals, clock signals of a BITS clock source are generated by special BITS clock equipment, the clock buckle plate supports two paths of input and two paths of output, the BITS clock source has the greatest advantage of highest precision, and the BITS clock source is adopted as the clock source of the first clock buckle plate to increase the accuracy of the clock signals.
In the embodiment of the application, the first clock buckle plate and the second clock buckle plate are mutually interlocked clock buckle plates, the first clock buckle plate of the main control board and the second clock buckle plate of the standby main control board are interlocked in clock, and under the condition that the main control board is abnormal, the standby main control board is switched to work.
The clock buckle in the embodiment of the present application is described below, referring to fig. 3, the clock buckle includes: a logic control module 301 and a signal frequency adjusting module 302;
a logic control module 301, configured to receive second clock signals sent by each service board, and select a target second clock signal from the received second clock signals;
and a signal frequency adjusting module 302, configured to adjust a frequency of a third clock signal output to each service board according to the frequency of the target second clock signal, and send the third clock signal to each service board.
In one example, the third clock signal is a clock signal with a specified frequency, and the specified frequency can be set in a customized manner according to actual conditions, for example, the specified frequency is set to 8 KHZ. And a logic control module in the clock buckle plate receives the second clock signal of each service board, and a signal frequency adjusting module in the clock buckle plate generates a third clock signal according to the second clock signal and sends the third clock signal with the specified frequency to each service board, wherein each service board switches the local crystal oscillator into an on-line clock, namely the clock signal sent by the clock buckle plate is used as a reference clock source, so that the reference clock sources of each service board are the same, and the clock synchronization of each service board is realized. And a clock closed loop is formed, the adjustment is carried out by adopting a feedback mode, the clock synchronization precision is improved, each service board shares one clock reference source, and the clock synchronization of each part can be realized.
The Logic control module may be a CPLD (Complex Programmable Logic Device), an ASIC (Application Specific Integrated Circuit), an FPGA (field Programmable gate array), or the like.
In a distributed system, the clock buckle may receive second clock signals of a plurality of service boards, and in a possible implementation, the logic control module is specifically configured to: selecting at least two paths of target second clock signals from the received second clock signals, and sending the selected paths of target second clock signals to a signal frequency adjusting module;
and the signal frequency adjusting module is used for selecting one path of available target second clock signal from the paths of target second clock signals, adjusting the frequency of a third clock signal output to each service board according to the frequency of the available target second clock signal, and sending the third clock signal to each service board.
In one example, the signal frequency adjustment module includes a phase locked loop; the signal frequency adjustment module is specifically configured to: and inputting the target second clock signal (specifically, the available target second clock signal when multiple paths of target second clock signals exist) into the phase-locked loop of the target second clock signal, obtaining a third clock signal output by the phase-locked loop, and respectively sending the third clock signal to each service board. The phase-locked loop is a negative feedback control system which utilizes voltage generated by phase synchronization to tune a voltage-controlled oscillator to generate target frequency, and utilizes an externally input reference signal to control the frequency and phase of an internal oscillation signal of the loop, so as to realize automatic tracking of the frequency of an output signal to the frequency of an input signal.
In one example, the signal frequency adjustment module detects a high level and a low level of an input target second clock signal (specifically, an available target second clock signal when multiple target second clock signals exist), outputs a high level third clock signal when the target second clock signal is at the high level, and outputs a low level third clock signal when the target second clock signal is at the low level.
In the embodiment of the application, the logic control module selects at least two paths of second clock signals (hereinafter referred to as target second clock signals) to send the signal frequency adjusting module, so that even if one path of target second clock signals is abnormal, a third clock signal with a specified frequency can be obtained according to other target second clock signals, and the reliability of the clock buckle plate is improved. The logic control module may randomly select a target second clock signal from the second clock signals, or preferentially select a second clock signal with a higher rank as the target second clock signal according to a preset rank, which is not specifically limited in this application.
The logic control module may receive second clock signals of the plurality of service boards, and may perform quality detection of the clock signals using the remaining second clock signals, in addition to the target second clock signal sent to the signal frequency adjustment module. In one possible implementation, the logic control module is further configured to: sending other second clock signals except the target second clock signal to a signal frequency adjusting module; and the signal frequency adjusting module is also used for detecting the quality of the clock signal by using other second clock signals to obtain a clock signal quality detection result.
The specific method for detecting the quality of the clock signal may refer to a clock signal quality detection method in the related art, and in one example, the signal quality detection module may perform pulse loss detection on the received clock signal, and perform frequency division processing on the clock signal whose pulse is not lost to obtain a quality detection clock signal after the frequency division processing; comparing the phases of the quality detection clock signals with the target second clock signal to obtain a clock signal quality detection result, for example, judging that the quality of the target second clock signal meets the quality requirement when the errors between the phases of the target second clock signal and the quality detection clock signals are smaller than a preset threshold; or when the average value of the errors between the phase of the target second clock signal and the phases of the quality detection clock signals is smaller than a preset threshold value, judging that the quality of the target second clock signal meets the quality requirement, and the like.
In one example, the signal frequency adjustment module is further configured to send a first signal to the logic control module when the quality of the target second clock signal does not meet the quality requirement, where the first signal indicates to reselect the target second clock signal; and after receiving the first signal, the logic control module reselects a target second clock signal from the acquired second clock signals of each service board and sends the target second clock signal to the signal frequency adjusting module. Therefore, the quality of the clock signal received by the signal frequency adjusting module meets the quality requirement.
In one example, the signal frequency adjusting module may further generate a seventh clock signal corresponding to another second clock signal by using a phase-locked loop, and send the seventh clock signal to the logic control module, the logic control module compares the input seventh clock signal with the output other second clock signal, and if a frequency difference between the input seventh clock signal and the output other second clock signal exceeds a threshold, it is determined that the quality of the clock signal generated by the signal frequency adjusting module does not meet the quality requirement, and an alarm may be given by a software means.
In the embodiment of the invention, the detection of the quality of the clock signal is realized, so that the accuracy of the clock signal can be improved.
In a possible implementation, the signal frequency adjustment module is further configured to: generating a fifth clock signal for clock interlocking, and outputting the fifth clock signal to an interlocking clock buckle plate; and receiving a sixth clock signal which is sent by the interlocking clock buckle plate and is used for clock interlocking.
Aiming at a scene with higher availability requirement, a standby clock buckle plate is required to be arranged for the clock buckle plate and is respectively called as a main clock buckle plate and a standby clock buckle plate, when the main clock buckle plate is abnormal, a third clock signal is sent to each service board by using the standby clock buckle plate, the main clock buckle plate and the standby clock buckle plate need to lock the clock signals, and the main clock buckle plate and the standby clock buckle plate are mutually interlocked clock buckle plates. And the signal frequency adjusting module of the current clock buckle plate sends a fifth clock signal to the interlocking clock buckle plate, and the signal frequency adjusting module of the current clock buckle plate receives a sixth clock signal output by the interlocking clock buckle plate, so that the interlocking of the clock signals of the current clock buckle plate and the interlocking clock buckle plate is realized.
In one example, the current clock buckle is a master clock buckle and the interlocking clock buckle of the current clock buckle is a standby clock buckle. Although the master clock buckle receives the sixth clock signal of the standby clock buckle, the master clock buckle still generates a third clock signal by taking the target second clock signal as the input of the phase-locked loop; and the standby clock buckle plate inputs the fifth clock signal into the phase-locked loop to generate a standby third clock signal, and when the main clock buckle plate is abnormal, the standby clock buckle plate can send the standby third clock signal to each service board in real time, so that the jumping amplitude of the third clock signal can be reduced, and the stability of the service boards is improved.
In one example, the clock signals (the fifth clock signal and the sixth clock signal) for clock interlock are the same in frequency as the clock signal (the third clock signal) sent to each service board, so that when the current clock buckle plate is abnormal, the clock signal with the specified frequency can be output to each service board by using the interlock clock buckle plate. Because the current clock buckle plate and the interlocking clock buckle plate are interlocked in a clock mode, and the phase and the frequency of the clock signals output to each service board are the same, the clock signals of each service board cannot jump before and after the clock buckle plate is switched, or the jumping amplitude of the clock signals can be reduced, so that the stability of the service boards is improved.
In a possible implementation, the signal frequency adjustment module is further configured to: generating a standby fifth clock signal for clock interlocking and outputting the standby fifth clock signal to an interlocking clock buckle plate; and receiving a standby sixth clock signal which is sent by the interlocking clock buckle plate and is used for clock interlocking.
In the embodiment of the application, the standby clock signal for clock interlocking can be transmitted and received, and when the clock signal for clock interlocking is abnormal due to the abnormality of the signal frequency adjusting module, the standby clock signal for clock interlocking can be used for realizing clock interlocking, so that the safety and the usability are further improved.
In one example, the signal frequency adjustment module may be a CPLD, an ASIC, an FPGA, or the like, and each function may be integrated on one circuit or chip, or may be different circuits or chips. In one example, the signal frequency adjustment module may be a DS31408 chip, which is a flexible high performance timing integrated circuit for various frequency conversion and frequency synthesis applications.
In an example, the signal frequency adjustment module is a DS31408 chip, for example, referring to fig. 4, the clock buckle includes a logic control module (CPLD/FPGA in the corresponding drawing) and a DS31408 chip, the CPLD/FPGA supports acquisition of 22 channels of 8KHZ second clock signals, the CPLD/FPGA selects two channels of SEC1 and SEC2 from the acquired channels of second clock signals as target second clock signals, and sends the target second clock signals to the DS31408 chip, in one example, SEC1 and SEC2 are both 8KHZ clock signals; sending the rest second clock signal SEC3 except SEC1 and SEC2 to a DS31408 chip for clock signal quality detection, wherein in one example, SEC3 is a 2MHZ clock signal; o4 is a seventh clock signal for quality detection output by the DS31408 chip of the clock buckle plate, in one example, O4 is a 2MHZ clock signal, and SEC3 and O4 are interconnected through logic to realize the quality monitoring of the clock signal; in one example, the CPLD/FPGA sends the other second clock signals of 2MHZ to the DS31408, the DS31408 chip also sends the seventh clock signal of 2MHZ to the CPLD/FPGA, the DS31408 compares the input and output clock signals, and if the frequency difference between the two exceeds the threshold, it is determined that the quality of the clock signals does not meet the quality requirement, and an alarm can be given through a software means.
O3 is a third clock signal sent to each service board by a DS31408 chip of the clock buckle plate, the DS31408 chip can comprise a phase-locked loop, and an SEC1 or an SEC2 is used as the input of the phase-locked loop to obtain a third clock signal O3; in one example, O3 is an 8KHZ clock signal. The DS31408 chip of the current clock buckle plate is connected with the interlocking clock buckle plate through the back plate, the SEC4 is a sixth clock signal which is sent to the current clock buckle plate by the interlocking clock buckle plate and used for clock interlocking, the O2 is a fifth clock signal which is sent to the interlocking clock buckle plate by the current clock buckle plate and used for clock interlocking, and in one example, the SEC4 and the O2 are both clock signals of 8 KHZ; SYNC is a standby sixth clock signal which is sent to the current clock buckle plate by the interlocking clock buckle plate and is used for clock interlocking, MFrSYNC is a standby fifth clock signal which is sent to the interlocking clock buckle plate by the current clock buckle plate and is used for clock interlocking, and in one example, SYNC and MFrSYNC are both 2KHZ clock signals; the O1 is a clock signal output by the DS31408 chip of the current clock buckle to the main control board interface board, and in one example, the O1 is a 38.88M or 8KHZ clock signal.
Referring to fig. 5, a service board in the embodiment of the present application is described below, where the service board includes a plurality of ports, a transceiver chip, a frequency conversion module, and a synchronizer clock module; the transceiver chip includes an MAC chip and may further include a PHY chip.
The frequency conversion module may be a CPLD, an FPGA, or other chips with frequency division function, and in one example, the frequency conversion module may be an N242 chip, and the N242 chip is a fractional feedback phase-locked loop and may be used as a jitter attenuator and a frequency converter.
The port of the service board can be connected with other equipment through a cable or an optical fiber and receives a first clock signal sent by the other equipment. The first clock signal received by the port can be replied from the transceiver chip corresponding to the port, and the frequency conversion module carries out frequency conversion to obtain a second clock signal.
In one example, for a service board having a PHY chip, a first clock signal is obtained from the PHY chip of the service board; and aiming at a service board without a PHY chip, acquiring a first clock signal from an MAC chip of the service board. In the embodiment of the present application, the first clock signal is recovered by selecting in a manner of switching between the MAC chip and the PHY chip according to whether the service board includes the PHY chip, and the method can be applied to different types of service boards.
The service board switches the local crystal oscillator into an on-line clock, that is, a third clock signal sent by the clock buckle is used as a reference clock source, the service board receives the third clock signal sent by the clock buckle, and generates a fourth clock signal through the synchronizer clock module to be provided to the MAC chip and/or the PHY chip, so that the fourth clock signal is used as a working clock signal of the MAC chip and/or the PHY chip. In one example, the synchronizer clock module may be an LMK05318 chip, and the LMK05318 chip is a high-performance network synchronizer clock module providing jitter removal, which can implement clock generation, advanced clock monitoring and failover.
As shown in fig. 5, the distributed system in this embodiment of the present application may further include an MPU (main control board) and a plurality of LPUs (service boards), where a port of a service board receives a first clock signal sent by another device, selects a port to which the clock signal is input, recovers the first clock signal on a PHY chip or an MAC chip corresponding to the port, and uses the port as a lock clock source, that is, uses the first clock signal recovered by the port as a clock source uploaded to the main control board; the first clock signal is subjected to frequency conversion through N242 or CPLD, a second clock signal of 8K is divided, the second clock signal is sent to CPLD or FPGA in a clock buckle plate of the main control board, the second clock signal is sent to DS31408 after being processed by the CPLD or FPGA, the DS31408 adjusts the frequency of a third clock signal output by the DS31408 according to the time when the second clock signal is input, and the third clock signal is sent to each service board. And the LMK05318 of the service board performs frequency division processing on the third clock signal to obtain a fourth clock signal, and sends the fourth clock signal to the MAC chip or the PHY chip as a working clock signal. The frequency of the working clock signal of the MAC chip or the PHY chip of each service board in the distributed system can reach a relatively stable value by repeatedly adjusting according to the process, so that the whole distributed system can achieve the condition of frequency synchronization. In addition, the clock synchronization can be performed by combining a Time adjustment function of PTP (Precision Time Protocol); in case of frequency stability, the time synchronization of PTP can converge quickly. In one example, if a plurality of distributed systems are connected through ports, clock synchronization can be achieved among the distributed systems on the basis of mutual frequency locking.
In the embodiment of the application, uplink and downlink clock signals form a closed loop, DS31408 on the clock buckle plate outputs 8KHZ clock signals to each service plate, the feedback mode is adopted for repeated adjustment, the whole system shares one clock reference source, and finally the frequency synchronization purpose is achieved.
An embodiment of the present application further provides a distributed system clock synchronization method, which is applied to any distributed system in the present application, and referring to fig. 6, the method includes:
s601, the service board acquires a first clock signal sent by other equipment and received by a designated port of the service board;
s602, the service board performs frequency conversion on the first clock signal to obtain a second clock signal, and sends the second clock signal to the clock buckle plate;
s603, the clock buckle plate selects a target second clock signal from the received second clock signals;
s604, the clock buckle plate adjusts the frequency of the third clock signal output to each service plate according to the frequency of the target second clock signal;
s605, the service board performs frequency conversion on the received third clock signal to obtain a fourth clock signal, and uses the fourth clock signal as a working clock signal of each port.
In a possible implementation manner, the acquiring, by the service board, the first clock signal sent by the other device and received by the designated port of the service board includes:
the method comprises the steps that a service board selects a designated port from each port of the service board, wherein the designated port is an interface for receiving clock signals sent by other equipment;
under the condition that the designated port has a PHY chip, the service board acquires a first clock signal from the PHY chip of the designated port; and under the condition that the designated port has no PHY chip, the service board acquires a first clock signal from the MAC chip of the designated port.
In a possible embodiment, the adjusting, by the clock buckle plate, the frequency of the third clock signal output to each service board according to the frequency of the target second clock signal includes:
and the clock buckle plate inputs the target second clock signal into the phase-locked loop of the clock buckle plate to obtain a third clock signal output by the phase-locked loop, and the third clock signal is respectively sent to each service board.
In a possible embodiment, the method further includes:
and the clock buckle plate detects the quality of the clock signal by using other second clock signals except the target second clock signal to obtain a clock signal quality detection result.
In the above embodiments, the implementation may be wholly or partially realized by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loaded and executed on a computer, cause the processes or functions described in accordance with the embodiments of the application to occur, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a network of computers, or other programmable device. The computer instructions may be stored in a computer readable storage medium or transmitted from one computer readable storage medium to another, for example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by wire (e.g., coaxial cable, fiber optic, digital subscriber line) or wirelessly (e.g., infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device, such as a server, a data center, etc., that incorporates one or more of the available media. The usable medium may be a magnetic medium (e.g., floppy Disk, hard Disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., Solid State Disk (SSD)), among others.
It should be noted that, in this document, the technical features in the various alternatives can be combined to form the scheme as long as the technical features are not contradictory, and the scheme is within the scope of the disclosure of the present application. Relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The embodiments in the present specification are described in a related manner, each embodiment focuses on differences from other embodiments, and the same and similar parts in the embodiments are referred to each other.
The above description is only for the preferred embodiment of the present application and is not intended to limit the scope of the present application. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application are included in the protection scope of the present application.
Claims (12)
1. A clock buckle, comprising:
a logic control module and a signal frequency adjusting module;
the logic control module is used for receiving second clock signals sent by each service board and selecting target second clock signals from the received second clock signals;
and the signal frequency adjusting module is configured to adjust a frequency of a third clock signal output to each service board according to the frequency of the target second clock signal, and send the third clock signal to each service board.
2. The clock buckle of claim 1, wherein the logic control module is specifically configured to: selecting at least two paths of target second clock signals from the received second clock signals, and sending the selected paths of target second clock signals to the signal frequency adjusting module;
the signal frequency adjusting module is configured to select one path of available target second clock signals from the paths of target second clock signals, adjust the frequency of a third clock signal output to each service board according to the frequency of the available target second clock signals, and send the third clock signal to each service board.
3. The clock clasp of claim 1 or 2, wherein the signal frequency adjustment module comprises a phase locked loop; the signal frequency adjustment module is specifically configured to: and inputting the target second clock signal into the phase-locked loop of the target second clock signal to obtain a third clock signal output by the phase-locked loop, and respectively sending the third clock signal to each service board.
4. The clock buckle of claim 1, wherein the logic control module is further configured to: sending other second clock signals except the target second clock signal to the signal frequency adjusting module;
and the signal frequency adjusting module is also used for detecting the quality of the clock signal by using the other second clock signals to obtain a clock signal quality detection result.
5. The clock buckle of claim 1, wherein the signal frequency adjustment module is further configured to: generating a fifth clock signal for clock interlocking and outputting the fifth clock signal to an interlocking clock buckle plate; and receiving a sixth clock signal which is sent by the interlocking clock buckle plate and is used for clock interlocking.
6. A distributed system, comprising:
a plurality of service boards and the clock gusset of any one of claims 1-5;
the service board is used for acquiring a first clock signal received by a designated port of the service board and sent by other equipment, performing frequency conversion on the first clock signal to obtain a second clock signal, and sending the second clock signal to the clock buckle plate; and carrying out frequency conversion on the received third clock signal to obtain a fourth clock signal, and using the fourth clock signal as a working clock signal of each port.
7. The system of claim 6, wherein the service board is specifically configured to: selecting a designated port from each port of the device, wherein the designated port is a port for receiving clock signals sent by other equipment; under the condition that the designated port has a PHY chip, the service board acquires a first clock signal from the PHY chip of the designated port; and under the condition that the designated port has no PHY chip, the service board acquires a first clock signal from the MAC chip of the designated port.
8. The distributed system of claim 7, wherein the distributed system comprises an active master control board and a standby master control board;
the main control board is provided with a first clock buckle plate, the standby main control board is provided with a second clock buckle plate, and the first clock buckle plate and the second clock buckle plate are mutually interlocked clock buckle plates;
under the condition that the main control board works normally, the first clock buckle plate sends a third clock signal to each service board;
and under the condition that the main control board is abnormal, the second clock buckle plate sends a third clock signal to each service board.
9. A distributed system clock synchronization method applied to the distributed system of any one of claims 6 to 8, the method comprising:
the method comprises the steps that a service board obtains a first clock signal sent by other equipment and received by a designated port of the service board;
the service board performs frequency conversion on the first clock signal to obtain a second clock signal, and sends the second clock signal to a clock buckle plate;
the clock buckle plate selects a target second clock signal from the received second clock signals;
the clock buckle plate adjusts the frequency of a third clock signal output to each service plate according to the frequency of the target second clock signal;
and the service board performs frequency conversion on the received third clock signal to obtain a fourth clock signal, and uses the fourth clock signal as a working clock signal of each port.
10. The method of claim 9, wherein the acquiring, by the service board, the first clock signal transmitted by the other device and received by the designated port of the service board comprises:
the service board selects a designated port from each port of the service board, wherein the designated port is an interface for receiving clock signals sent by other equipment;
under the condition that the designated port has a PHY chip, the service board acquires a first clock signal from the PHY chip of the designated port; and under the condition that the designated port has no PHY chip, the service board acquires a first clock signal from the MAC chip of the designated port.
11. The method of claim 9, wherein the clock gusset plate adjusting the frequency of the third clock signal output to each service plate according to the frequency of the target second clock signal comprises:
and the clock buckle plate inputs the target second clock signal into a phase-locked loop of the clock buckle plate to obtain a third clock signal output by the phase-locked loop, and the third clock signal is respectively sent to each service board.
12. The method of claim 9, further comprising:
and the clock buckle plate detects the quality of the clock signal by using other second clock signals except the target second clock signal to obtain a clock signal quality detection result.
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| CN202111106064.6A CN113852438A (en) | 2021-09-22 | 2021-09-22 | Clock buckle plate, distributed system and clock synchronization method of distributed system |
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| CN202111106064.6A CN113852438A (en) | 2021-09-22 | 2021-09-22 | Clock buckle plate, distributed system and clock synchronization method of distributed system |
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