JP2013058143A - Memory control device and memory control program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable an image processing device to surely recover without hang-up while reducing a recovery time from an energy-saving mode.SOLUTION: A memory control device monitors power supply in an energy-saving mode (100). When a voltage equal to or more than a threshold is detected, the memory control device performs control to execute normal recovery in which an image processing device recovers by initializing a memory and newly developing information without utilizing development information stored in the memory (104 to 112). When a voltage equal to or more than the threshold is not detected, the memory control device performs control to execute an energy-saving mode recovery using the development information stored in the memory (104).

Description

  The present invention relates to a memory control device and a memory control program.

  Various techniques have been proposed as a memory control device for controlling a memory such as a DRAM (Dynamic Random Access Memory) (for example, Patent Documents 1 to 3).

  In the technique described in Patent Document 1, when the SDRAM controller shifts to the power saving mode, information set in the SDRAM controller is stored in the SDRAM, and then the SDRAM shifts to the self-refresh mode and the energy saving return recognition is performed. The power is cut off after the information indicating the power saving mode is stored in the circuit. When power supply is started, it is determined whether or not the power saving mode is restored based on the information stored in the energy saving return recognition circuit, and the power supply to the entire apparatus is restored from the stopped state. If the SDRAM is initialized and the return from the power saving mode is determined, the SDRAM is released from the self-refresh mode without initializing the SDRAM, and then the information stored in the SDRAM is determined. Return processing from the power saving mode is performed.

  Further, in the technique described in Patent Document 2, when it is determined that the DRAM bus is switched from the operating state to the non-operating state, the output state of the SSTL2 interface buffer is reduced so as to reduce the amount of current flowing to the DRAM bus via the VT power supply. It has been proposed to reduce the amount of current flowing through the bus by switching to a predetermined output state.

  Furthermore, the technique described in Patent Document 3 includes a DRAM and a DRAM controller for controlling the DRAM, and the DRAM controller and the DRAM are connected by a data transmission communication line. The termination voltage supply means receives a control signal from the DRAM controller and supplies power to the data transmission communication line. When the DRAM controller cancels the refresh mode of the DRAM, the termination voltage supply means supplies power to the termination voltage supply means. It has been proposed to wait for access to the DRAM until the DRAM is in the refresh release state after the termination voltage supply means starts supplying power.

JP 2006-72476 A JP 2006-350859 A JP 2008-217890 A

  An object of this invention is to make it return reliably, without hanging up, shortening energy-saving return time.

  The image processing apparatus according to claim 1 detects a phenomenon that leads to destruction of the development information held in a memory that holds development information developed in the apparatus when shifting to an energy saving state that suppresses power consumption. When the detection means does not detect the phenomenon, the development information stored in the memory is used to perform an energy saving return to return from the energy saving state, and the phenomenon is detected by the detection means. Control means for controlling the return from the energy-saving state so as to perform a normal return in which the information is newly developed and restored without using the development information held in the memory. It is characterized by that.

  The invention according to claim 2 is characterized in that, in the invention according to claim 1, the detection means detects the phenomenon depending on whether or not the power supplied to the memory exceeds a predetermined threshold value. Yes.

  According to a third aspect of the present invention, in the first or second aspect of the present invention, the detection means includes a refresh time interval until a refresh command is output after shifting from self-refresh to auto-refresh in the memory. This phenomenon is characterized in that the phenomenon is detected depending on whether or not exceeds a predetermined threshold value.

  According to a fourth aspect of the present invention, in the invention according to any one of the first to third aspects of the present invention, the detection means may be configured to obtain a result of read / write leveling performed in the memory when returning from the energy saving state. The above-described phenomenon is detected depending on whether or not a predetermined setting range is exceeded.

  According to a fifth aspect of the present invention, a computer is caused to function as a detection unit and a control unit in the memory control device according to any one of the first to fourth aspects.

  According to the first and fifth aspects of the invention, there is an effect that it is possible to reliably return without hang-up while shortening the energy saving return time.

  According to the invention described in claims 2 to 4, there is an effect that it is possible to detect whether or not there is a possibility that information is destroyed.

It is a figure which shows schematic structure of the memory control apparatus concerning 1st Embodiment of this invention. It is a flowchart which shows an example of the flow of a process at the time of returning from an energy saving mode in the memory control apparatus concerning 1st Embodiment of this invention. It is a figure which shows schematic structure of the memory control apparatus concerning 2nd Embodiment of this invention. (A) is a figure which shows the flow of a DIMM process at the time of return from an energy saving mode, (B) is a figure which shows the refresh time interval for every temperature. It is a flowchart which shows an example of the flow of a process at the time of returning from an energy saving mode in the memory control apparatus concerning 2nd Embodiment of this invention. (A) is a figure which shows schematic structure of the memory control apparatus concerning 3rd Embodiment of this invention, (B) is a figure which shows an example of the setting value of the reference | standard of read / write leveling. It is a flowchart which shows an example of the flow of a process at the time of returning from an energy saving mode in the memory control apparatus concerning 3rd Embodiment of this invention.

  Hereinafter, an example of an embodiment of the present invention will be described in detail with reference to the drawings.

(First embodiment)
FIG. 1 is a diagram showing a schematic configuration of a memory control device 10 according to the first embodiment of the present invention.

  As shown in FIG. 1, the memory control device 10 includes a CPU 12, a DIMM (Dual Inline Memory Module) 14, an energy saving control unit 16, a power supply monitoring unit 18, and a display unit 20.

  A DIMM 14 is connected to the CPU 12. The DIMM 14 is a memory module in which memories such as a plurality of DRAMs (Dynamic Random Access Memory) are mounted on a printed circuit board, and is used as a main storage memory of the CPU 12. Note that the memory mounted on the DIMM 14 in the present embodiment will be described assuming that the DDR3 (Double Data Rate3) standard is applied as an example.

  The power monitoring unit 18 monitors the state (for example, voltage or current) of the power supplied to each memory of the DIMM 14 and outputs the monitoring result to the energy saving control unit 16.

  The energy saving control unit 16 controls the transition of the DIMM 14 to the energy saving mode and the return from the energy saving mode based on an instruction from the CPU 12. Further, in the present embodiment, the energy saving control unit 16 determines whether or not a phenomenon that leads to destruction of information stored in the DIMM 14 has occurred based on the monitoring result of the power supply monitoring unit 18, and from the power saving state. The return method is controlled.

  Specifically, the energy saving control unit 16 notifies the controller in the CPU 12 that determines the next return factor when the power supplied to the DIMM 14 deviates from a predetermined value range during the energy saving mode. Then, the next return is changed from “energy-saving return” to “normal return” and controlled to return.

  In the following description, “energy-saving return” is stored in the memory as information for returning from the energy-saving mode the deployment information deployed in the device before shifting to the energy-saving mode, and stored at the time of return. In the following description, it is assumed that the normal recovery is performed by initializing the memory and newly expanding the information without using the expansion information stored in the memory.

  Next, the operation of the memory control device according to the first embodiment of the present invention will be described. FIG. 2 is a flowchart showing an example of the flow of processing when returning from the energy saving mode in the memory control device 10 according to the first embodiment of the present invention.

  In Step 100, the power source (for example, voltage or current) in the energy saving mode is monitored by the power source monitoring unit 18, and the process proceeds to Step 102.

  In step 102, it is determined whether or not it is a return from the energy saving mode. In this determination, for example, the energy saving control unit 16 determines whether or not a return instruction is issued from the CPU 12, and if the determination is affirmative, the process proceeds to step 104, and if the determination is negative, the process proceeds to step 106. .

  In step 104, energy saving return is performed and a series of processing is completed. That is, an instruction is output to the memory controller included in the CPU 12 so that the energy saving control unit 16 returns to energy saving. Thereby, the return from the energy saving mode is performed using the development information developed in each memory of the DIMM 14, the time for re-developing the information is shortened, and the restoration time is shortened.

  On the other hand, in step 106, it is determined whether or not the voltage is equal to or higher than a threshold value. For this determination, for example, the power supply monitoring unit 18 determines whether or not the voltage supplied to the DIMM 14 is equal to or higher than a predetermined threshold value. If the determination is negative, the process returns to step 100 and the above processing is performed. If the determination is repeated and the determination is affirmative, the routine proceeds to step 108.

  In step 108, the power monitoring unit 18 notifies the energy saving control unit 16 that the threshold has been exceeded, and the process proceeds to step 110.

  In step 110, the energy saving control unit 16 switches the return method to normal return, and the process proceeds to step 112.

  In step 112, normal return is performed and the routine proceeds to step 114. That is, when the voltage becomes equal to or higher than the threshold value, an instruction is output to the memory controller included in the CPU 12 so that the energy saving control unit 16 returns to normal. As a result, each memory of the DIMM 14 is initialized and new information is developed to perform restoration. Therefore, the memory power supply is monitored, and when a phenomenon (state where the power supply voltage is equal to or higher than the threshold value) that leads to the destruction of information stored in the DIMM 14 is detected, the normal recovery is performed. A return is made.

  In step 114, the fact that the threshold value has been exceeded is counted by the energy saving control unit 16, and the process proceeds to step 116. The count result is stored in a nonvolatile memory or the like.

  In step 116, it is determined by the energy-saving control unit 16 whether or not the count value has reached the specified value. If the determination is negative, the series of processing ends, and if the determination is affirmative, the process proceeds to step 118. Transition.

  In step 118, it is notified that there is a possibility of a failure, and the series of processing ends. For example, when the energy saving control unit 16 notifies the CPU 12 that there is a possibility of malfunction of the DIMM 14, information indicating that there is a possibility of malfunction is displayed on the display unit 20.

(Second Embodiment)
Next, a memory control device according to the second embodiment of the present invention will be described. FIG. 3 is a diagram showing a schematic configuration of a memory control device according to the second embodiment of the present invention.

  In the first embodiment, the phenomenon that leads to the destruction of the information stored in the DIMM 14 is detected by monitoring the power supplied to the memory. However, in the second embodiment, the return factor is detected and the self is detected. By monitoring the time from switching from refresh to auto refresh until the refresh command is output, a phenomenon leading to information destruction is detected.

  The memory control device according to the second embodiment of the present invention includes a CPU 12, a DIMM 14, and a temperature sensor 28 as shown in FIG.

  The CPU 12 includes a memory controller 24 and a monitoring unit 26, and the DIMM 14 is connected to the memory controller 24. As described above, the DIMM 14 is a memory module in which memories such as a plurality of DRAMs (Dynamic Random Access Memory) are mounted on a printed board, and is used as a main memory of the CPU 12.

  When the DIMM 14 returns from the energy saving mode, as shown in FIG. 4 (A), the self-refresh during energy saving shifts to the energy saving return auto refresh, and then refreshes through the mode register set, read / write leveling, and calibration. Output the command. Self-refresh is a mode in which the clock is deactivated to reduce the power consumption of the device, and the refresh operation is executed using the internal refresh counter. It is effective when not accessing. In addition, the auto refresh is for refreshing the DRAM.

  In the present embodiment, the time from when the memory controller 24 starts counting until the refresh command is output at the time of shifting to the energy saving return auto refresh is counted.

  In addition, since the time (refresh time interval t) from when the transition to energy-saving return auto-refresh is output until the refresh command is output varies depending on the temperature, the temperature is measured by the temperature sensor 28 and the reference refresh for each temperature is performed. The time interval (FIG. 4B) is stored in a nonvolatile memory or the like.

  For example, the temperature sensor 28 detects the temperature of each memory mounted in the DIMM 14 or the temperature around the DIMM 14, and outputs the detection result to the monitoring unit 26 of the CPU 12.

  Then, the monitoring unit 26 of the CPU 12 reads the reference refresh time interval based on the detection result of the temperature sensor 28, and outputs it to the memory controller 24. As a result, the memory controller 24 compares the counted refresh time interval with the read reference refresh time interval to determine whether or not a phenomenon leading to the destruction of information stored in the DIMM 14 has occurred. Controls how to recover from the state.

  Specifically, the memory controller 24 controls to change the next return from “energy-saving return” to “normal return” when the refresh time interval exceeds the read reference refresh time interval.

  Next, the operation of the memory control device according to the second embodiment of the present invention will be described. FIG. 5 is a flowchart showing an example of a processing flow when returning from the energy saving mode in the memory control device according to the second embodiment of the present invention.

  In step 200, the process shifts to the energy saving mode and shifts to step 202.

  In step 202, it is determined by the memory controller 24 whether or not a return factor has been detected. If the determination is negative, the process waits until the determination is affirmed and the process proceeds to step 204.

  In step 204, the return factor is output from the memory controller 24 to the memory, and the process proceeds to step 206.

  In step 206, the memory controller 24 starts counting the refresh time interval using the return factor as a trigger, and the process proceeds to step 208.

  In step 208, it is determined by the memory controller 24 whether or not a refresh command has been issued. The process waits until the determination is affirmed and the process proceeds to step 210.

  In step 210, the count of the refresh time interval by the memory controller 24 is stopped, and the process proceeds to step 212.

  In step 212, the temperature is detected by the temperature sensor 28 and notified to the monitoring unit 26, and the process proceeds to step 214.

  In step 214, the threshold of the refresh time interval corresponding to the detected temperature is determined by the monitoring unit 26, and the process proceeds to step 216. That is, the refresh time interval corresponding to the temperature detected by the monitoring unit 26 is read and determined as the threshold value.

  In step 216, the memory controller 24 determines whether or not the count value is equal to or greater than the threshold value. If the determination is negative, the process proceeds to step 218. If the determination is affirmative, the process proceeds to step 220.

  In step 218, the process proceeds to the energy saving return sequence and the series of processes is terminated. In other words, the return from the energy saving mode is performed using the development information developed in the memory of the DIMM 14, the time for re-developing the information is shortened, and the restoration time is shortened.

  In step 220, the process returns to the normal return sequence, and the series of processes ends. That is, the recovery is performed by initializing each memory of the DIMM 14 and newly developing information. Therefore, when a phenomenon that leads to destruction of information stored in the DIMM 14 (refresh time interval exceeding a threshold value determined for each temperature) is detected based on the refresh time interval, the normal recovery is performed, so that a hang-up occurs at the time of energy saving recovery. The return is performed reliably.

(Third embodiment)
Subsequently, a memory control device according to a third embodiment of the present invention will be described. FIG. 6A is a diagram showing a schematic configuration of a memory control device according to the third embodiment of the present invention.

  In the first embodiment, a phenomenon that leads to the destruction of information stored in the DIMM 14 is detected by monitoring the power supply supplied to the memory. In the second embodiment, a recovery factor is detected and auto refresh is performed from self refresh. The phenomenon that leads to information destruction is detected by monitoring the refresh time interval from when switching to the output of the refresh command, but in the third embodiment, the read / write leveling adjustment result performed at the time of return is detected. By monitoring this, a phenomenon that leads to information destruction is detected.

  The memory control device according to the third embodiment of the present invention includes a CPU 12, a DIMM 14, and an SRAM (Static Random Access Memory) 28 as shown in FIG.

  The CPU 12 includes a memory controller 24, and the DIMM 14 is connected to the memory controller 24. As described above, the DIMM 14 is a memory module in which memories such as a plurality of DRAMs (Dynamic Random Access Memory) are mounted on a printed board, and is used as a main memory of the CPU 12.

  As shown in FIG. 4A, each memory of the DIMM 14 shifts from self-refresh during energy-saving to auto-recovery auto-refresh, as shown in FIG. 4A, and then mode register set, read / write leveling, and calibration Output a refresh command.

  In the present embodiment, the memory controller 24 acquires the read / write leveling adjustment result of each memory that is performed when the energy saving is restored.

  The read / write leveling is within a predetermined range if no problem occurs in the memory. Therefore, the reference set value of the read / write leveling is stored in a nonvolatile memory or the like. For example, as shown in FIG. 6B, a minimum value, a normal value, and a maximum value are stored in advance in a non-volatile memory as reference setting values for read / write leveling.

  Then, the memory controller reads the read / write leveling reference setting value stored in the nonvolatile memory into the SRAM 28 and compares it with the read / write leveling adjustment result at the time of energy saving recovery, and stores it in the DIMM 14. It is determined whether or not a phenomenon that leads to the destruction of information has occurred, and the method for returning from the power saving state is controlled.

  Specifically, when the read / write leveling result deviates from the read reference setting value, the memory controller 24 performs control so that the next return is changed from “energy-saving return” to “normal return”.

  Next, the operation of the memory control device according to the third embodiment of the present invention will be described. FIG. 7 is a flowchart showing an example of the flow of processing when returning from the energy saving mode in the memory control device according to the third embodiment of the present invention.

  In step 300, the process proceeds to the energy saving mode and proceeds to step 302.

  In step 302, it is determined by the memory controller 24 whether or not a return factor has been detected. If the determination is negative, the process waits until the determination is affirmed and the process proceeds to step 304.

  In step 304, it is determined whether the read / write leveling has been completed. In this determination, the memory controller 24 monitors each memory of the DIMM 14 to determine whether the read / write leveling has been completed, waits until the determination is affirmed, and proceeds to step 306.

  In step 306, the read / write leveling reference setting value stored in advance in the nonvolatile memory is read by the memory controller 24 into the SRAM 28, and the process proceeds to step 308.

  In step 308, it is determined whether the result of the read / write leveling is within a threshold value. That is, the memory controller 24 determines whether or not the read / write leveling result is within the set value of the read / write leveling machine gun. If the determination is affirmative, the process proceeds to step 310; Then, the process proceeds to step 312.

  In step 310, the process proceeds to the energy saving return sequence and the series of processes is terminated. In other words, the return from the energy saving mode is performed using the development information developed in the memory of the DIMM 14, the time for re-developing the information is shortened, and the restoration time is shortened.

  In step 312, the process returns to the normal return sequence, and the series of processing ends. That is, the recovery is performed by initializing each memory of the DIMM 14 and newly developing information. Therefore, when a phenomenon that leads to destruction of information stored in the DIMM 14 is detected based on the result of read / write leveling (read / write leveling result outside the threshold value), the normal recovery is performed, so that the system hangs up at the time of energy saving recovery. The return is performed reliably.

  In the above embodiment, a phenomenon that leads to destruction of information stored in the DIMM 14 is detected by monitoring the memory power supply, the refresh time interval, or the read / write leveling result at the time of recovery. You may make it detect the phenomenon which leads to information destruction using another physical quantity.

  Moreover, although each said embodiment was demonstrated separately, you may make it combine each. That is, by monitoring at least one of the memory power supply, the refresh time interval, and the read / write leveling result at the time of recovery, a phenomenon that leads to information destruction is detected, and any one parameter leads to information destruction In such a case, control may be performed so as to switch from energy saving return to normal return.

  Further, the processing in each of the above embodiments may be stored and distributed as various programs in various storage media.

10 Memory control device 12 CPU
14 DIMM
16 Energy Saving Control Unit 18 Power Supply Monitoring Unit 24 Memory Controller 26 Monitoring Unit 28 Temperature Sensor

Claims (5)

Detecting means for detecting a phenomenon that leads to destruction of the deployment information held in a memory that holds deployment information deployed in the apparatus when shifting to an energy saving state that suppresses power consumption;
When the phenomenon is not detected by the detection unit, the energy saving recovery is performed to return from the energy saving state using the development information held in the memory, and when the phenomenon is detected by the detection unit, Control means for controlling the return from the energy-saving state so as to perform a normal return that newly expands and returns information without using the expansion information held in the memory;
A memory control device.   The memory control device according to claim 1, wherein the detection unit detects the phenomenon based on whether or not a power supplied to the memory exceeds a predetermined threshold value.   The detection unit detects the phenomenon depending on whether or not a refresh time interval until a refresh command is output after the transition from self-refresh to auto-refresh in the memory exceeds a predetermined threshold value. Item 3. The memory control device according to Item 2.   The detection unit according to any one of claims 1 to 3, wherein the detection unit detects the phenomenon depending on whether a result of read / write leveling performed in the memory when returning from the energy saving state exceeds a predetermined setting range. 2. The memory control device according to item 1.   The memory control program for functioning a computer as a detection means and a control means in the memory control apparatus of any one of Claims 1-4.

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