JP2012215743A - Electro-optic device and electronic apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an electro-optic device and an electronic apparatus with high cost performance.SOLUTION: An electro-optic device includes a Nch transistor 82, a VSS power supply wiring 75 connected to an external connection terminal 23(23b), and a first relay wiring 85b provided on a wiring layer different from the wiring layer where the VSS power supply wiring 75 is provided, in which a source 88d of the Nch transistor 82 is connected to the VSS power supply wiring 75 through the first relay wiring 85b.

Description

  The present invention relates to an electro-optical device and an electronic apparatus.

  As the electro-optical device, for example, there is an active matrix driving type liquid crystal device including a transistor for each pixel as an element for switching control of a pixel electrode. As a method of manufacturing this liquid crystal device, for example, an element-side mother substrate on which a plurality of element substrates on which a pixel circuit including the transistor is formed is provided and a counter substrate disposed opposite to the element substrate are also provided on the same surface. The opposite mother substrate is bonded through a liquid crystal layer. Thereafter, the pair of mother substrates are divided and individual liquid crystal devices are taken out.

  On the other hand, due to static electricity generated during assembly and inspection of the liquid crystal device, an excessive voltage may be applied to transistors included in peripheral circuits (signal line driving circuit, scanning line driving circuit, etc.) and electrostatic breakdown may occur. Therefore, for example, as described in Patent Document 1, by providing a high resistance portion made of polysilicon or the like having a higher resistance than other wiring in a portion connected to the peripheral circuit, the electrostatic withstand voltage of the liquid crystal device can be improved. A method is disclosed that can do this.

JP 2009-75506 A

  However, the transistor connected to the power supply wiring connected to the power supply in addition to the peripheral circuit described above has a large area of charge compared to the other wiring and has a large amount of charge. There is a problem in that the generated static electricity is applied to the transistor via the power supply wiring and the transistor is electrostatically destroyed (for example, a gate insulating film).

  SUMMARY An advantage of some aspects of the invention is to solve at least a part of the problems described above, and the invention can be implemented as the following forms or application examples.

  Application Example 1 An electro-optical device according to this application example includes a transistor that forms a peripheral circuit, a constant potential wiring electrically connected to an external connection terminal, and a wiring layer that is the same as the constant potential wiring. An electrode electrically connected to the source or drain of the transistor; and a relay wiring electrically connecting the constant potential wiring and the electrode to a wiring layer different from the constant potential wiring and the electrode. Features.

  According to this configuration, since the source or drain of the transistor is connected to the constant potential wiring and the electrode via the relay wiring provided in a wiring layer different from the constant potential wiring and the electrode, the plane of the wiring directly connected to the transistor The typical area can be reduced as compared with the conventional case. Therefore, it is possible to reduce the electric charge charged in the wiring directly connected to the transistor, and it is possible to suppress the electrostatic breakdown of the transistor due to static electricity generated in the constant potential wiring during the manufacturing process. The constant potential wiring is a wiring to which a driving potential, a reference potential, or the like for driving the electro-optical device is applied.

  Application Example 2 In the electro-optical device according to the application example described above, it is preferable that the electro-optical device has a plurality of wiring layers, and has one or more wiring layers between the constant potential wiring and the relay wiring.

  According to this configuration, the relay wiring is provided in the upper layer with one or more wiring layers sandwiched between the relay wiring and the constant potential wiring, so that the wiring and contact holes below the relay wiring are manufactured. In this case, the transistor can be protected from static electricity generated in the constant potential wiring.

  Application Example 3 In the electro-optical device according to the application example, it is preferable that the transistor is connected via the electrode provided in the same wiring layer as the wiring layer provided with the constant potential wiring. .

  According to this configuration, since the transistor is connected via the electrode, it is not necessary to provide a deep contact hole as compared with the case where the transistor is directly connected from the relay wiring to the transistor via the contact hole. Can be reduced.

  Application Example 4 In the electro-optical device according to the application example, it is preferable that an electrostatic protection circuit including the transistor is provided.

  According to this configuration, the electrostatic protection circuit can be normally operated by preventing electrostatic breakdown of the transistor.

  Application Example 5 In the electro-optical device according to the application example, it is preferable that an inverter circuit including the transistor is provided.

  According to this configuration, the inverter circuit can be normally operated by preventing electrostatic breakdown of the transistor.

  Application Example 6 The electro-optical device according to the application example described above preferably includes a NAND circuit including the transistor.

  According to this configuration, the NAND circuit can be normally operated by preventing electrostatic breakdown of the transistor.

  Application Example 7 An electronic apparatus according to this application example includes the electro-optical device described above.

  According to this configuration, the electrostatic breakdown of the transistor in the manufacturing process can be prevented, and the electro-optical device that can be manufactured with a high yield is provided. Therefore, an electronic device having high cost performance can be provided.

The schematic plan view which shows the structure of a mother board | substrate. The enlarged plan view which expands and shows the A section of the mother board | substrate shown in FIG. FIG. 2 is a schematic plan view illustrating a structure of a liquid crystal device. FIG. 4 is a schematic cross-sectional view taken along the line CC ′ of the liquid crystal device illustrated in FIG. 3. FIG. 3 is an equivalent circuit diagram illustrating an electrical configuration of the liquid crystal device. 1 is a schematic cross-sectional view illustrating a structure of a liquid crystal device according to a first embodiment. FIG. 3 is an equivalent circuit diagram showing an electrical configuration of part B of the mother board in FIG. 2. 2A and 2B are schematic views illustrating a partial structure of a peripheral circuit, in which FIG. 1A is a schematic plan view illustrating a partial structure of the peripheral circuit, and FIG. 2B is a schematic cross-sectional view illustrating a partial structure of the peripheral circuit; FIG. 3 is a schematic diagram illustrating a configuration of a liquid crystal projector as an example of an electronic apparatus including a liquid crystal device. 4A and 4B are schematic diagrams illustrating a configuration of a liquid crystal device as an electro-optical device according to a second embodiment, in which FIG. 5A is a schematic plan view illustrating a structure of a peripheral circuit of the liquid crystal device, and FIG. Figure. The schematic cross section which shows the modification of the connection method in a peripheral circuit. The equivalent circuit diagram which shows the modification of a peripheral circuit.

  DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, embodiments of the invention will be described with reference to the drawings. Note that the drawings to be used are appropriately enlarged or reduced so that the part to be described can be recognized.

(First embodiment)
<Configuration of mother board>
FIG. 1 is a schematic plan view showing the configuration of the mother board. FIG. 2 is an enlarged plan view showing an A portion of the mother board shown in FIG. Hereinafter, the configuration of the mother board will be described with reference to FIGS. 1 and 2.

  As shown in FIG. 1, the mother substrate 100 is used for manufacturing a liquid crystal device 11 (see FIG. 3), for example, and one of the pair of substrates constituting the liquid crystal device 11 (for example, A plurality of element substrates are imposed in a matrix. The size of the mother substrate 100 is, for example, 8 inches. The thickness of the mother substrate 100 is, for example, 1.2 mm. The material of the mother substrate 100 is, for example, quartz.

  The mother substrate 100 is not limited to a circular shape in plan, and may have a shape having an orientation flat with a part of the circumference cut out.

  As shown in FIG. 2, in each liquid crystal device 11, a signal line driving circuit 22, a scanning line driving circuit 24, and an external connection terminal 23 as peripheral circuits are formed around the display area 19. The signal line driving circuit 22 and the scanning line driving circuit 24 and the external connection terminal 23 are electrically connected to each other by a signal wiring 29. Hereinafter, the structure of the liquid crystal device 11 that is finally formed by processing the mother substrate 100 will be described.

<Configuration of electro-optical device>
FIG. 3 is a schematic plan view showing the structure of a liquid crystal device as an electro-optical device. FIG. 4 is a schematic cross-sectional view taken along the line CC ′ of the liquid crystal device shown in FIG. Hereinafter, the structure of the liquid crystal device will be described with reference to FIGS.

  As shown in FIGS. 3 and 4, the liquid crystal device 11 is, for example, a TFT active matrix type liquid crystal device using a thin film transistor (hereinafter referred to as a “TFT (Thin Film Transistor) element”) as a pixel switching element. It is. In the liquid crystal device 11, an element substrate 200 and a counter substrate 300 constituting a pair of substrates are bonded together via a sealing material 14 having a substantially rectangular frame shape in plan view.

  The first substrate 12 constituting the element substrate 200 and the second substrate 13 constituting the counter substrate 300 are made of a translucent material such as glass or quartz, for example. The liquid crystal device 11 has a configuration in which a liquid crystal layer 15 is enclosed in a region surrounded by a sealing material 14. The sealing material 14 is provided with an injection port 16 for injecting liquid crystal, and the injection port 16 is sealed with a sealing material 17.

  As the liquid crystal layer 15, for example, a liquid crystal material having a positive dielectric anisotropy is used. In the liquid crystal device 11, a frame light shielding film 18 having a rectangular frame shape made of a light shielding material is formed on the second substrate 13 along the vicinity of the inner periphery of the sealing material 14, and a region inside the frame light shielding film 18. Is the display area 19.

  The frame light shielding film 18 is made of, for example, aluminum (Al), which is a light shielding material, and is provided so as to partition the outer periphery of the display region 19 on the second substrate 13 side.

  In the display area 19, pixel areas 21 are provided in a matrix. The pixel area 21 constitutes one pixel that is the minimum display unit of the display area 19. A signal line drive circuit 22 and an external connection terminal 23 are formed along one side (the lower side in FIG. 3) of the first substrate 12 in a region outside the sealing material 14.

  Further, scanning line driving circuits 24 are formed in the inner region of the sealing material 14 along two sides adjacent to the one side. An inspection circuit 25 is formed on the remaining side of the first substrate 12 (upper side in FIG. 3). The frame light shielding film 18 formed on the second substrate 13 side is, for example, at a position facing the scanning line driving circuit 24 and the inspection circuit 25 formed on the first substrate 12 (in other words, a position overlapping in plane). Is formed.

  On the other hand, vertical conduction terminals 26 for providing electrical continuity between the element substrate 200 and the counter substrate 300 are disposed at each corner of the counter substrate 300 (for example, four corners of the sealing material 14). Has been.

  As shown in FIG. 4, a plurality of pixel electrodes 27 are formed on the liquid crystal layer 15 side of the first substrate 12, and a first alignment film 28 is formed so as to cover the pixel electrodes 27. . The pixel electrode 27 is a conductive film made of a transparent conductive material such as ITO (Indium Tin Oxide).

  On the other hand, on the liquid crystal layer 15 side of the second substrate 13, a lattice-shaped light shielding film (BM: black matrix) (not shown) is formed, and a flat solid common electrode 31 is formed thereon. A second alignment film 32 is formed on the common electrode 31. The common electrode 31 is a conductive film made of a transparent conductive material such as ITO.

  The liquid crystal device 11 is a transmissive type, and polarizing plates (not shown) or the like are disposed on the light incident side and the light emitting side of the element substrate 200 and the counter substrate 300, respectively. The configuration of the liquid crystal device 11 is not limited to this, and may be a reflective type or a transflective type.

  FIG. 5 is an equivalent circuit diagram showing an electrical configuration of the liquid crystal device. Hereinafter, the electrical configuration of the liquid crystal device will be described with reference to FIG.

  As shown in FIG. 5, the liquid crystal device 11 has a plurality of pixel regions 21 that constitute a display region 19. A pixel electrode 27 is disposed in each pixel region 21. A TFT element 33 is formed in the pixel region 21.

  The TFT element 33 is a switching element that controls energization of the pixel electrode 27. A signal line 34 is electrically connected to the source side of the TFT element 33. Image signals S1, S2,..., Sn are supplied to each signal line 34 from, for example, the signal line drive circuit 22 (see FIG. 3).

  A scanning line 35 is electrically connected to the gate side of the TFT element 33. For example, scanning signals G1, G2,..., Gm are supplied to the scanning lines 35 in a pulsed manner at a predetermined timing from the scanning line driving circuit 24 (see FIG. 3). Further, the pixel electrode 27 is electrically connected to the drain side of the TFT element 33.

  .., Gm supplied from the scanning line 35 causes the TFT element 33 serving as a switching element to be in an ON state for a certain period, so that the image signals S1, S2,. , Sn are written to the pixel region 21 via the pixel electrode 27 at a predetermined timing.

  Image signals S1, S2,..., Sn written at a predetermined level in the pixel region 21 are held for a certain period by a liquid crystal capacitor formed between the pixel electrode 27 and the common electrode 31 (see FIG. 4). In order to prevent leakage of the held image signals S1, S2,..., Sn, a storage capacitor 37 is formed between the pixel electrode 27 and the capacitor line.

  Thus, when a voltage signal is applied to the liquid crystal layer 15, the alignment state of the liquid crystal molecules changes according to the applied voltage level. Thereby, the light incident on the liquid crystal layer 15 is modulated to generate image light.

  FIG. 6 is a schematic cross-sectional view showing the structure of the liquid crystal device. Hereinafter, the structure of the liquid crystal device will be described with reference to FIG. FIG. 6 shows the cross-sectional positional relationship of each component, and is represented on a scale that can be clearly shown. FIG. 6 shows only the element substrate among the element substrate and the counter substrate constituting the liquid crystal device.

  As shown in FIG. 6, the liquid crystal device 11 includes an element substrate 200 and a counter substrate 300 (not shown). A lower light shielding film 41 made of Ti (titanium), Cr (chromium), or the like is formed on the first substrate 12 of the element substrate 200. The lower light-shielding film 41 is planarly patterned in a lattice shape, and defines an opening area of each pixel area 21. A base insulating film 42 made of a silicon oxide film or the like is formed on the first substrate 12 and the lower light shielding film 41.

  On the base insulating film 42, a TFT element 33, a scanning line 35, and the like are formed. The TFT element 33 has, for example, an LDD (Lightly Doped Drain) structure, a semiconductor layer 43 made of polysilicon or the like, a gate insulating film 44 formed on the semiconductor layer 43, and a gate insulating film 44 on the gate insulating film 44. And a scanning line 35 made of a formed polysilicon film or the like. As described above, the scanning line 35 functions as a gate electrode.

  The semiconductor layer 43 includes a channel region 43a, a low concentration source region 43b, a low concentration drain region 43c, a high concentration source region 43d, and a high concentration drain region 43e. A channel is formed in the channel region 43 a by an electric field from the scanning line 35. A first interlayer insulating film 45 made of a silicon oxide film or the like is formed on the gate insulating film 44.

  The high concentration source region 43 d of the TFT element 33 is electrically connected to the relay layer 46 formed on the first interlayer insulating film 45 through the contact hole 47. On the other hand, the high-concentration drain region 43 e is electrically connected to a relay layer 51 formed in the same layer as the relay layer 46 through a contact hole 52.

  The relay layer 46 is electrically connected to the signal line 34 formed on the second interlayer insulating film 53 via the contact hole 54. On the other hand, the relay layer 51 is electrically connected to a relay layer 55 formed in the same layer as the signal line 34 via a contact hole 56.

  The relay layer 55 is further electrically connected via a contact hole 56 to a relay layer 58 provided in the same layer as a capacitor electrode 57 described later. The relay layer 58 is electrically connected to the pixel electrode 27 through the contact hole 59. That is, the high concentration drain region 43e of the TFT element 33 and the pixel electrode 27 are electrically relay-connected through the relay layer 51, the relay layer 55, and the relay layer 58 in this order.

  A storage capacitor 62 is formed on the upper side of the signal line 34 and the relay layer 55 via a third interlayer insulating film 61. By electrically connecting the storage capacitor 62 in parallel with the liquid crystal capacitor, it is possible to hold the voltage of the pixel electrode 27 for a time that is, for example, three digits longer than the time during which the image signal is actually applied. Since the retention characteristics of the liquid crystal element are improved, the liquid crystal device 11 having a high contrast ratio can be realized.

  The capacitor electrode 57 functions as one electrode of the storage capacitor 62 electrically connected in parallel to the liquid crystal capacitor, and is held at a fixed potential. The capacitive electrode 57 is made of a transparent electrode such as ITO. For this reason, even if the capacitor electrode 57 is formed so as to overlap the display region 19 including the opening region, it is possible to suppress a decrease in light transmittance in the opening region.

  A dielectric film 63 is formed on the capacitor electrode 57. The dielectric film 63 is formed in a solid shape so as to cover the capacitor electrode 57. Since the dielectric film 63 is made of a transparent dielectric material such as silicon nitride, even if the dielectric film 63 is formed widely in the display area 19 including the opening area, the light transmittance in the opening area is high. It can suppress that it falls. In addition, it is more preferable that the thickness of the dielectric film 63 is smaller in order to increase the capacitance value of the storage capacitor 62.

  A capacitor separation film 64 for separating the storage capacitor 62 from one pixel to another is formed on the capacitor electrode 57. The capacitance value of the storage capacitor 62 can be adjusted by increasing or decreasing the area of the capacitor separation film 64.

  A pixel electrode 27 is formed on the capacitor separation film 64. The pixel electrode 27 is formed in an island shape for each pixel divided in a matrix by the signal line 34 and the scanning line 35. Although not shown here, on the pixel electrode 27, a first alignment film 28 (see FIG. 4) for regulating the alignment state of the liquid crystal molecules contained in the liquid crystal layer 15 (see FIG. 4). ) Is formed.

  Since the storage capacitor 62 is composed of the transparent capacitor electrode 57, the dielectric film 63, and the pixel electrode 27, each of the storage capacitors 62 does not narrow the opening region, and the aperture ratio, which is the proportion of the pixel in the opening region, is reduced. I will not let you. In addition, according to such a storage capacitor 62, the storage capacitor 62 can be formed in the open region, so that the capacitance value can be increased compared to the case where the storage capacitor is formed only in the non-open region. is there.

Although not shown, a black matrix (BM) made of aluminum or the like is formed on the side of the counter substrate 300 facing the liquid crystal layer 15 of the second substrate 13, and a silicon oxide film (SiO ₂ ) is formed thereon. Is formed. Further, a transparent common electrode 31 (see FIG. 4) is formed on the entire surface of the silicon oxide film, and a second alignment film 32 (see FIG. 4) is formed to cover the common electrode 31 made of ITO or the like. ing.

  FIG. 7 is an equivalent circuit diagram showing an electrical configuration of part B (peripheral circuit) of the mother board in FIG. FIG. 8 is a schematic diagram showing a partial structure of the peripheral circuit. (A) is a schematic plan view showing a partial structure of a peripheral circuit, and (b) is a schematic cross-sectional view showing a partial structure of the peripheral circuit. Hereinafter, the structure of the peripheral circuit will be described with reference to FIGS.

  As shown in FIG. 7, for example, an electrostatic protection circuit 71 and an inverter circuit 72 used for an inspection circuit are provided around the liquid crystal device 11. The electrostatic protection circuit 71 includes a Pch transistor (PchTFT) and an Nch transistor (NchTFT).

  The source and gate of the Pch transistor are connected to a VDD power supply wiring 73 as a constant potential wiring to which a driving potential for driving the liquid crystal device 11 and a reference potential are applied. The drain is connected to the signal potential wiring 74. The source and gate of the Nch transistor are connected to a VSS power supply wiring 75 (GND) as a constant potential wiring. The drain is connected to the signal potential wiring 74. The signal potential wiring 74 is connected to the signal terminal 23c.

  Similarly, the inverter circuit 72 includes a Pch transistor and an Nch transistor. The source of the Pch transistor is connected to the VDD power wiring 73. The gate is connected to the signal potential wiring 74. The source of the Nch transistor is connected to the VSS power supply wiring 75 (GND). The gate is connected to the signal potential wiring 74.

  The VDD power supply wiring 73 connected to the VDD power supply terminal 23a and the VSS power supply wiring 75 connected to the VSS power supply terminal 23b have a larger planar area and a larger amount of charge than other wirings. Therefore, another wiring layer is provided between the VDD power supply wiring 73 and the transistor (for example, the Pch transistor of the electrostatic protection circuit 71) and between the VSS power supply wiring 75 and the transistor (for example, the Nch transistor of the electrostatic protection circuit 71). By connecting through the wiring, it is possible to reduce the planar area of the wiring directly connected to the transistor, and to reduce the charge charged in the wiring.

  Accordingly, it is possible to suppress, for example, electrostatic breakdown of the gate insulating film of the transistor due to static electricity generated in the VDD power supply wiring 73 and the VSS power supply wiring 75 in the manufacturing process. Hereinafter, a method of connecting the VDD power supply wiring 73 and the VSS power supply wiring 75 in the electrostatic protection circuit 71 out of the electrostatic protection circuit 71 and the inverter circuit 72 will be described with reference to FIG.

  As shown in FIG. 8A, the electrostatic protection circuit 71 includes a Pch transistor 81 and an Nch transistor 82, a VDD power supply wiring 73 and a VDD connection wiring 83 as an electrode, a VSS power supply wiring 75 and a VSS connection wiring as an electrode. 84.

  As described above, the VDD power supply wiring 73 and the VSS power supply wiring 75 are power supply wirings connected to the external connection terminal 23 (VDD power supply terminal 23a, VSS power supply terminal 23b), and are compared with the planar areas of other wirings. And has a large area and a large amount of charge compared to other wirings.

  The VDD connection wiring 83 connected to the source 88a and the gate 88b of the Pch transistor 81 is electrically connected to the VDD power supply wiring 73 through the first relay wiring 85a. The VSS connection wiring 84 connected to the source 88d and the gate 88e of the Nch transistor 82 is electrically connected to the VSS power supply wiring 75 via the first relay wiring 85b. The sources 88a and 88d and the drains 88c and 88f constitute part of the semiconductor layer 86 (86a and 86b) made of, for example, polysilicon.

  The Nch transistor 82 will be specifically described as an example. As shown in FIG. 8B, for example, the VSS power supply wiring 75 includes a first relay wiring 85b provided in a wiring layer (on the second interlayer insulating film 53) having a wiring layer different from the VSS power supply wiring 75, and the VSS power supply wiring 75. The power supply wiring 75 and the VSS connection wiring 84 provided in the same layer are electrically connected to the Nch transistor 82 (semiconductor layer 86b). The above-described wiring is connected by contact holes 87a, 87b, 87c.

  That is, in the manufacturing process, the VSS power supply wiring 75 and the Nch transistor 82 are not electrically connected. Therefore, when forming a wiring, a contact hole, etc., it becomes possible to prevent static electricity from flowing from the VSS power supply wiring 75 having a large planar area to the Nch transistor 82, and the Nch transistor 82 is prevented from electrostatic breakdown. Can be prevented.

  In addition, since the VSS power supply wiring 75 and the Nch transistor 82 are electrically connected via the first relay wiring 85b and the VSS connection wiring 84 in a later manufacturing process, the VSS power supply wiring 75 and the Nch transistor 82 are normally used as the electrostatic protection circuit 71. It can be operated.

  Further, since the VSS power supply wiring 75, the VSS connection wiring 84, and the first relay wiring 85b are made of a low resistance material such as aluminum, the characteristics of the electrostatic protection circuit 71 are reduced without significantly reducing the wiring resistance. Can be suppressed.

  The same effect can be obtained for the Pch transistor 81 of the electrostatic protection circuit 71 and the inverter circuit 72 by applying the wiring structure described above.

<Configuration of electronic equipment>
FIG. 9 is a schematic diagram illustrating a configuration of a liquid crystal projector as an example of an electronic apparatus including the above-described liquid crystal device. Hereinafter, the configuration of the liquid crystal projector including the liquid crystal device will be described with reference to FIG.

  As shown in FIG. 9, the liquid crystal projector 901 has a structure in which three liquid crystal modules employing the liquid crystal device 11 described above are arranged and used as RGB light valves 911R, 911G, and 911B, respectively.

  Specifically, when projection light is emitted from a lamp unit 912 of a white light source such as a metal hydrolamp, the light components R, G, and B corresponding to the three primary colors of RGB are generated by three mirrors 913 and two dichroic mirrors 914. Divided and led to light valves 911R, 911G, and 911B corresponding to the respective colors. In particular, the light component B is guided through a relay lens system 918 including an incident lens 915, a relay lens 916, and an exit lens 917 in order to prevent light loss due to a long optical path.

  The light components R, G, and B corresponding to the three primary colors modulated by the light valves 911R, 911G, and 911B are synthesized again by the dichroic prism 919, and then projected as a color image on the screen 921 through the projection lens 920. The

  As described above, the present invention is not limited to the liquid crystal projector 901 in which three liquid crystal modules are arranged, and may be applied to, for example, a liquid crystal projector in which one liquid crystal module is arranged.

  The liquid crystal projector 901 having such a configuration can be efficiently assembled by reducing the cost through the liquid crystal module in which the liquid crystal device 11 described above is employed. In addition to the above-described liquid crystal projector 901, the electronic device including the liquid crystal device 11 is a high-definition EVF (Electric View Finder), a mobile phone, a mobile computer, a digital camera, a digital video camera, a television, a display, an in-vehicle device, an audio It can be used for various electronic devices such as devices and lighting devices.

  As described above in detail, according to the liquid crystal device 11 and the electronic apparatus of the first embodiment, the following effects can be obtained.

  (1) According to the liquid crystal device 11 of the first embodiment, for example, the source 88d of the Nch transistor 82 is connected to the VSS power supply wiring 75 via the first relay wiring 85b provided in a wiring layer different from the VSS power supply wiring 75. Since they are connected, the planar area of the wiring (VSS connection wiring 84) directly connected to the Nch transistor 82 can be reduced as compared with the conventional case. Accordingly, since the charge charged in the VSS connection wiring 84 directly connected to the Nch transistor 82 is reduced, it is possible to suppress the Nch transistor 82 from being electrostatically damaged by static electricity generated in the VSS power supply wiring 75 in the manufacturing process.

  (2) According to the liquid crystal device 11 of the first embodiment, since the Nch transistor 82 is connected via the VSS connection wiring 84, the Nch transistor 82 is directly connected to the Nch transistor 82 via the contact hole from the first relay wiring 85b. Compared to the case, it is not necessary to provide a deep contact hole, and the load in the manufacturing process can be reduced.

  (3) According to the electronic apparatus of the present embodiment, since the Nch transistor 82 can be prevented from electrostatic breakdown in the manufacturing process and the liquid crystal device 11 that can be manufactured with high yield is provided, an electronic device having high cost performance is provided. Equipment can be provided.

(Second Embodiment)
<Configuration of electro-optical device>
FIG. 10 is a schematic diagram illustrating a configuration of a liquid crystal device as an electro-optical device according to the second embodiment. (A) is a schematic plan view which shows the structure of the peripheral circuit of a liquid crystal device. (B) is a schematic cross-sectional view showing the structure of a peripheral circuit. The configuration of the liquid crystal device according to the second embodiment will be described below with reference to FIG.

  The liquid crystal device 111 of the second embodiment is different from the liquid crystal device 11 described in the above first embodiment in that a large number of wiring layers are provided. Hereinafter, the same components as those in the first embodiment are denoted by the same reference numerals, and description thereof is omitted or simplified here. FIG. 10 is a cross-sectional view of a region from the electrostatic protection circuit 71 which is one of the peripheral circuits to the external connection terminal 23. As described above, the Nch transistor 82 in the electrostatic protection circuit 71 will be specifically described as an example.

  As shown in FIG. 10B, the liquid crystal device 111 is provided with one of the transistors (for example, the Nch transistor 82) constituting the electrostatic protection circuit 71 on the first substrate 12 (see FIG. 6). On the Nch transistor 82, a VSS connection wiring 84 and a VSS power supply wiring 75 are provided via a first interlayer insulating film 45. On the VSS connection wiring 84 and the VSS power supply wiring 75, first relay wirings 85 c and 85 d are provided via the second interlayer insulating film 53. A second relay wiring 91 is provided on the first relay wiring 85c and 85d with a third interlayer insulating film 61 interposed therebetween.

  The first interlayer insulating film 45 to the third interlayer insulating film 61 are made of, for example, a silicon oxide film. The VSS power supply wiring 75, the VSS connection wiring 84, the first relay wiring 85c and 85d, and the second relay wiring 91 are made of a low resistance material such as aluminum, for example.

  As shown in FIGS. 10A and 10B, the source 88d of the Nch transistor 82 is connected via the contact holes 87d, 87e, 87f, 87g, and 87h to the VSS connection wiring 84, the first relay wiring 85c, the first The second relay wiring 91, the first relay wiring 85d, and the VSS power supply wiring 75 are connected in this order, and are electrically connected to the external connection terminal 23 (VSS power supply terminal 23b).

  As described above, the Nch transistor 82 electrically connected to the VSS power supply wiring 75 is connected via the first relay wirings 85 c and 85 d and the second relay wiring 91 provided in a wiring layer different from the VSS power supply wiring 75. Therefore, as compared with the conventional case where the VSS power supply wiring 75 and the Nch transistor 82 are directly connected, the planar area of the wiring directly connected to the Nch transistor 82 (VSS connection wiring 84) can be reduced. it can. Further, since the charge charged on the VSS connection wiring 84 is small, it is possible to suppress the Nch transistor 82 from being electrostatically damaged due to static electricity of the VSS power supply wiring 75 generated in the manufacturing process.

  The same effect can be obtained for the Pch transistor 81 of the electrostatic protection circuit 71 and the inverter circuit 72 by applying the wiring structure described above.

  As described in detail above, according to the liquid crystal device 111 of the second embodiment, the following effects can be obtained in addition to the effects (1) to (3) of the first embodiment.

  (4) According to the liquid crystal device 111 of the second embodiment, the second relay wiring 91 is provided in the upper layer between the second relay wiring 91 and the VSS power supply wiring 75 via the first relay wiring 85c and 85d. Therefore, the Nch transistor 82 can be protected from static electricity generated in the VSS power supply wiring 75 when a wiring, a contact hole, or the like below the second relay wiring 91 is manufactured.

  In addition, embodiment is not limited above, It can also implement with the following forms.

(Modification 1)
As in the second embodiment described above, the Nch transistor 82 and the VSS power supply terminal 23b are connected in the order of the VSS connection wiring 84, the first relay wiring 85c, the second relay wiring 91, the first relay wiring 85d, and the VSS power supply wiring 75. It is not limited to connecting, but may be connected as follows.

  For example, as shown in FIG. 11, the Nch transistor 82 and the VSS power supply terminal 23b are electrically connected via the VSS connection wiring 84a, the second relay wiring 91, the VSS connection wiring 84b, the first relay wiring 85e, and the VSS power supply wiring 75. May be connected to each other.

  According to this, similarly to the second embodiment, the Nch transistor 82 and the VSS power supply terminal 23b are connected via the wirings of the plurality of wiring layers (the first relay wiring 85e, the second relay wiring 91, etc.). Therefore, static electricity charged in the VSS power supply wiring 75 can be prevented from flowing directly to the Nch transistor 82. Therefore, the Nch transistor 82 can be prevented from electrostatic breakdown.

(Modification 2)
As described above, the circuit including the transistor in the peripheral circuit is not limited to the electrostatic protection circuit 71 and the inverter circuit 72, and may be a NAND circuit 95 as shown in FIG. 12, for example. According to this, the transistors constituting the NAND circuit 95 are not directly connected to the VDD power supply wiring 73 and the VSS power supply wiring 75, but are connected via a wiring layer different from the wiring layer of the VDD power supply wiring 73 and the VSS power supply wiring 75. Therefore, static electricity charged in the VDD power supply wiring 73 and the VSS power supply wiring 75 can be prevented from flowing directly to the transistor. Therefore, electrostatic breakdown of the transistor can be suppressed, and the NAND circuit 95 can be normally operated.

(Modification 3)
As described above, the source of the transistor constituting the electrostatic protection circuit 71 is connected to the power supply wiring (VDD power supply wiring 73, VSS power supply wiring 75), and the drain is connected to the power supply wiring. May be.

  DESCRIPTION OF SYMBOLS 11, 111 ... Liquid crystal device as an electro-optical device, 12 ... 1st board | substrate, 13 ... 2nd board | substrate, 14 ... Sealing material, 15 ... Liquid crystal layer, 16 ... Injection port, 17 ... Sealing material, 18 ... Frame light shielding film , 19 ... Display area, 21 ... Pixel area, 22 ... Signal line drive circuit, 23 ... External connection terminal, 23a ... VDD power supply terminal, 23b ... VSS power supply terminal, 23c ... Signal terminal, 24 ... Scanning line drive circuit, 25 DESCRIPTION OF SYMBOLS ... Inspection circuit, 26 ... Vertical conduction terminal, 27 ... Pixel electrode, 28 ... 1st alignment film, 29 ... Signal wiring, 31 ... Common electrode, 32 ... 2nd alignment film, 33 ... TFT element, 34 ... Signal line, 35 Scan line 36 Capacitance line 37 Storage capacitor 41 Lower light shielding film 42 Base insulating film 43 Semiconductor layer 43a Channel region 43b Low concentration source region 43c Low concentration drain region 43d ... High concentration source region, 3e ... High-concentration drain region, 44 ... Gate insulating film, 45 ... First interlayer insulating film, 46, 51, 55, 58 ... Relay layer, 47, 52, 54, 56, 59 ... Contact hole, 53 ... Second interlayer Insulating film, 57 ... capacitance electrode, 61 ... third interlayer insulating film, 62 ... storage capacitor, 63 ... dielectric film, 64 ... capacitance separation film, 71 ... electrostatic protection circuit, 72 ... inverter circuit, 73 ... constant potential wiring VDD power wiring, 74 ... signal potential wiring, 75 ... VSS power wiring as constant potential wiring, 81 ... Pch transistor, 82 ... Nch transistor, 83 ... VDD connection wiring as electrode, 84, 84a, 84b ... as electrode VSS connection wiring, 85a, 85b, 85c, 85d, 85e ... first relay wiring, 86, 86a, 86b ... semiconductor layer, 87a, 87b, 87c, 87d ... Tact hole, 88a, 88d ... source, 88b, 88e ... gate, 88c ... drain, 91 ... second relay wiring, 95 ... NAND circuit, 100 ... mother substrate, 200 ... element substrate, 300 ... counter substrate, 901 ... liquid crystal Projector, 911R, 911G, 911B ... light valve, 912 ... lamp unit, 913 ... mirror, 914 ... dichroic mirror, 915 ... incident lens, 916 ... relay lens, 917 ... exit lens, 918 ... relay lens system, 919 ... dichroic prism 920 ... projection lens, 921 ... screen.

Claims (7)

A transistor constituting a peripheral circuit;
Constant potential wiring electrically connected to the external connection terminal;
An electrode electrically connected to the source or drain of the transistor on the same wiring layer as the constant potential wiring;
A relay wiring electrically connecting the constant potential wiring and the electrode to a wiring layer different from the constant potential wiring and the electrode;
An electro-optical device comprising: The electro-optical device according to claim 1,
Having multiple wiring layers,
An electro-optical device having one or more wiring layers between the constant potential wiring and the relay wiring. The electro-optical device according to claim 1 or 2,
The electro-optical device, wherein the transistor is connected via the electrode provided in the same wiring layer as the wiring layer provided with the constant potential wiring. An electro-optical device according to any one of claims 1 to 3,
An electro-optical device comprising an electrostatic protection circuit including the transistor. An electro-optical device according to any one of claims 1 to 3,
An electro-optical device comprising an inverter circuit including the transistor. An electro-optical device according to any one of claims 1 to 3,
An electro-optical device comprising a NAND circuit including the transistor.   An electronic apparatus comprising the electro-optical device according to any one of claims 1 to 6.

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