JP2012137708A - Liquid crystal display - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve linearity without any substrate effect of a transistor for source follower.SOLUTION: With respect to PMOS transistors Tr3 and Tr4 for source follower, a source is connected to a back gate. A PMOS transistor Tr8 that is commonly connected to each pixel in the same column direction in a pixel part is a transistor for constant current which is connected to each source and each back gate of the PMOS transistors Tr3 and Tr4 for source follower within each pixel. Transistors Tr3, Tr5, Tr4, Tr6, Tr7 and Tr8 constitute a read-out part that alternately reads out a positive pixel value retained by retention volume C1 and a negative pixel value retained by retention volume C2 to a pixel electrode PE with a period shorter than a vertical scanning period. Threshold voltages Vth3 and Vth4 of the PMOS transistors Tr3 and Tr4 for source follower fall into a state of not varying by a signal level (gate voltage) (a state of no substrate effect) and become fixed voltages.

Description

  The present invention relates to a liquid crystal display device, and in particular, in each pixel, a positive-polarity video signal and a negative-polarity video signal are separately sampled and held in two holding capacitors, and then those holding voltages are alternately applied to the pixel electrodes. The present invention relates to a liquid crystal display device in which a display element is AC driven.

  In recent years, a liquid crystal on silicon (LCOS) type liquid crystal display device is often used as a central part for projecting an image in a projector device or a projection television. In this LCOS type liquid crystal display device, an analog video signal is inputted to a semiconductor element such as a CMOS (Complementary Metal Oxide Semiconductor), and the signal is held as it is on the pixel electrode of the liquid crystal display element for each pixel. A method of changing the orientation of the liquid crystal in the display element or applying a video signal pulse-width modulated (PWM) with a digital signal to the pixel electrode of the liquid crystal display element to temporally align the liquid crystal in the liquid crystal display element. There is a method of driving by switching. Among them, the method of directly applying an analog video signal to the pixel electrode has a problem that liquid crystal burn-in easily occurs.

  In order to solve the problem, the present applicant firstly intersects each of a plurality of data lines each including two data lines (column signal lines) and a plurality of gate lines (row scanning lines). Each pixel is disposed in a portion, and in each of the pixels, a positive video signal and a negative video signal are separately sampled and held in two holding capacitors, and then the holding voltage is alternately applied to the pixel electrode to liquid crystal A liquid crystal display device in which the display element is AC driven has been proposed (see, for example, Patent Document 1).

  In this liquid crystal display device, the voltage applied to the pixel electrode can be held in two holding capacitors in each pixel for one frame period. Therefore, the AC drive frequency of the liquid crystal display element does not depend on the vertical scanning frequency. It can be set freely in the inversion control cycle in the pixel circuit. As a result, according to this liquid crystal display device, the AC drive frequency can be set to be extremely higher than the vertical scanning frequency, thereby preventing burn-in compared to the prior art, preventing deterioration of display quality such as spots, and digital PWM. Features such as the ability to express gradation correctly than the method are obtained.

  In addition, this liquid crystal display device converts the positive and negative ramp signals, which change monotonically in one horizontal scanning period (1H) period from the black level to the white level, into the number of pixels in one line. Commonly supplied to the corresponding number of video switches. Then, after all the video switches are turned on every time the horizontal scanning period starts, the counter value indicating the gradation obtained by counting the clock synchronized with the ramp signal by the counter and the pixel value of the digital video signal are displayed on one line. The comparator for comparing each pixel outputs a coincidence pulse when both coincide with each other, turns off the video switch provided corresponding to the pixel, and turns off the voltages of the two ramp signals at this time. The D / A conversion into the analog video signal is performed by holding the video switches in the two holding capacitors in the pixels connected to the video switch via a set of two data lines. In this liquid crystal display device, the DA conversion unit that performs the DA conversion described above is taken into the chip and the digital video signal is input, making it easier to use and reducing the number of external circuits compared to the conventional method of directly inputting an analog video signal. But there are benefits.

JP 2009-223289 A

  However, the above liquid crystal display device has the following problems.

  The first problem is that the holding voltage of the positive video signal and the negative video signal (specifically, the positive ramp signal and the negative ramp signal) in which the pixel circuit is separately held in the two holding capacitors is used as the source follower. In the case of a circuit configuration in which the voltage is alternately applied to the pixel electrodes of the liquid crystal display element, linearity deteriorates due to a problem peculiar to the CMOS source follower, and the dynamic range of the liquid crystal drive voltage is lowered, including gain reduction, to increase brightness. Saddle seizure will be affected.

  The deterioration of the linearity of the source follower will be further described with reference to FIG. FIG. 6 is an equivalent circuit diagram of one pixel of the liquid crystal display device described in Patent Document 1. In FIG. 6, the source follower transistors Tr3 and Tr4 have gates connected to connection points between the holding capacitors C1 and C2 and the drains of the pixel selection transistors Tr1 and Tr2, and sources connected to the drains and sources of the switching transistors Tr21 and Tr22. To the drain of the constant current transistor Tr23. Each connection point of the transistors Tr21, Tr22, and Tr23 is connected to the pixel electrode PE. The transistors Tr21 and Tr22 are alternately turned on by the switching signals 2k and 2kb, and the positive electrode holding voltage and the negative electrode holding voltage held in the holding capacitors C1 and C2 are alternately supplied to the pixel electrodes through the source follower transistors Tr3 and Tr4. Apply to PE.

  Here, the threshold voltage Vth of the source follower transistors Tr3 and Tr4 expressed by the following equation changes due to the source voltage of Tr3 and Tr4 due to the influence of the substrate effect.

Vth = Vth0 + γ [√ ( 2 × φ f + Vsb) -√ (2 × φ f)] (1)
Vth0: Vth when Vsb = 0 Vsb: substrate voltage of transistor
φ _f : Fermi level 2 × φ _f ≒ 0.6V
γ: Substrate effect constant Due to the Vth substrate effect of Tr1 and Tr2 which are N-channel MOS type field effect transistors, the input voltage of the source follower transistors Tr3 and Tr4 can be held from VDD to a voltage lower by Vth of Tr1 and Tr2. Cannot hold at C2. Therefore, the following formula is established.

Vc1 = VDD-Vth1 (2)
Vc1: Maximum voltage that can be held at C1
Vth1: Vth of Tr1 when the source voltage of Tr1 is Vc1
Vc2 = VDD-Vth2 (3)
Vc2: Maximum voltage that can be held at C2
Vth2: Vth of Tr1 when the source voltage of Tr2 is Vc2
In addition, the voltage output to the pixel electrode PE by Vth including the substrate effect of Tr21 and Tr22 which are P-channel MOS field effect transistors does not decrease by Vth even if the voltage is lowered. That is, the following equation is established.

Vbl = Vth3m (4)
Vbml = Vth4m (5)
Vbl: Minimum output voltage on the positive polarity side
Vbml: Minimum output voltage on the negative polarity side
Vth3m: Vth when the source voltage of Tr3 is Vbl
Vth4m: Vth when the source voltage of Tr4 is Vbml
From the above results, the voltage Vb applied to the liquid crystal layer of the pixel portion has poor linearity and becomes a curve deviating from a straight line. In particular, the gain is about 0.8 due to the influence of the substrate effect, the change of the slope is about 50 mV when the input voltage range is 0V to 5V.

  The second problem is that the number of transistors that can be included in one pixel is limited due to the problem of the pixel pitch. Therefore, it is difficult to change the circuit configuration, and there is a limit to the improvement in linearity.

  The present invention has been made in view of the above points, and an object of the present invention is to provide a liquid crystal display device which can improve the linearity by eliminating the substrate effect of the source follower transistor.

In order to achieve the above object, the liquid crystal display device of the present invention has a plurality of data lines and a plurality of row scanning lines provided at a crossing portion where a plurality of data lines intersect each other. Each of the pixels
A display element in which a liquid crystal layer is sandwiched between an opposing pixel electrode and a common electrode, and a positive video signal supplied via one data line of a set of two data lines are sampled and fixed. The first sampling and holding means for holding in the first holding capacitor for the period and the negative polarity having the opposite polarity to the positive video signal supplied through the other data line of the set of two data lines Second sampling and holding means for sampling the video signal and holding it in the second holding capacitor for a certain period of time, first and second source follower transistors each having a source connected to the back gate, The positive-polarity video signal voltage, which is separately connected to the drains of the two source follower transistors and is held in the first holding capacitor, is output from the source of the first source follower transistor. The first and second switching operations for alternately switching the operation of outputting the negative video signal voltage held in the second holding capacitor from the source of the second source follower transistor at a predetermined cycle shorter than the vertical scanning cycle. A drain and a back gate are connected in common to each source of the transistor and the first and second source follower transistors, and a source is connected to the pixel electrode. Switching between the first and second switching transistors And the positive video signal voltage held in the first holding capacitor input through the first source follower transistor and the second holding capacitor input through the second source follower transistor. A third switching transistor for applying the held negative video signal voltage to the pixel electrode; For example,
A constant current transistor having a drain connected in common to a common connection point between the first and second source follower transistors and the third switching transistor in each pixel of the plurality of pixels in the column direction. It is characterized by having.

In order to achieve the above object, the liquid crystal display device of the present invention is provided at an intersection where a plurality of sets of data lines and a plurality of row scanning lines intersect each other. Each of the plurality of pixels
A display element in which a liquid crystal layer is sandwiched between an opposing pixel electrode and a common electrode, and a positive video signal supplied via one data line of a set of two data lines are sampled and fixed. The first sampling and holding means for holding in the first holding capacitor for the period and the negative polarity having the opposite polarity to the positive video signal supplied through the other data line of the set of two data lines A second sampling and holding means for sampling the video signal and holding it in the second holding capacitor for a certain period, and a gain of 1 for differentially amplifying and outputting the positive video signal voltage held in the first holding capacitor A first differential amplifier; a second differential amplifier having a gain of 1 that differentially amplifies and outputs the negative-polarity video signal voltage held in the second holding capacitor; and the first and second differential amplifiers Are alternately selected at a predetermined cycle shorter than the vertical scanning cycle. The drains are commonly connected to the first and second switching transistors for outputting the positive video signal voltage or the negative video signal voltage from the selected differential amplifier, and the output terminals of the first and second differential amplifiers. The positive video signal voltage held in the first holding capacitor, which is switched in synchronism with the switching of the first and second switching transistors and inputted through the first differential amplifier, and the second differential amplifier A third switching transistor that applies to the pixel electrode a negative video signal voltage held in the second holding capacitor input through the pixel electrode,
Each pixel in the column direction among the plurality of pixels has a constant current transistor having a drain connected in common to each drain of the first and second switching transistors in the pixel.

  According to the present invention, since the substrate effect of the source follower transistor is eliminated, the linearity can be improved, and the holding voltage can be applied to the liquid crystal layer by an ideal circuit having a gain of about 1.

It is a block diagram of one embodiment of a liquid crystal display device of the present invention. FIG. 3 is an equivalent circuit diagram of the first embodiment of one pixel in the liquid crystal display device of the present invention. 3 is a timing chart for explaining the operation of FIG. 2. It is an equivalent circuit diagram of the second embodiment of one pixel in the liquid crystal display device of the present invention. 5 is a timing chart for explaining the operation of FIG. 4. 6 is an equivalent circuit diagram of one pixel of a liquid crystal display device described in Patent Literature 1. FIG.

  Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows a block diagram of an embodiment of a liquid crystal display device according to the present invention. As shown in the figure, the liquid crystal display device 100 according to the present embodiment includes a shift register and comparator 101, a horizontal drive circuit 102 including a video switch, and a set of two connected to the horizontal drive circuit 102. N sets (n is a natural number of 2 or more) data lines (column signal lines) Di +, Di- (i = 1, 2, 3,..., N), and a total of m lines (m is 2 or more) A total number of m × n pixels 103 _{11 to} 103 _mn arranged at the intersections of (natural number) gate lines (row scanning lines) G1 to Gm and connected in common to m pixels in each column. N constant current transistors 104 _{1 to} 104 _n and vertical drive circuits 105 and 106.

  The shift register and comparator 101 develops one line of the input digital video signal (image data) by the shift register, temporarily holds it, and supplies it to the comparator. N shift registers and comparators of the comparator 101 are provided for each column corresponding to n sets of data lines (column signal lines). The n comparators are commonly supplied with reference gradation data from a counter (not shown) in which a plurality of gradation values change stepwise at regular intervals within a horizontal scanning period from, for example, a minimum value to a maximum value. On the other hand, the image data held by the shift register is supplied for each pixel unit of n pixels in one line, compared with each other, and when the two match, a matching pulse is supplied to the horizontal drive circuit 102.

  The horizontal drive circuit 102 includes a video switch for positive polarity connected to one data line Di + of a pair of data lines (column signal lines) Di + and Di−, and a negative electrode connected to the other data line Di−. N video switches for each data line (column signal line) unit are provided in total, and are matched with the corresponding comparators among the n comparators in the shift register and comparator 101 described above. The pulse is supplied through a buffer amplifier. The above configuration is the same as the configuration of the liquid crystal display device described in Patent Document 1 described above.

  The vertical drive circuits 105 and 106 sequentially supply row selection signals to the gate lines G1 to Gm in one horizontal scanning period (1H) cycle, and simultaneously supply the same row selection signals to the same gate lines. This is because the chip is long horizontally (the number of horizontal pixels is large), and unless it is driven from the left and right, waveform dullness occurs due to wiring resistance and the like, which affects the image quality. Driving with the left and right vertical drive circuits 105 and 106 can reduce the waveform dullness and increase the speed.

The pixels 103 _{11 to} 103 _mn arranged in a matrix constituting the pixel portion as a whole have a configuration unique to the present invention, which is different from the pixels of the liquid crystal display device described in Patent Document 1 described above. The constant current transistors 104 _{1 to} 104 _n are connected in units of pixels.

FIG. 2 shows an equivalent circuit diagram of the first embodiment of one pixel in the liquid crystal display device according to the present invention. In the figure, the same components as those in FIG. A pixel 103A shown in the equivalent circuit of FIG. 2 is a pixel according to any one of the first embodiments among the pixels 103 _{11 to} 103 _mn in FIG. Tr1 and Tr2 (referred to as NMOS transistors), P-channel MOS field effect transistors (hereinafter referred to as PMOS transistors) Tr3 and Tr4 for source followers whose gates are connected to the sources of the NMOS transistors Tr1 and Tr2, and NMOS transistors for switching A PMOS transistor Tr7 having a drain and a back gate connected in common to the sources and back gates of Tr5 and Tr6, PMOS transistors Tr3 and Tr4, two holding capacitors C1 and C2, and a pixel electrode to the source of the transistor Tr7 PE is connected Liquid crystal display element. Although not shown, this liquid crystal display element has a known configuration in which a liquid crystal layer is sandwiched between the pixel electrode PE and a common electrode (not shown).

  Further, the PMOS transistor Tr8 has a drain connected to a point B that is a common connection point of the PMOS transistors Tr3, Tr4, and Tr7, a source and a back gate connected to a power supply line of the power supply voltage VDD, and a gate connected to the control signal cur. It is connected to the. The PMOS transistor Tr8 corresponds to the constant current transistor 104i shown in FIG. 1 that is commonly connected to the point B in each pixel in the i-th column.

  In the pixel selection NMOS transistors Tr1 and Tr2, each drain is connected to a set of data lines (column signal lines) Di + and Di− in the i-th column, and each gate is connected to a gate line Gj in the same j-th row. A row selection signal SW1 is supplied and switching control is performed simultaneously. The storage capacitor C1 has one end connected to a connection point C between the source of the NMOS transistor Tr1 and the gate of the PMOS transistor Tr3, and the other end grounded. On the other hand, the holding capacitor C2 has one end connected to a connection point A between the source of the NMOS transistor Tr2 and the gate of the PMOS transistor Tr4, and the other end grounded. The source follower PMOS transistor Tr3 and the constant current PMOS transistor Tr8 constitute a first source follower circuit that drives the switching NMOS transistor Tr5. The source follower PMOS transistor Tr4 and the constant current PMOS transistor Tr8 constitute a second source follower circuit for driving the switching NMOS transistor Tr6.

  The first switching signal 2kp is applied to the gate of the PMOS transistor Tr5, and the second switching signal 2km is applied to the gate of the PMOS transistor Tr6. A control signal 2k is applied to the gate of the PMOS transistor Tr7. The transistors Tr3, Tr5, Tr4, Tr6, Tr7, and Tr8 are configured so that the positive pixel value held in the holding capacitor C1 and the negative pixel value held in the holding capacitor C2 are shorter than the vertical scanning cycle. A readout unit that alternately reads out to the pixel electrode PE is configured.

  In this embodiment, the source follower PMOS transistors Tr3 and Tr4 have their sources connected to the back gates. Further, the drain and back gate of the switching PMOS transistor Tr7 are commonly connected to the sources and back gates of the transistors Tr3 and Tr4. Further, the power supply potential VDD is applied to the back gate of the PMOS transistor Tr8. Since the back gates of the PMOS transistors Tr3, Tr4, Tr7, Tr8 are terminals of the same N well formed on the substrate, the N well potential is set to VDD. In this embodiment, one constant current PMOS transistor Tr8 is added for each pixel in each column. However, the number of transistors in the pixel 103A is the number of transistors in the pixel of the liquid crystal display device described in Patent Document 1. Since it is the same as the number, it is not necessary to change the pixel pitch.

  Next, the operation of the pixel 103A will be described with reference to the flowchart of FIG.

  In the writing period of the pixel 103A, the switching signals 2kp and 2km are set to the high level as shown in FIGS. 3F and 3G, respectively, and the PMOS transistors Tr5 and Tr6 are turned off. Further, the control signal cur is set to the high level as shown in FIG. 3E, and the PMOS transistor Tr8 is also turned off. In this state, as shown in FIG. 3C, when the row selection signal SW1 becomes high level from time t1 to time t2 for a period considerably shorter than one vertical scanning period (1V), it is connected to the gate line Gj. The pixels in the same row direction are selected, and the NMOS transistors Tr1 and Tr2 are simultaneously turned on.

  Thus, the positive DA conversion pixel value of the image data input from the horizontal drive circuit 102 through the data line (column signal line) Di + is sampled by the NMOS transistor Tr1 and held in the holding capacitor C1. At the same time, the negative DA conversion pixel value of the image data input from the horizontal drive circuit 102 through the data line (column signal line) Di− is sampled by the NMOS transistor Tr2 and held in the holding capacitor C2. Here, the voltage VC at point C held in the holding capacitor C1 and applied to the gate of the PMOS transistor Tr3, and the voltage VA at point A held in the holding capacitor C2 and applied to the gate of the PMOS transistor Tr4 are: Assume that the settings are as follows.

VC = Vp-Von1 (6)
Von1: Tr1 ON voltage Vp is larger than Tr1 threshold voltage Vth1
Vp: Signal voltage input from Di + VA = Vm-Von2 (7)
Von2: Tr2 ON voltage Vm is larger than Tr2 threshold voltage Vth2
When the row selection signal SW1 input from Vm: Di- is high level from time t1 to time t2, the voltages VC and VA change as shown in FIGS. 3A and 3B, respectively. To do.

  Next, in the readout period of the pixel 103A, the row selection signal SW1 is set to a low level after time t2 as shown in FIG. 3C, and the NMOS transistors Tr1 and Tr2 are turned off. In this state, when reading the positive holding voltage of the holding capacitor C1, as shown in FIG. 3H, the switching signal 2k is set to the low level at time t3 to turn on the PMOS transistor Tr7, and then the switching NMOS Of the transistors Tr5 and Tr6, only Tr5 is turned on by setting the switching signal 2kp to high level at time t4 as shown in FIG. 3F, and the control signal cur is turned on at time t5 as shown in FIG. By setting the low level, the constant current transistor Tr8 is turned on and a constant current flows. Thus, the positive holding voltage of the holding capacitor C1 is applied from the source of the source follower PMOS transistor Tr3 to the pixel electrode PE through the drain / source of the PMOS transistor Tr7. At this time, the read voltage VBp at the point B of the positive holding voltage is expressed by the following equation.

VBp = Vp-Von1 + Vth3 (8)
However, in the formula (8), Vth3 is a threshold voltage of the transistor Tr3 having no substrate effect, and is a fixed voltage and a voltage specific to the element. FIG. 3D shows the read voltage VB at point B, which becomes the voltage VBp expressed by the equation (2) after time t6 when the control signal cur becomes high level.

  Next, when reading the negative holding voltage of the holding capacitor C2, as shown in FIG. 3H, the switching NMOS transistor Tr5 and the switching NMOS transistor Tr5 and the PMOS transistor Tr7 are turned on with the switching signal 2k set to the low level. Of Tr6, only Tr6 is turned on by setting the switching signal 2km to high level at time t7 as shown in FIG. 3G, and the control signal cur is set to low level at time t8 as shown in FIG. 3E. As a result, the constant current transistor Tr8 is turned on to allow a constant current to flow. As a result, the negative holding voltage of the holding capacitor C2 is applied from the source of the source follower PMOS transistor Tr4 to the pixel electrode PE through the drain / source of the PMOS transistor Tr7. The read voltage VBm at the point B of the negative holding voltage at this time is expressed by the following equation.

VBm = Vm-Von2 + Vth4 (9)
However, in the formula (9), Vth4 is a threshold voltage of the transistor Tr4 which has no substrate effect, and is a fixed voltage which is a voltage peculiar to the element. As shown in FIG. 3D, the read voltage at the point B becomes the voltage VBm expressed by the equation (4) after time t9 when the control signal cur becomes high level.

  As the voltage applied to the liquid crystal layer, the ON voltage Von7 of the PMOS transistor Tr7 is added to the voltage at the point B. Therefore, the voltage Vop applied to the liquid crystal layer at the time of reading out the positive holding voltage and the voltage Vom applied to the liquid crystal layer at the time of reading out the negative holding voltage are expressed by the following equations, respectively.

Vop = VBp + Von7 (10)
Vom = VBm + Von7 (11)
In this case, the expressions (10) and (11) are effective when VBp or VBm is higher than the threshold voltage Vth of the PMOS transistor Tr7. The lower limit is limited by Vth.

  As a result, in the range where Von1, Von2, and Von7 are 0V, the above voltages Vop and Vom are expressed by the following equations from equations (8) to (11).

Vop = Vp + Vth3 (12)
Vom = Vm + Vth4 (13)
The threshold voltages Vth3 and Vth4 of the source follower PMOS transistors Tr3 and Tr4 in the above expressions (12) and (13) do not vary depending on the signal level (gate voltage) (no substrate effect) and become fixed voltages. Therefore, the holding voltage can be applied to the liquid crystal layer by an ideal source follower circuit having a gain of 1 by the source follower PMOS transistors Tr3 and Tr4. Thereafter, the NMOS transistors Tr5 and Tr6 are alternately switched at a predetermined cycle shorter than the vertical scanning cycle, and the same operation as described above is performed.

  As described above, in this embodiment, it is difficult to increase the number of transistors in the pixel, and the source of the PMOS transistor and the substrate (N well) are made to have the same potential by using the N well. However, the circuit of the pixel 103A as shown in FIG. 2 is configured by clearing the second restriction that only one type of potential N-well can be arranged in one pixel due to the process rule. As a result, the following effects can be obtained.

  (A) Since the substrate effect is eliminated, the linearity is substantially linear, and a holding voltage can be applied to the liquid crystal layer by an ideal source follower circuit having a gain of 1.

  (B) Due to the circuit configuration, since one constant current PMOS transistor Tr8 is provided in one column (one column) of the pixel portion, signal readout from the pixel 103A always takes one horizontal line, and therefore it takes time for readout. However, power consumption is reduced.

  (C) Since the current source is one constant-current PMOS transistor Tr8, the variation in output voltage due to current fluctuation for each pixel in the same column is reduced.

  Next, a second embodiment of the pixel in the liquid crystal display device according to the present invention will be described.

FIG. 4 shows an equivalent circuit diagram of the second embodiment of one pixel in the liquid crystal display device according to the present invention. In the figure, the same components as those in FIGS. 2 and 6 are denoted by the same reference numerals. A pixel 103B shown in the equivalent circuit of FIG. 4 is a pixel according to any one of the second embodiments among the pixels 103 _{11 to} 103 _mn in FIG. 1, and includes a PMOS transistor Tr11, NMOS transistors Tr12 and Tr13, and a PMOS transistor Tr14. And a gain 1 second differential amplifier composed of a PMOS transistor Tr11, NMOS transistors Tr12 and Tr13, and a PMOS transistor Tr16. The PMOS transistor Tr15 is a first switching transistor that operates or deactivates the first differential amplifier. The PMOS transistor Tr17 is a second switching transistor that operates or inactivates the second differential amplifier.

  A connection point C between the source of the NMOS transistor Tr1 and the storage capacitor C1 is connected to the gate of the PMOS transistor Tr14. The connection point A between the source of the NMOS transistor Tr2 and the storage capacitor C2 is connected to the gate of the PMOS transistor Tr16. The sources of the PMOS transistors Tr14 and Tr16 are commonly connected to the gates of the NMOS transistors Tr12 and Tr13. The drains of the PMOS transistors Tr14 and Tr16 are connected to the drain of the PMOS transistor Tr11 via the PMOS transistors Tr15 and Tr17.

  The PMOS transistor Tr18 has a gate connected to the wiring of the switching signal 2k, a drain connected to the connection point between the gate of the PMOS transistor Tr11 and the drain of the NMOS transistor Tr12, and a source connected to the pixel electrode PE. Transistor. A point B that is a common connection point of the PMOS transistors Tr11, Tr15, and Tr17 is connected to the drain of one constant current PMOS transistor Tr8 that is provided in common to a plurality of pixels in the same column. The back gates (N well terminals) of all the PMOS transistors Tr11, Tr14, Tr15, Tr16, Tr17 and the constant current PMOS transistor Tr8 in the pixel are all configured to be supplied with the power supply voltage VDD.

  Next, a specific operation of the pixel 103B of this embodiment will be described with reference to a timing chart of FIG. 5A and 5B show the voltages VC and VA at the connection points C and A in FIG. 4, and a plurality of one line connected to the gate line Gj by the row selection signal SW1 shown in FIG. When the transistors Tr1 and Tr2 in the pixel are turned on, the positive video signal Vp and the negative video signal Vm from the data lines Di + and Di− sampled by the transistors Tr1 and Tr2 are held in the holding capacitors C1 and C2. The Vp−Von1 and Vm−Von2 in FIGS. 5A and 5B indicate the holding voltages of the holding capacitors C1 and C2 shown in the equations (6) and (7).

  Thereafter, when reading the positive holding voltage of the holding capacitor C1, as shown in FIG. 5H, the switching signal 2k is set to the low level at time t11 to turn on the PMOS transistor Tr18, and then the switching signal at time t12. 2kp is set to the low level as shown in FIG. 5F, the PMOS transistor Tr15 is turned on, and the control signal cur is set to the low level at time t13 as shown in FIG. Turn on. At this time, since the switching signal 2 km is at a high level as shown in FIG. 5G, the PMOS transistor Tr 17 is off.

  When the PMOS transistor Tr15 is turned on, the first differential amplifier of gain 1 including the transistors Tr11, Tr12, Tr13, and Tr14 operates, and the positive holding voltage of the holding capacitor C1 applied to the gate of the PMOS transistor Tr14 is the first. 1 is applied to the drain of the PMOS transistor Tr18 through the differential amplifier, and further applied to the pixel electrode PE through the Tr18. Since the voltage at the connection point B at this time is (Vp−Von1) as shown in FIG. 5D, the positive holding voltage Vop applied to the pixel electrode PE is expressed by the following equation.

Vop = Vp-Von1 + Von18 (14)
In the equation (14), Von1 is an on-voltage of the transistor Tr1, and Von18 is an on-voltage of the transistor Tr18.

  After that, when reading the negative holding voltage of the holding capacitor C2, as shown in FIG. 5H, the switching signal 2k is set to the low level at time t14 to turn on the PMOS transistor Tr18, and then the switching signal at time t15. As shown in FIG. 5G, 2 km is set to the low level to turn on the PMOS transistor Tr17, and the control signal cur is set to the low level at time t16 as shown in FIG. Turn on. At this time, since the switching signal 2kp is at a high level as shown in FIG. 5F, the PMOS transistor Tr15 is off.

  When the PMOS transistor Tr17 is turned on, the second differential amplifier having a gain of 1 including the transistors Tr11, Tr12, Tr13, and Tr16 operates, and the negative holding voltage of the holding capacitor C2 applied to the gate of the PMOS transistor Tr16 is the first. 2 is applied to the drain of the PMOS transistor Tr18 through the differential amplifier, and further applied to the pixel electrode PE through the Tr18. Since the voltage at the connection point B at this time is (Vm−Von2) as shown in FIG. 5D, the negative holding voltage Vom applied to the pixel electrode PE is expressed by the following equation.

Vom = Vm-Von2 + Von18 (15)
In equation (15), Von2 is the on-voltage of the transistor Tr2, and Von18 is the on-voltage of the transistor Tr18. Thereafter, the PMOS transistors Tr15 and Tr17 are alternately switched at a predetermined cycle shorter than the vertical scanning cycle, and the same operation as described above is performed.

  As described above, according to the present embodiment, the number of transistors in the pixel is slightly increased as compared with the conventional case, but the restriction that only one N-type potential can be arranged in one pixel in accordance with the process rule is cleared. Thus, the pixel 103B shown in FIG. 4 is configured. Thus, according to the present embodiment, since the substrate effect of the source follower transistor is eliminated, the linearity is substantially linear, and the holding voltage can be applied to the liquid crystal layer by an ideal differential amplifier having a gain of 1. . Further, in the present embodiment, similarly to the embodiment of FIG. 2, since one constant current PMOS transistor Tr8 is provided in one column (one column) of the pixel portion, power consumption can be reduced, and Variations in output voltage due to current fluctuations for each pixel can also be reduced.

100 liquid crystal display device 101 a shift register and a comparator 102 horizontal driving circuit 103 ₁₁ ~103 _mn, 103A, 103B pixel 104 ₁ -104 _n constant current transistor 105 and 106 vertical driving circuit D1 + ~Dn +, Di + positive polarity side gate line (column Signal line)
D1- to Dn-, Di- Negative polarity side gate line (column signal line)
G1 to Gm, Gj gate lines (row scanning lines)
Tr1, Tr2 Pixel selection NMOS transistor Tr3, Tr4 Source follower PMOS transistor Tr5, Tr6, Tr7, Tr18 Switching PMOS transistor Tr8 Constant current PMOS transistor Tr11-Tr17 Differential amplifier transistor C1, C2 Holding capacitance PE Pixel electrode

Claims (2)

Each of a plurality of pixels provided at intersections where a plurality of sets of data lines and a plurality of row scanning lines intersect each other with two data lines as one set,
A display element in which a liquid crystal layer is sandwiched between a pixel electrode and a common electrode facing each other;
First sampling and holding means for sampling a positive video signal supplied via one of the two data lines in a set and holding it in a first holding capacitor for a certain period;
The negative polarity video signal having the opposite polarity to the positive polarity video signal supplied through the other data line of the set of the two data lines is sampled and held in the second holding capacitor for a certain period. Second sampling and holding means;
First and second source follower transistors each having a source connected to the back gate;
Separately connected to the drains of the first and second source follower transistors, the positive video signal voltage held in the first holding capacitor is output from the source of the first source follower transistor. The first and second switching operations for alternately outputting the negative video signal voltage held in the second holding capacitor from the source of the second source follower transistor at a predetermined cycle shorter than the vertical scanning cycle. Switching transistors of
A drain and a back gate are connected in common to the sources of the first and second source follower transistors, and a source is connected to the pixel electrode. Switching between the first and second switching transistors The positive video signal voltage held in the first holding capacitor input through the first source follower transistor and the second input through the second source follower transistor. A third switching transistor for applying a negative-polarity video signal voltage held in the holding capacitor to the pixel electrode;
A drain common to a common connection point of the first and second source follower transistors and the third switching transistor in the pixel for each pixel in the column direction of the plurality of pixels. A liquid crystal display device having a connected constant current transistor. Each of a plurality of pixels provided at intersections where a plurality of sets of data lines and a plurality of row scanning lines intersect each other with two data lines as one set,
A display element in which a liquid crystal layer is sandwiched between a pixel electrode and a common electrode facing each other;
First sampling and holding means for sampling a positive video signal supplied via one of the two data lines in a set and holding it in a first holding capacitor for a certain period;
The negative polarity video signal having the opposite polarity to the positive polarity video signal supplied through the other data line of the set of the two data lines is sampled and held in the second holding capacitor for a certain period. Second sampling and holding means;
A first differential amplifier of gain 1 for differentially amplifying and outputting the positive video signal voltage held in the first holding capacitor;
A second differential amplifier having a gain of 1 that differentially amplifies and outputs the negative video signal voltage held in the second holding capacitor;
The first and second differential amplifiers are alternately selected at a predetermined cycle shorter than a vertical scanning cycle, and the positive video signal voltage or the negative video signal voltage is output from the selected differential amplifier. First and second switching transistors;
The drains are commonly connected to the output terminals of the first and second differential amplifiers, and are switched in synchronization with the switching of the first and second switching transistors, and input through the first differential amplifier. A positive video signal voltage held in the first holding capacitor and a negative video signal voltage held in the second holding capacitor input through the second differential amplifier are applied to the pixel electrode. A third switching transistor;
A constant current transistor having a drain commonly connected to each drain of the first and second switching transistors in the pixel for each pixel in the column direction among the plurality of pixels. A characteristic liquid crystal display device.

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