JP2002156935A - Display driving circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a display driving circuit having low power consumption. SOLUTION: When a switch 11a is closed by a system selection signal LOE, input signals IN are held in a capacitor 12a and given to an N type amplifier 30a and a P type amplifier 50a. The output stage of the amplifier 30a is provided with switching transistors PMOS 38 and NMOS 40 which are turned on/off by output selection signals /SEL and SEL. The output stage of the amplifier 50a is provided with switching transistors PMOS 58 and NMOS 60 that are turned on/off by the output selection signals SEL and /SEL. Thus, either one of the amplifier 30a or the amplifier 50a is selected by the signals SEL. When a switch 13a is closed by the signal LOE, output signals OUT are outputted from the selected amplifier. Thus, the power consumption is reduced compared with a conventional push-pull type amplifier.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display drive circuit for sampling and holding an input signal in a liquid crystal display device or the like and driving the display device based on the held content.

[0002]

2. Description of the Related Art FIGS. 2A and 2B are schematic structural views of a conventional liquid crystal display device. FIG.
FIG. 2B is a diagram showing the configuration of the display drive unit. FIG.
As shown in FIG. 1A, this liquid crystal display device includes an RGB decoder 1, a display control unit 2, an inverting amplification unit 3, an amplification unit 4, a scanning driving unit 5, a display driving unit 6, and a liquid crystal panel 7. . The RGB decoder 1 separates the given video signal VS into a color signal and a composite synchronization signal,
(Red), G (green), and B (blue) are generated, and the horizontal and vertical synchronization signals SYN are generated from the composite synchronization signal. The synchronization signal SYN is supplied to the display control unit 2, and the color signals RGB are supplied to the inverting amplification unit 3.

The display control unit 2 includes a field line inversion signal FRP for inverting the polarity for each field line based on the synchronization signal SYN, a vertical control signal VER for controlling the operation of the scan drive unit 5, and a display drive unit. 6 to generate a horizontal control signal HOR for controlling the operation of FIG. The field line inversion signal FRP is output from the inversion amplifier 3
To the amplifier 4.

The inversion amplifying unit 3 inverts the polarity of the color signal RGB supplied from the RGB decoder 1 for each frame to generate an inversion signal / RGB and supplies it to the display driving unit 6. The amplifying unit 4 inverts the polarity of the common voltage signal VCM every field and every horizontal period and supplies the same to the liquid crystal panel 7 in accordance with the field line inversion signal FRP supplied from the display control unit 2.

The scan driver 5 sequentially selects the gate lines GL of the liquid crystal panel 7 according to the vertical control signal VER supplied from the display controller 2, and applies a gate pulse to the selected gate lines GL. . The display driver 6 is configured to control the horizontal control signal HOR supplied from the display controller 2.
, The inverted signal / RG supplied from the inverting amplifier 3
B is sampled and held for one line, and the held image signals are output in parallel to the signal line DL of the liquid crystal panel 7 in line units.

The liquid crystal panel 7 has pixel electrodes and TFTs (Thin Film Transistors) arranged in a matrix of i rows and j columns.
or) and a common electrode opposed to the pixel electrode via a liquid crystal. Each pixel electrode is connected to a corresponding signal line DL via a corresponding TFT. The gates of the TFTs in each column are connected to a common gate line GL. The liquid crystal panel 7 controls the direction of the liquid crystal to display an image by charging the pixel capacitance _CLC formed by the pixel electrode, the common electrode, and the liquid crystal through the gate line GL and the signal line DL. It has become.

[0007] As shown in FIG.
Are the CK generation / delay circuit 6a, shift register 6b, level shifter 6c, sample hold group 6d, amplifier group 6
e and a bias circuit 6f.

The CK generation / delay circuit 6a includes a display control unit 2
1 based on the basic clock signal MCK supplied from
Sampling clock CK for selecting each pixel on the line
Is generated and supplied to the shift register 6b.
The CK generation / delay circuit 6a generates a start pulse ST indicating the timing of starting the shift operation in accordance with the data line start signal STR supplied from the display control unit 2, and supplies the start pulse ST to the shift register 6b.

The shift register 6b is an n-bit shift register corresponding to the number n of the signal lines DL of the liquid crystal panel 7. The shift register 6b takes in the start pulse ST in accordance with the sampling clock CK and sequentially shifts the start pulse ST to generate a sampling pulse indicating the sampling timing of the video signal for the first to n-th display dots on one scanning line, and sends the sampling pulse to the level shifter 6c. They are output in parallel. The level shifter 6c includes the shift register 6
The sampling pulse supplied from b is converted from the voltage level of the logic circuit system to the voltage level of the drive circuit system and supplied to the sample / hold group 6d.

The sample / hold group 6d is composed of n sample / hold circuits corresponding to each signal line DL of the liquid crystal panel 7. The sample / hold circuit includes two circuits, operates alternately according to a system selection signal LOE, samples an inversion signal / RGB according to a sampling pulse supplied via a level shifter 6c, and holds the sampled signal. is there.

The amplifier group 6e includes a sample / hold group 6
It is composed of n amplifier circuits corresponding to each sample / hold circuit d. The amplifier circuit has two circuits,
It is connected to the output side of each system of the corresponding sample / hold circuit. One of the amplifier circuits operates, amplifies the image signal held by the sample / hold circuit, and outputs the amplified signal to the signal line DL of the liquid crystal panel 7. The bias circuit 6f supplies a bias voltage VB to each amplifier circuit of the amplifier group 6e.

FIGS. 3A and 3B are diagrams showing the configuration of the display drive circuit in FIG. This display drive circuit is shown in FIG.
Corresponds to the sample / hold circuit and the amplifier circuit of the sample / hold group 6d and the amplifier group 6e. FIG. 3A shows a block configuration of the display driving circuit, and FIG.
Shows the configuration of the amplifier in FIG.

As shown in FIG. 3A, this display drive circuit is a circuit corresponding to one signal line DL, and has switches 11a and 11b to which an input voltage IN is applied. Switches 11a and 11b are connected to a system selection signal LOE.
ON / OFF state is controlled complementarily by
Voltage holding capacitors 12a and 12b are connected between these output sides and the ground potential GND, respectively. Further, the outputs of the switches 11a and 11b are connected to the inputs of the amplifiers (AMP) 20a and 20b, respectively.

The outputs of the amplifiers 20a and 20b are connected to the inputs of the switches 13a and 13b, respectively.
The switches 13a and 13b are controlled on / off by a system selection signal LOE.
Is on, switch 13b is turned on, and switch 1 is turned on.
When the switch 1b is turned on, the switch 13a is controlled to be turned on. The outputs of the switches 13a and 13b are connected in common, and the output signal OUT is output from this.

The amplifiers 20a and 20b have the same configuration.
As shown in (b), it has a + input terminal and a-input terminal,
These input terminals are connected to the gates of N-channel MOS transistors (hereinafter, referred to as “NMOS”) 21 and 22, respectively. The drains of the NMOSs 21 and 22 are
Each is a P-channel MOS transistor (hereinafter referred to as “PM
OS ”) 23 and 24 are connected to the power supply potential VDD. The gates of the PMOS 23 and 24 are NMO
It is connected to the drain of S22. NMOS 21, 2
2 is connected to the ground potential GND via the NMOS 25.

The drain of the NMOS 21 is connected to the NMOS 26
And the drain of the NMOS 26 is connected to the power supply potential VDD. The source of the NMOS 26 is connected to the ground potential GND via the NMOS 27. The gates of the NMOSs 27 and 25 are supplied with a bias voltage VB.

The drain of the NMOS 21 is further connected to the gate of a PMOS 28 which is an output buffer. P
The source of the MOS 28 is connected to the power supply potential VDD, and the drain is an NMO constituting a push-pull type output buffer.
It is connected to the ground potential GND via S29.

The gate of the NMOS 29 is connected to the source of the NMOS 26, and the connection between the drain of the NMOS 29 and the drain of the PMOS 28 is the output terminal O of the amplifier.

In such a display drive circuit, when the system selection signal LOE is at level "H", the switches 11a,
13b is closed and switches 11b and 13a are opened. As a result, the input voltage IN is applied to the capacitor 12a.
The input voltage IN charged in the capacitor 12a is
The voltage is amplified at 0a, and a voltage corresponding to the input voltage IN is output to the output terminal of the amplifier 20a. However, since the switch 13a is open, the output voltage of the amplifier 20a is
It is not output as the output signal OUT. On the other hand, the voltage charged in the capacitor 12b is amplified by the amplifier 20b, and an output signal OUT is output from the output terminal of the amplifier 20b via the switch 13b.

Next, when the system selection signal LOE is at level "L"
, The switches 11a and 13b are opened and the switches 11b and 13a are closed. Thereby, the capacitor 1
2a is disconnected from the input voltage IN and this capacitor 1
A voltage corresponding to the input voltage IN before being charged into the amplifier 2a and amplified by the amplifier 20a is output as the output voltage OUT via the switch 13a. On the other hand, the capacitor 12b
Is supplied with a new input voltage IN, and a voltage corresponding to the new input voltage IN is output to the output side of the amplifier 20b.

As described above, two systems of sample / hold circuits and amplifier circuits are provided, and sampling and driving are performed by alternately switching the two systems by the system selection signal LOE. Thereby, the capacitors 12a and 12b
Since the liquid crystal panel 7 can be driven at all times without being affected by the charging time, a display with a high response speed and high luminance can be performed.

[0022]

However, the conventional display driving circuit has the following problems. As shown in FIG. 3B, the amplifiers 20a and 20b used in the amplifier circuit are of a push-pull type in which an output stage is configured by a PMOS 28 and an NMOS 29. In the push-pull type amplifier circuit, the gate voltage of the two transistors (PMOS 28 and NMOS 29) connected in series at the output stage constantly changes, so that the value of the current flowing through these transistors changes as needed. As a result, an output signal is output to the output terminal O. in this way,
In a push-pull type amplifier circuit, PMOS 28 and NM
There is a problem that an idle current always flows through the two buffer transistors of the OS 29, and power consumption increases.

The present invention solves the problems of the prior art and provides a display driving circuit with low power consumption.

[0024]

According to a first aspect of the present invention, an image signal of an input node is inputted when a first system is designated by a system selection signal. A first sample-and-hold unit for holding the image signal of the input node when a second system is designated by the system selection signal.
Sample and hold means, first and second amplifying means for amplifying the image signals held by the first and second sample and hold means, respectively, and when a first system is designated by the system selection signal Output means for outputting an output signal of the second amplifying means to an output node, and outputting an output signal of the first amplifying means to the output node when a second system is designated by the system selection signal Wherein the first and second amplifying means comprise:
The following first and second amplifiers are provided.

That is, the first amplifier has a switching transistor that is turned on when the output selection signal has a first value and turned off when the output selection signal has a second value, and the conduction state changes according to the level of the input signal. And an output stage in which a P-type transistor and a N-type transistor for passing a constant current are connected in series. A second amplifier connected in parallel with the first amplifier, a switching transistor which is turned off when the output selection signal is at a first value and turned on when the output selection signal is at a second value; And an output stage in which an N-type transistor whose conduction state changes according to the level of an input signal is connected in series.

According to the first aspect, since the display driving circuit is configured as described above, the following operation is performed. When the output selection signal has the first value, the switching transistor of the first amplifier in each amplifying means is turned on,
The image signal held by the sample and hold means is amplified by the first amplifier. When the output selection signal has the second value, the switching transistor of the second amplifier in each amplifying unit is turned on, and the image signal held by the sample and hold unit is amplified by the second amplifier. You.

According to a second aspect of the present invention, in the display drive circuit according to the first aspect of the present invention, the first and second amplifying means compares an input signal with a reference voltage, and when the input signal is higher than the reference voltage, A comparator is provided for outputting an output selection signal of a first value and outputting the output selection signal of the second value when the signal level is lower than the reference voltage.

According to the second aspect, the following operation is performed. In each amplifying unit, the image signal held by the sample-and-hold unit is compared by a comparator. If the image signal is equal to or higher than the reference voltage, an output selection signal having a first value is output. Thereby, the image signal is amplified by the first amplifier in the amplifying means. If the image signal is less than the reference voltage, a second value output selection signal is output from the comparator, and the image signal is amplified by the second amplifier in the amplifier.

[0029]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) FIGS.
FIG. 1C is a configuration diagram of a display drive circuit according to a first embodiment of the present invention. FIG. 2A is a block diagram of the display drive circuit, and FIGS. FIG.
The circuit of the N-type amplifier and the P-type amplifier in the middle is shown. This display drive circuit is used in the display drive unit 6 in the liquid crystal display device of FIG. 2 instead of the display drive circuit of FIG. 3, and the same elements as those of FIG. Have been.

As shown in FIG. 1A, in this display driving circuit, the input sides of switches 11a and 11b are commonly connected to a node N1 to which an input voltage IN is applied. The switches 11a and 11b are composed of switching transistors such as transfer gates, and are provided with a system selection signal LOE.
The on / off state is controlled in a complementary manner. For example, when the system selection signal LOE is "H", the switches 11a and 11b are set to be on and off, respectively. The outputs of the switches 11a and 11b
Voltage holding capacitors 12a and 12b are connected to nodes N2a and N2b, respectively, and between nodes N2a and N2b and ground potential GND, respectively.

The N-type amplifier 30a and the + input terminal of the P-type amplifier 50a connected to the voltage follower are connected to the node N2a. The output terminals of the N-type amplifier 30a and the P-type amplifier 50a are connected to the node N3a. It is connected. Similarly, to the node N2b, the + input terminals of the N-type amplifier 30b and the P-type amplifier 50b, which are connected by the voltage follower, are connected. The output terminals of the N-type amplifier 30b and the P-type amplifier 50b are connected to the node N3b. It is connected.

The N-type amplifiers 30a and 30b have the same configuration.
It has control terminals A and B to which an output selection signal SEL and an output selection signal / SEL inverted by the inverter 14 are supplied, respectively, and a bias terminal to which a bias voltage VBn is supplied. The P-type amplifiers 50a and 50b have the same configuration, and have control terminals A and B to which output selection signals SEL and / SEL are applied, respectively, and a bias terminal to which a bias voltage VBp is applied.

The inputs of switches 13a and 13b are connected to nodes N3a and N3b, respectively, and the outputs of switches 13a and 13b are connected to node N4. Switches 13a and 13b are switches 11a,
11b, they are set to be off and on when the system selection signal LOE is "H".
Then, the output signal OUT is output from the node N4.

As shown in FIG. 1B, the N-type amplifier 30
a and 30b have a + input terminal and a − input terminal, and these input terminals are NMOS 31 and 32 constituting a differential amplifier circuit.
Are connected to the respective gates. NMOS 31,
The drain of 32 is connected to the power supply potential VDD via PMOSs 33 and 34, respectively. PMOS 33, 3
The gate of No. 4 is connected to the drain of the NMOS 32. The sources of the NMOSs 31 and 32 are connected to the ground potential GND via the NMOS 35 forming a constant current circuit.

The drain of the NMOS 31 is connected to a PM for operation.
The source of the PMOS 36 is connected to the gate of the OS 36, and the source of the PMOS 36 is connected to the ground potential GND via the NMOS 37 forming the constant current circuit and the NMOS 40 for the switch controlled by the output selection signal SEL. The drain of the PMOS 36 is connected to the power supply potential VDD via the switching PMOS 38 controlled by the output selection signal / SEL. The gates of the NMOSs 35 and 37 are supplied with a bias voltage VBn. A capacitor 39 for phase compensation is connected between the gate and the drain of the PMOS 36,
The drain of the PMOS 36 is connected to the output terminal O of the N-type amplifier.
It has become.

As shown in FIG. 1C, the P-type amplifier 50
a, 50b have a + input terminal and a-input terminal, and these input terminals are NMOS 51, 52 constituting a differential amplifier circuit.
Are connected to the respective gates. NMOS 51,
52 are connected to the ground potential GND, and these N
The drains of the MOSs 51 and 52 are respectively connected to the PMOS5
3, 54 drains. PMOS 53,
The gate of the transistor 54 is connected to the drain of the NMOS 52, and the source is connected to the power supply potential VDD via the PMOS 55 forming a constant current circuit.

The drain of the NMOS 51 is connected to an NM for operation.
The source of the NMOS 56 is connected to the gate of the OS 56, and the source of the NMOS 56 is connected to the ground potential GND via the switching NMOS 60 controlled by the output selection signal / SEL. The drain of the NMOS 56 is connected to the drain of a PMOS 57 forming a constant current circuit.
Are connected to the power supply potential VDD via a switching PMOS 58 controlled by the output selection signal SEL. The gates of the PMOSs 55 and 57 are supplied with a bias voltage VBp. A capacitor 59 for phase compensation is connected between the gate and the drain of the NMOS 56, and the drain of the NMOS 56 is an output terminal O of the P-type amplifier.

Next, the operation will be described. In this display drive circuit, the level of the system selection signal LOE is switched between "H" and "L" every horizontal scanning period.

When the system selection signal LOE is "H",
The switches 11a and 13b are turned on, and the switch 11
b and 13a are turned off. As a result, the node N1 and the node N2a are connected, and the input voltage IN
2a. In addition, the node N2b is disconnected from the node N1, the node N3b is connected to the node N4, and the voltage held in the capacitor 12b in the previous period is amplified by the N-type amplifier 30b or the P-type amplifier 50b and the node N4 Is output as an output signal OUT.

Next, when the system selection signal LOE becomes "L", the switches 11a and 13b are turned off, and the switch 1
1b and 13a are turned on. Thereby, the node N2a
Is disconnected from the node N1, the node N3a is connected to the node N4, and the voltage held in the capacitor 12a while the system selection signal LOE is "H" is amplified by the N-type amplifier 30a or the P-type amplifier 50a. Node N
4 is output as an output signal OUT. Further, the node N1 and the node N2b are connected, and the input voltage IN is held in the capacitor 12b.

On the other hand, the output selection signal SEL is switched between "H" and "L" in a cycle shorter than the cycle of one horizontal scanning period.

When the output selection signal SEL is "H", the N-type amplifiers 30a and 30b, as shown in FIG.
The output selection signal SEL is applied to the gate of the NMOS 40, and the output selection signal / SEL (that is, "L") is applied to the gate of the PMOS 38. Thereby, the PMOS 38 and the NMO
S40 is turned on. On the other hand, the P-type amplifiers 50a and 50
0b, the output selection signal SE as shown in FIG.
Since L is applied to the gate of the PMOS 58 and the output selection signal / SEL is applied to the gate of the NMOS 60, these PMs
The OS 58 and the NMOS 60 are turned off. Therefore, N
The type amplifiers 30a and 30b become operable, and the operations of the P-type amplifiers 50a and 50b are stopped.

On the contrary, when the output selection signal SEL is "L",
The P-type amplifiers 50a and 50b become operable, and N
The operations of the mold amplifiers 30a and 30b are stopped.

As described above, the display drive circuit according to the first embodiment connects the N-type amplifier 30a (or 30b) and the P-type amplifier 50a (or 50b) in parallel and outputs the output selection signals SEL and / SEL. Is configured to operate only one of them. N-type amplifiers 30a, 30
b indicates that the NMOS 37 in the output stage serves as a constant current source for supplying a constant current by the bias voltage VBn, and the PMOS 36 serves as an operation buffer for determining the output voltage. The P-type amplifiers 50a and 50b are connected to the output stage PMOS5.
Reference numeral 7 denotes a constant current source for supplying a constant current by the bias voltage VBp, and the NMOS 56 serves as an operation buffer for determining an output voltage. Therefore, the current of these output stages is determined by the constant current source. For this reason, it is expected that the current in the output stage is suppressed, that is, the power consumption is reduced, as compared with a push-pull amplifier in which two buffers constantly operate.

(Second Embodiment) FIG. 4 shows a second embodiment of the present invention.
FIG. 2 is a configuration diagram of a display drive circuit according to the embodiment. This display drive circuit is used in place of the display drive circuit of FIG. 3 in the display drive section 6 in the liquid crystal display device of FIG. 2, similarly to the display drive circuit of FIG. In FIG. 4, elements common to those in FIG. 1 are denoted by common reference numerals.

As shown in FIG. 4, in this display drive circuit, comparators (CMP) 15a and 15b are provided, and these comparators 15a and 30b are connected to control terminals of N-type amplifiers 30a and 30b and P-type amplifiers 50a and 50b. , 15b are provided as output selection signals CA, / CACB, / CB.

That is, the comparator 15a is provided with a resistor 1 for voltage division.
Reference voltage VR generated by voltage division at 6, 17 and node N
2a, and compares the comparison result with the output selection signal C.
A is given to the control terminal A of the N-type amplifier 30a and the P-type amplifier 50a. Further, output selection signal CA is inverted by inverter 18a, and output selection signal / CA is inverted.
To the control terminal B of the N-type amplifier 30a and the P-type amplifier 50a.

Similarly, comparator 15b compares reference voltage VR with the voltage at node N2b, and uses the comparison result as output selection signal CB for N-type amplifier 30b and P-type amplifier 50b.
To the control terminal A. Further, the output selection signal CB is inverted by the inverter 18b and is supplied to the control terminals B of the N-type amplifier 30b and the P-type amplifier 50b as the output selection signal / CB.

Other configurations are the same as those in FIG. In this display drive circuit, as in FIG.
Thus, the two-system sample / hold circuit and the amplifier circuit are alternately switched.

On the other hand, the following operation is performed in the amplifier circuit. Node N2a voltage and reference voltage VR
Are compared by the comparator 15a. Here, if the voltage of the node N2a is higher than the reference voltage VR, the comparator 1
The output selection signal CA of the comparison result of 5a becomes "H". As a result, the N-type amplifier 30a becomes operable,
The operation of the P-type amplifier 50a is stopped.

On the contrary, if the voltage of the node N2a is lower than the reference voltage VR, the output selection signal CA of the comparison result becomes "L", the operation of the N-type amplifier 30a is stopped, and the P-type amplifier 50a can operate. State.

As described above, the display drive circuit according to the second embodiment connects the N-type amplifier 30a (or 30b) and the P-type amplifier 50a (or 50b) in parallel, and outputs the output selection signal CA (or CB). ) To operate only one of them. This is expected to suppress the current in the output stage, that is, reduce the power consumption, as in the first embodiment.

Further, when the input voltage IN is higher than the reference voltage VR, the N-type amplifiers 30a and 30b are operated, and when the input voltage IN is lower than the reference voltage VR, the P-type amplifier 5 is turned off.
0a and 50b are operated. Typically,
The N-type amplifier operates accurately in the high input voltage range,
The type amplifier has a feature that it operates accurately in a range where the input voltage is low. Thereby, there is an advantage that accurate operation can be performed over a wide range of the input voltage.

Note that the present invention is not limited to the above embodiment, and various modifications are possible. For example, there are the following modifications. (A) The display driving circuit applied to the liquid crystal display device has been described.
The present invention is applicable as a display drive circuit that samples and outputs a display signal.

(B) N-type amplifier and P shown in FIGS. 1 and 4
The circuit of the type amplifier is an example, and the present invention is not limited to this. A switching transistor whose output stage is on / off controlled by an output selection signal, an operation transistor whose conduction state is controlled in accordance with an input signal, and a circuit in which transistors constituting a constant current circuit are connected in series If so, it is equally applicable.

[0056]

As described above in detail, according to the first aspect, the amplifying means includes the first and second amplifiers, one of which is selected by the output selection signal to turn on the output stage. Have. Further, the output stages of these first and second amplifiers have a configuration in which a transistor for constant current and a transistor whose conduction state changes according to an input signal are connected in series. As a result, the current flowing to the output stage is limited, and power consumption can be reduced.

According to the second invention, the first invention has a comparator for outputting an output selection signal for selecting the first or second amplifier according to the result of comparison between the input signal and the reference voltage. Provided. Thus, in addition to the same effects as those of the first embodiment, there is an effect that an amplifier with high accuracy corresponding to the level of the input signal can be selected.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a display drive circuit according to a first embodiment of the present invention.

FIG. 2 is a schematic configuration diagram of a conventional liquid crystal display device.

FIG. 3 is a configuration diagram of a display drive circuit in FIG. 2;

FIG. 4 is a configuration diagram of a display drive circuit according to a second embodiment of the present invention.

[Explanation of symbols]

 11a, 11b, 13a, 13b Switch 12a, 12b Capacitor 15a, 15b Comparator 30a, 30b N-type amplifier 50a, 50b P-type amplifier

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G09G 3/36 G09G 3/36 F-term (Reference) 2H093 NC21 NC22 NC23 ND39 5C006 BB16 BC13 BF11 BF14 BF25 BF33 FA47 5C080 AA10 BB05 DD26 EE29 JJ02 JJ03

Claims (2)

[Claims] A first sample and hold means for inputting and holding an image signal of an input node when a first system is designated by a system selection signal; and a second system designated by the system selection signal. A second sample-and-hold means for inputting and holding the image signal of the input node, and first and second means for amplifying the image signals held by the first and second sample-and-hold means, respectively. And when the first system is specified by the system selection signal, the output signal of the second amplifier is output to an output node, and when the second system is specified by the system selection signal. Output means for outputting an output signal of the first amplifying means to the output node, wherein each of the first and second amplifying means has a first value when the output selection signal has a first value. Oh An output stage in which a transistor for a switch which is in a state and is turned off at the second value, a P-type transistor whose conduction state changes according to the level of an input signal, and an N-type transistor which flows a constant current is connected in series. A first amplifier having: a switching transistor connected in parallel to the first amplifier, and turned off when the output selection signal has a first value and turned on when the output selection signal has a second value; A display driver circuit comprising: a second amplifier having an output stage in which a P-type transistor for flowing current and an N-type transistor whose conduction state changes according to the level of an input signal are connected in series. 2. The display driving circuit according to claim 1, wherein the first and second amplifying means compare an input signal with a reference voltage, and when the input signal is higher than the reference voltage, the first value. And a comparator for outputting the output selection signal having the second value when the signal level is lower than the reference voltage.