JP2012134567A5 - - Google Patents
Download PDFInfo
- Publication number
- JP2012134567A5 JP2012134567A5 JP2012088982A JP2012088982A JP2012134567A5 JP 2012134567 A5 JP2012134567 A5 JP 2012134567A5 JP 2012088982 A JP2012088982 A JP 2012088982A JP 2012088982 A JP2012088982 A JP 2012088982A JP 2012134567 A5 JP2012134567 A5 JP 2012134567A5
- Authority
- JP
- Japan
- Prior art keywords
- insulating resin
- wiring board
- solder resist
- resin composition
- resist layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Description
半導体搭載用の基板などに用いられる多層ビルドアップ配線板は、コア基板の両面に絶縁層と導体層とを交互に積層された構造を有するものであり、これに半導体チップを搭載する場合は、配線板の外層表面にソルダーレジスト層を形成し、該ソルダーレジスト層に開口部を設け、該開口部に外部接続用の半田バンプを設け、半導体チップの電極と接続を行っている。
近年、電子機器の更なる小型化、大容量化に伴い、より一層の多層ビルドアップ配線板の薄型化、配線の微細化が進むことから、ソルダーレジスト層に対する要求が厳しくなってきている。半田パッド用開口部を形成するには、従来の写真法では、散乱光の影響により、微細な開口部を形成することが難しくなっておきており、レーザーによる開口が(例えば、特許文献1参照。)行われている。レーザー開口に伴いエポキシ樹脂などの熱硬化性樹脂を用いることが考えられている。しかし鉛フリー化に伴う、実装工程における半田リフロー温度の上昇に伴い、熱時のクラックが発生しやすくなる恐れがあり、特に配線板の薄型化に伴い、絶縁層とソルダーレジスト層の間に大きな線膨張係数を有する場合、両者の線膨張係数の相違に起因して生じる応力により熱衝撃性試験などの試験においてクラックが懸念され、耐湿性を含めた信頼性などの向上が望まれている。
A multilayer buildup wiring board used for a substrate for mounting a semiconductor has a structure in which insulating layers and conductor layers are alternately stacked on both sides of a core substrate, and in the case of mounting a semiconductor chip thereon, A solder resist layer is formed on the surface of the outer layer of the wiring board, an opening is provided in the solder resist layer, a solder bump for external connection is provided in the opening, and connection is made with the electrode of the semiconductor chip.
In recent years, with the further miniaturization of electronic devices and the increase in capacity, the thickness of multilayer buildup wiring boards has been further reduced, and the miniaturization of wiring has progressed, so the demand for a solder resist layer has become severe. In order to form the openings for solder pads, it is difficult to form fine openings due to the influence of scattered light in the conventional photographic method, and it is difficult to form openings by laser (see, for example, Patent Document 1) ) Is done. It is considered to use a thermosetting resin such as an epoxy resin along with the laser opening. However, with the increase of solder reflow temperature in the mounting process due to lead-free, there is a possibility that cracks during heat may easily occur. Especially with the thinning of the wiring board, a large area between the insulating layer and the solder resist layer When it has a linear expansion coefficient , a crack is concerned about in tests, such as a thermal shock resistance test, by stress which originates in a difference of both linear expansion coefficients , and improvement of reliability etc. including moisture resistance is desired.
本発明は、実装工程における半田リフロー温度の上昇に伴う熱時のクラックの発生、配線板の薄型化に伴う絶縁層とソルダーレジスト層との線膨張係数の相違に起因して生じる応力による熱衝撃性試験などの試験において発生するクラックなどの問題点を解決するためになされたものであり、その目的とするところは、耐湿性を含めた信頼性に優れた配線板を提供し、またその配線板に用いられる、著しく不純物が少なく、熱衝撃性に優れたソルダーレジスト用の絶縁樹脂組成物および導体回路が設けられた絶縁樹脂層と、該ソルダーレジスト層とを含んでなる配線板を提供することにある。 In the present invention, thermal shock is caused by the stress caused by the occurrence of cracks during heat accompanying the rise of the solder reflow temperature in the mounting process, and the difference in the coefficient of linear expansion between the insulating layer and the solder resist layer accompanying thinning of the wiring board. The present invention was made in order to solve problems such as cracks generated in tests such as conductivity tests, and the object of the present invention is to provide a highly reliable wiring board including moisture resistance, and the wiring thereof. Abstract: An insulating resin composition for a solder resist which is used in a plate, which is extremely low in impurities and excellent in thermal shock resistance, an insulating resin layer provided with a conductor circuit, and a wiring board comprising the solder resist layer. It is.
本発明者らは鋭意検討を行った結果、導体回路が設けられた絶縁層と、ソルダーレジスト層とを含んでなり、前記ソルダーレジスト層は前記導体回路と相対する位置に開口部を有する配線板において、ソルダーレジスト層と絶縁樹脂層を構成する絶縁樹脂組成物の硬化物の線膨張係数差が25℃以上ガラス転移温度以下において20ppm/K以下である配線板を見出し、この配線板はレーザー微細回路において耐半田性、熱衝撃試験に優れることから本発明を完成するに至ったものである。 As a result of intensive studies, the present inventors include an insulating layer provided with a conductor circuit and a solder resist layer, and the solder resist layer has a wiring board having an opening at a position facing the conductor circuit. Find a wiring board with a difference in linear expansion coefficient between the solder resist layer and the insulating resin composition and the cured product of the insulating resin composition of 20 ppm / K or less at 25.degree. C. or more and the glass transition temperature or less. The present invention has been completed because the circuit is excellent in solder resistance and thermal shock test.
このような目的は、[1]〜[14]に記載の本発明により達成される。
[1]導体回路が設けられた絶縁樹脂層と、ソルダーレジスト層とを含んでなる配線板であって、前記ソルダーレジスト層は前記導体回路と相対する位置に開口部を有するものであり、前記絶縁樹脂層と前記ソルダーレジスト層とが、絶縁樹脂と無機充填材とを含む絶縁樹脂組成物より構成されたものであり、前記ソルダーレジスト層と前記絶縁樹脂層を構成する前記絶縁樹脂組成物の硬化物は各々25℃以上のガラス転移温度を有しており、前記ソルダーレジスト層と前記絶縁樹脂層を構成する前記絶縁樹脂組成物の硬化物の25℃以上ガラス転移温度以下におけ
る線膨張係数差が20ppm/K以下であって、
前記絶縁樹脂層または前記ソルダーレジスト層を構成する前記絶縁樹脂組成物が、前記絶縁樹脂としてエポキシ樹脂とフェノキシ樹脂とを含む、配線板。
[2]前記ソルダーレジスト層を構成する前記絶縁樹脂組成物の硬化物の25℃以上ガラス転移温度以下における線膨張係数α1とガラス転移温度以上における線膨張係数α2との差(α2−α1)が50ppm/K以下である上記[1]に記載の配線板。
[3]前記絶縁樹脂層を構成する前記絶縁樹脂組成物の硬化物の25℃以上ガラス転移温度以下における線膨張係数α1とガラス転移温度以上における線膨張係数α2との差(α2−α1)が50ppm/K以下である上記[1]または[2]に記載の配線板。
[4]前記ソルダーレジスト層を構成する前記絶縁樹脂組成物の硬化物のガラス転移温度が200℃以上である上記[1]〜[3]のいずれか1項に記載の配線板。
[5]前記ソルダーレジスト層を構成する前記絶縁樹脂組成物の硬化物の線膨張係数α1が35ppm/K以下である上記[1]〜[4]のいずれか1項に記載の配線板。
[6]前記開口部がレーザー加工により形成される上記[1]〜[5]のいずれか1項に記載の配線板。
[7]前記ソルダーレジスト層を構成する該絶縁樹脂組成物中に含まれるNaイオンおよび塩素イオンがそれぞれ10ppm以下である上記[1]〜[3]のいずれか1項に記載の配線板。
[8]前記ソルダーレジスト層を構成する該絶縁樹脂組成物中に、着色剤としてハロゲンを含まない青色顔料とハロゲンを含まない黄色顔料および/またはハロゲンを含まない橙色顔料とを含むものである、上記[1]〜[7]のいずれか1項に記載の配線板。
[9]前記ハロゲンを含まない黄色顔料および/またはハロゲンを含まない橙色顔料の合計量と、前記ハロゲンを含まない青色顔料の量とが、重量比1:10〜10:1割合で調合された着色剤である、上記[8]に記載の配線板。
[10]前記ハロゲンを含まない黄色顔料がベンズイミダゾロンイエローである上記[8]または[9]に記載の配線板。
[11]前記ハロゲンを含まない青色顔料が銅フタロシアニンブルーである上記[8]〜[10]のいずれか1項に記載の配線板。
[12]前記着色剤の含有量が、ソルダーレジストを構成する該絶縁樹脂組成物に対して0.01〜5重量%である上記[8]〜[11]のいずれか1項に記載の配線板。
[13]前記絶縁樹脂層または前記ソルダーレジスト層を構成する前記絶縁樹脂組成物が、イミダゾール化合物をさらに含む[1]〜[12]のいずれか1項に記載の配線板。
[14][1]〜[13]のいずれか1項に記載された配線板に用いられる、ソルダーレジスト用絶縁樹脂組成物。
Such an object is achieved by the present invention described in [1] to [1 4 ].
[1] A wiring board comprising an insulating resin layer provided with a conductor circuit and a solder resist layer, wherein the solder resist layer has an opening at a position facing the conductor circuit, and the solder resist layer and the insulating resin layer, which is constituted of an insulating resin composition and an insulating resin and an inorganic filler, the insulating resin composition constituting the insulating resin layer and the solder resist layer cured product each have a glass transition temperature above 25 ° C., the linear expansion coefficient difference at 25 ° C. higher than the glass transition temperature or less of the cured product of the insulating resin composition constituting the insulating resin layer and the solder resist layer It der but less than 20ppm / K,
A wiring board , wherein the insulating resin composition constituting the insulating resin layer or the solder resist layer contains an epoxy resin and a phenoxy resin as the insulating resin .
[2] the difference between the linear expansion coefficient [alpha] 2 in the linear expansion coefficient [alpha] 1 and the glass transition temperature or more at a temperature lower than the glass transition temperature 25 ° C. or more cured product of the insulating resin composition constituting the solder resist layer (α2-α1) is The wiring board according to the above [1] , which is 50 ppm / K or less.
[3] the difference between the insulating linear expansion coefficient of the linear expansion coefficient [alpha] 1 and the glass transition temperature or higher at 25 ° C. higher than the glass transition temperature or less of the cured product of the resin composition [alpha] 2 constituting the insulating resin layer (α2-α1) is The wiring board according to the above [1] or [2] , which is 50 ppm / K or less.
[4] The wiring board according to any one of the above [1] to [3], wherein the glass transition temperature of the cured product of the insulating resin composition constituting the solder resist layer is 200 ° C. or higher.
[5] The wiring board according to any one of the above [1] to [4], wherein the linear expansion coefficient α1 of the cured product of the insulating resin composition constituting the solder resist layer is 35 ppm / K or less.
[6] above wherein the opening is made Rikatachi by the laser processing [1] to the wiring board according to any one of [5].
[7] The wiring board according to any one of the above [1] to [3], wherein Na ions and chlorine ions contained in the insulating resin composition constituting the solder resist layer are each 10 ppm or less.
[8] The insulating resin composition constituting the solder resist layer, the coloring agent comprising a halogen-free blue pigment and a halogen-free yellow pigment and / or a halogen-free orange pigment as described above. The wiring board of any one of 1]-[7].
[9] The total amount of the halogen-free yellow pigment and / or the halogen-free orange pigment and the amount of the halogen-free blue pigment are mixed at a weight ratio of 1:10 to 10: 1 The wiring board according to the above [8], which is a colorant.
[10] The wiring board according to the above [8] or [9], wherein the halogen-free yellow pigment is benzimidazolone yellow.
[11] The wiring board according to any one of the above [8] to [10], wherein the blue pigment containing no halogen is copper phthalocyanine blue.
[12] The wiring according to any one of the above [8] to [11], wherein the content of the coloring agent is 0.01 to 5% by weight with respect to the insulating resin composition constituting the solder resist. Board.
[13] The wiring board according to any one of [1] to [12], wherein the insulating resin composition constituting the insulating resin layer or the solder resist layer further contains an imidazole compound.
[14] An insulating resin composition for a solder resist , which is used for the wiring board described in any one of [1] to [1 3 ].
本発明の配線板は、絶縁樹脂層とソルダーレジスト層を構成する絶縁樹脂組成物の硬化物の線膨張係数差が25℃以上ガラス転移温度以下において20ppm/K以下であるものとすることにより、耐半田性試験、熱衝撃試験などの試験において絶縁樹脂層とソルダーレジスト層界面の応力集中を回避すると共に、ソルダーレジスト層を構成する絶縁樹脂組成物の硬化物のガラス転移温度が200℃以上であること、不純物として含まれるNaイオン、塩素イオンが10ppm以下であることから耐湿信頼性などの信頼性に優れた配線板である。 In the wiring board of the present invention, the linear expansion coefficient difference between the cured product of the insulating resin layer and the insulating resin composition constituting the solder resist layer is 20 ppm / K or less at a glass transition temperature of 25 ° C. or more. While avoiding stress concentration at the interface between the insulating resin layer and the solder resist layer in tests such as solder resistance test and thermal shock test, the glass transition temperature of the cured product of the insulating resin composition that constitutes the solder resist layer is 200 ° C or higher The wiring board is excellent in reliability such as moisture resistance and reliability because it contains 10 ppm or less of Na ions and chlorine ions contained as impurities.
次いで、上記で得たビルドアップ層が形成された基板10の最外層面に、絶縁樹脂組成物から構成されるソルダーレジスト層2を形成して、最外層にソルダーレジスト層が形成された基板11を得る(図2)。
前記ソルダーレジスト層として、ソルダーレジスト層と絶縁樹脂層を構成する絶縁樹脂組成物の硬化物の25℃以上ガラス転移温度以下における線膨張係数差は20ppm/K以下が好ましく、さらに好ましくは10ppm/K以下であり、さらには前記ソルダーレジスト層を構成する絶縁樹脂組成物の硬化物の25℃以上ガラス転移温度以下における線膨張係数α1とガラス転移温度以上における線膨張係数α2との差(α2−α1)は50ppm/K以下であることが好ましく、さらに好ましくは40ppm/K以下である。さらには、前記絶縁樹脂層を構成する絶縁樹脂組成物の硬化物の25℃以上ガラス転移温度以下における線膨張係数α1とガラス転移温度以上における線膨張係数α2との差(α2−α1)は50ppm/K以下であることが好ましく、さらに好ましくは40ppm/K以下である。また、ソルダーレジスト層を構成する絶縁樹脂組成物は、該絶縁樹脂組成物中に含まれるNaイオンおよび塩素イオンがそれぞれ10ppm以下であることが好ましく、さらに8ppm以下であることが好ましい。またその硬化物のガラス転移温度が200℃以上であることがさらに好ましい。
Next, the solder resist layer 2 composed of the insulating resin composition is formed on the outermost layer surface of the substrate 10 on which the buildup layer obtained above is formed, and the substrate 11 on which the solder resist layer is formed on the outermost layer. Get (Figure 2).
Examples solder resist layer, the difference in linear expansion coefficient at 25 ° C. higher than the glass transition temperature or less of the cured product of the insulating resin composition constituting the solder resist layer and the insulating resin layer is preferably from 20 ppm / K, more preferably 10 ppm / K The difference between the linear expansion coefficient α1 at 25 ° C. or more and the glass transition temperature or less of the cured product of the insulating resin composition constituting the solder resist layer and the linear expansion coefficient α2 at the glass transition temperature or more (α2−α1) Is preferably 50 ppm / K or less, more preferably 40 ppm / K or less. Furthermore, the difference (α2-α1) between the linear expansion coefficient α1 at 25 ° C. or higher and the glass transition temperature or lower of the cured resin composition constituting the insulating resin layer and the linear expansion coefficient α2 at the glass transition temperature or higher is 50 ppm / it is preferably K or less, more preferably not more than 40 ppm / K. Further, in the insulating resin composition constituting the solder resist layer, the Na ion and the chlorine ion contained in the insulating resin composition are each preferably 10 ppm or less, and more preferably 8 ppm or less. The arbitrary and even more preferred glass transition temperature of the cured product is 200 ° C. or higher.
(配線板の製造)
両面銅張積層板A(図5,住友ベークライト社製、ELC4785GS(220℃以下の線膨張係数13ppm/K)、以下両面板と記す)にドリルにて貫通スルーホールbを穿設(図6)し、上面と下面を導通させるためのスルーホールめっきcを施した。(図7)
(Manufacturing of wiring board)
A through hole b is drilled in a double-sided copper-clad laminate A (FIG. 5, manufactured by Sumitomo Bakelite, ELC 4785 GS (linear expansion coefficient 13 ppm / K 2 at 220 ° C. or less), hereinafter referred to as double-sided plate) (FIG. 6) Through-hole plating c for conducting the upper surface and the lower surface. (Figure 7)
(評価用単層フィルムの作製)
実施例1〜3で得た、絶縁樹脂層用樹脂付PETフィルム、ソルダーレジスト層用樹脂付PETフィルム1、2、3(以下、これらを合わせて樹脂付PETフィルムと称する)のPETフィルムを剥離して得た、単層絶縁樹脂フィルム(表1では絶縁樹脂)、単層ソルダーレジストフィルム1、2、3(表1ではそれぞれSR1、SR2、SR3)、および比較例1で用いたドライフィルム型感光性ソルダーレジスト(PFR800−AUS402)(表1ではDF型)のフィルム単体を熱硬化後、ガラス転移温度、線膨張係数α1・α2、Naイオン、塩素イオン不純物および1MHzにおける誘電率と誘電正接を以下に示す方法で測定した。
(Preparation of monolayer film for evaluation)
The PET film with resin for insulating resin layer obtained in Examples 1 to 3, PET film with resin for solder resist layer 1, 2 and 3 (hereinafter, these are collectively referred to as a PET film with resin) and peeled off The dry film type used in the single-layer insulating resin film (insulating resin in Table 1), single-layer solder resist films 1, 2, 3 (SR1, SR2, SR3 in Table 1) and Comparative Example 1 obtained by After heat curing of a film of photosensitive solder resist (PFR800-AUS402) (type DF in Table 1), the glass transition temperature , linear expansion coefficient α1 · α2, Na ion, chloride ion impurity, dielectric constant and dielectric loss tangent at 1 MHz It measured by the method shown below.
表2中の導通試験とは、実施例および比較例のビルドアップ配線板の外周部に設けられた導通測定用パッドを導通試験機(HIOKI:X=YC Hightester111 6)により接合不良または回路の断線発生の有無を検証する試験である。
表2中の剥離観察とは、ビルドアップ配線板の内層界面(例えば図5におけるb1とc1)を非破壊超音波式観察機(日立建機ファインテック株式会社:mi-scope hyper)にて密着しているか否かを判別する試験である。ここで、不良が発見された場合、断面観察によりサンプルを破壊してどの層間の剥離であるかの確認を行った。結果を表3に示す。また、ソルダーレジスト層と絶縁樹脂層を構成する絶縁樹脂組成物の硬化物の25℃以上ガラス転移温度以下における線膨張係数差は、上記測定した線膨張係数の結果より算出した。20ppm/K以下を○、20ppm/K以上を×として示した。
表3において、導通試験の項目で、完全に接続しているものは○、一箇所でも導通がされていない場合は×としている。剥離観察の項目では、剥離が観察されなかったサンプルを○、層間での剥離が観察されたサンプルを×としている。導通不具合、剥離が発生したものはその後の測定を中止した。
The continuity test in Table 2 means that the pads for continuity measurement provided on the outer peripheral portion of the buildup wiring boards of the example and the comparative example are joint failure or disconnection of the circuit by the continuity tester (HIOKI: X = YC Hightester 11 6) It is a test to verify the presence or absence of occurrence.
Peeling observation in Table 2 refers to adhesion of the inner layer interface (for example, b1 and c1 in FIG. 5) of the buildup wiring board with a nondestructive ultrasonic observation machine (Hitachi Construction Machinery Finetech Co., Ltd .: mi-scope hyper) It is a test to determine whether or not Here, in the case where a defect was found, the sample was broken by cross-sectional observation to confirm which layer is peeling. The results are shown in Table 3. Moreover, the linear expansion coefficient difference in 25 degreeC or more and glass transition temperature or less of the hardened | cured material of the insulation resin composition which comprises a soldering resist layer and an insulation resin layer was computed from the result of the linear expansion coefficient measured above. 20 ppm / K or less is shown as ○, and 20 ppm / K or more as x.
In Table 3, in the item of the continuity test, those which are completely connected are marked with ○, and even if only one point is not conductive, they are marked with x. In the item of exfoliation observation, the sample in which exfoliation was not observed is made ○, and the sample in which exfoliation between layers was observed is x. The continuity failure and the occurrence of peeling stopped the subsequent measurement.
これらの評価結果から明らかなように、ソルダーレジスト層と絶縁樹脂層を構成する絶縁樹脂組成物の硬化物の25℃以上ガラス転移温度以下における線膨張係数差が20ppm/K以下である実施例1〜3は、比較例1に比べて良好な温度サイクル試験、耐湿信頼性試験の結果を示した。 As is clear from these evaluation results, Example 1 in which the difference in linear expansion coefficient at 25 ° C. or more and the glass transition temperature or less of the cured product of the insulating resin composition constituting the solder resist layer and the insulating resin layer is 20 ppm / K or less. The result of ~ 3 showed the result of a good temperature cycle test and a moisture proof reliability test compared with comparative example 1.
Claims (14)
前記絶縁樹脂層または前記ソルダーレジスト層を構成する前記絶縁樹脂組成物が、前記絶縁樹脂としてエポキシ樹脂とフェノキシ樹脂とを含む、配線板。 A wiring board comprising an insulating resin layer provided with a conductor circuit and a solder resist layer, wherein the solder resist layer has an opening at a position facing the conductor circuit, and the insulating resin layer and the solder resist layer and is, has been constituted of an insulating resin composition and an insulating resin and an inorganic filler, a cured product of the insulating resin composition constituting the insulating resin layer and the solder resist layer each has a glass transition temperature above 25 ° C., the linear expansion coefficient difference at 25 ° C. higher than the glass transition temperature or less of the cured product of the insulating resin composition constituting the insulating resin layer and the solder resist layer is 20 ppm / K der below,
A wiring board , wherein the insulating resin composition constituting the insulating resin layer or the solder resist layer contains an epoxy resin and a phenoxy resin as the insulating resin .
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2012088982A JP5392373B2 (en) | 2005-12-28 | 2012-04-10 | WIRING BOARD AND INSULATION RESIN COMPOSITION FOR SOLDER RESIST USED FOR THE WIRING BOARD |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005377230 | 2005-12-28 | ||
JP2005377230 | 2005-12-28 | ||
JP2012088982A JP5392373B2 (en) | 2005-12-28 | 2012-04-10 | WIRING BOARD AND INSULATION RESIN COMPOSITION FOR SOLDER RESIST USED FOR THE WIRING BOARD |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2006352199A Division JP2007201453A (en) | 2005-12-28 | 2006-12-27 | Wiring board and insulating resin composition for solder resist used for same |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2012134567A JP2012134567A (en) | 2012-07-12 |
JP2012134567A5 true JP2012134567A5 (en) | 2012-08-23 |
JP5392373B2 JP5392373B2 (en) | 2014-01-22 |
Family
ID=46649692
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2012088982A Expired - Fee Related JP5392373B2 (en) | 2005-12-28 | 2012-04-10 | WIRING BOARD AND INSULATION RESIN COMPOSITION FOR SOLDER RESIST USED FOR THE WIRING BOARD |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP5392373B2 (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2017212400A (en) * | 2016-05-27 | 2017-11-30 | 住友ベークライト株式会社 | Resin sheet and circuit board |
JP7058467B2 (en) * | 2017-01-20 | 2022-04-22 | 住友ベークライト株式会社 | Resin sheet and circuit board |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5667934A (en) * | 1990-10-09 | 1997-09-16 | International Business Machines Corporation | Thermally stable photoimaging composition |
JP3686699B2 (en) * | 1995-03-31 | 2005-08-24 | 太陽インキ製造株式会社 | Alkali-developable photocurable / thermosetting resin composition |
JPH10306138A (en) * | 1997-03-03 | 1998-11-17 | Hitachi Chem Co Ltd | Photosensitive resin composition and production of printed wiring board using the same |
JP2001053448A (en) * | 1999-08-12 | 2001-02-23 | Ibiden Co Ltd | Printed wiring board, solder resist resin composition, and method for manufacturing printed wiring board |
JP2001094239A (en) * | 1999-09-22 | 2001-04-06 | Ibiden Co Ltd | Multilayer printed wiring board and semiconductor device |
JP3840043B2 (en) * | 2000-07-14 | 2006-11-01 | 京セラ株式会社 | Photosensitive solder resist layer, wiring board using the same, and electronic component module |
JP2002040663A (en) * | 2000-07-26 | 2002-02-06 | Taiyo Ink Mfg Ltd | Solder resist composition and its hardened product |
TWI237531B (en) * | 2000-12-13 | 2005-08-01 | Goo Chemical Co Ltd | Solder resist ink |
JP2002258476A (en) * | 2001-03-01 | 2002-09-11 | Toppan Printing Co Ltd | Insulating photosensitive resin composition and printed wiring board |
JP2003069229A (en) * | 2001-08-27 | 2003-03-07 | Ngk Spark Plug Co Ltd | Multilayer printed wiring board |
JP4268456B2 (en) * | 2002-06-07 | 2009-05-27 | 積水化学工業株式会社 | Resin substrate material |
JP4462872B2 (en) * | 2002-08-28 | 2010-05-12 | 京セラ株式会社 | Wiring board and manufacturing method thereof |
JP2004149763A (en) * | 2002-09-03 | 2004-05-27 | Ngk Spark Plug Co Ltd | Thermosetting resin composition and printed circuit board using the same |
JP4375957B2 (en) * | 2002-11-21 | 2009-12-02 | 太陽インキ製造株式会社 | Thermosetting resin composition |
JP4309225B2 (en) * | 2003-10-14 | 2009-08-05 | 太陽インキ製造株式会社 | Curable composition, cured product thereof and printed wiring board using the same |
JP4338570B2 (en) * | 2004-03-31 | 2009-10-07 | 三洋電機株式会社 | Element mounting substrate and semiconductor device using the same |
-
2012
- 2012-04-10 JP JP2012088982A patent/JP5392373B2/en not_active Expired - Fee Related
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US8148647B2 (en) | Printed circuit board and method of manufacturing the same | |
US20120047727A1 (en) | Flex-rigid wiring board and method for manufacturing the same | |
US20110019383A1 (en) | Wiring board and method for manufacturing the same | |
JP6747063B2 (en) | Glass circuit board | |
JPWO2010137421A1 (en) | Wiring board and manufacturing method thereof | |
KR101523818B1 (en) | Method For Manufacturing Wiring Board | |
TWI600350B (en) | Multilayer wiring board | |
JP6790847B2 (en) | Wiring board, multilayer wiring board and manufacturing method of wiring board | |
CN104508810B (en) | Circuit board | |
WO2017217138A1 (en) | Multilayer wiring board for inspection of electronic components | |
JP2004274035A (en) | Module having built-in electronic parts and method of manufacturing same | |
JP2010258390A (en) | Wiring board | |
US20140151100A1 (en) | Electronic component embedded printed circuit board | |
US20100236822A1 (en) | Wiring board and method for manufacturing the same | |
TW201429326A (en) | Printed circuit board with burried element and method for manufacture same and package structure | |
JP2012134567A5 (en) | ||
JP2002290052A (en) | Multilayer wiring board | |
KR101167453B1 (en) | A printed circuit board comprising embeded electronic component within and a method for manufacturing | |
TWI477214B (en) | Printed circuit board having buried component and method for manufacturing same | |
JP2000165052A (en) | Multilayer wiring board | |
JP2003110237A (en) | Multilayer interconnection board and multilayer semiconductor device | |
US20140353017A1 (en) | Printed wiring board and method for manufacturing the same | |
JP2003283145A (en) | Method of inspecting misregistration of multilayer wiring board | |
TWI663666B (en) | Method for manufacturing interposer having buried passive components | |
CN104604341A (en) | Wiring substrate and production method therefor |