JP2003283145A - Method of inspecting misregistration of multilayer wiring board - Google Patents
Method of inspecting misregistration of multilayer wiring boardInfo
- Publication number
- JP2003283145A JP2003283145A JP2002087066A JP2002087066A JP2003283145A JP 2003283145 A JP2003283145 A JP 2003283145A JP 2002087066 A JP2002087066 A JP 2002087066A JP 2002087066 A JP2002087066 A JP 2002087066A JP 2003283145 A JP2003283145 A JP 2003283145A
- Authority
- JP
- Japan
- Prior art keywords
- wiring board
- inspection
- multilayer wiring
- misregistration
- inspecting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 25
- 238000007689 inspection Methods 0.000 claims abstract description 43
- 238000010030 laminating Methods 0.000 claims abstract description 4
- 239000004020 conductor Substances 0.000 claims description 19
- 230000000149 penetrating effect Effects 0.000 claims description 3
- 239000000758 substrate Substances 0.000 abstract 3
- 238000009413 insulation Methods 0.000 abstract 2
- 239000010410 layer Substances 0.000 description 22
- 238000006073 displacement reaction Methods 0.000 description 10
- 238000012790 confirmation Methods 0.000 description 8
- 238000003475 lamination Methods 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 230000007547 defect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
Landscapes
- Measurement Of Length, Angles, Or The Like Using Electric Or Magnetic Means (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
【発明の詳細な説明】
【0001】
【発明の属する技術分野】本発明は、多層配線板の位置
ずれ検査方法に関するものである。
【0002】
【従来の技術】近年の電子機器の高機能化並びに軽薄短
小化の要求に伴い、電子部品の高密度集積化、さらには
高密度実装化が進んできており、これらの電子機器に使
用される半導体パッケージは、従来にも増して、益々小
型化かつ多ピン化が進んできている。
【0003】近年、ビルドアップ多層配線板が採用され
るようになっている。ビルドアップ多層配線板は、樹脂
のみで構成される絶縁層と導体とを、積み重ねて成形さ
れる。また、各層を一括で積層するために、各層にビア
ホールを設け、ビアホールの中を導電性の材料で埋めて
ビアポストを形成し、その上端部に半田層を設ける。そ
して、各層に半田層とそれに対するランドを設け、ビア
ポストとランドが、半田接合するように各層を積み重
ね、一括で加圧し、積層することができる。一括で積層
することは、各層を個別に製造できるので、従来の積層
法に比べて、低コスト化、工程の簡略化につながる。
【0004】しかし、この多層配線板においては、位置
ずれによる不良が発生する可能性があるため、検査が必
要となる。位置ずれの検査方法としては、X線による位
置ずれ検査や、導通による位置ずれ検査などがある。
【0005】X線による位置ずれ検査の方法では、X線
装置で多層配線板内部の位置ずれを観察することができ
るが、X線装置は高価であるという短所があり、かつ各
層の位置ずれを、ひとつひとつ目視で調べることは時間
がかかる。導通による位置ずれ検査の方法では、各層に
位置ずれ検査用ビアポストと位置ずれ検査用ランドを形
成し、その層における導通を調べることで、位置ずれの
精度を調べることが出来る。例えば、位置ずれ検査用ラ
ンドが円形で、その径をDaとし、位置ずれ検査用ポス
トの径をDbとし、多層配線板を一括積層で形成した
後、各層の位置ずれ検査用ビアポストと位置ずれ検査用
ランドの導通を測る。しかし、この方法では、位置ずれ
検査用ランド上に位置ずれ検査用ビアポストが乗ってい
なくても、位置ずれ検査用ビアポストと位置ずれ検査用
ランドがわずかでも接触していれば、判定が良となる。
よって位置精度は、
±(Da+Db)/2 ≦ 位置精度
で、表されるため、通常のポストとランドの径に対する
位置精度の算出方法である
±(Da−Db)/2 ≦ 位置精度
よりも、位置精度が大きくなる。このため、導体回路や
導体ポストが益々微細化してくることで位置精度を厳し
くすることに対応できない問題が生じてきている。
【0006】
【発明が解決しようとする課題】本発明は、位置精度を
小さくした多層配線板の容易かつ有効な位置ずれ検査方
法を提供することを目的とする。
【0007】
【課題を解決するための手段】即ち、本発明は、導体回
路、絶縁層、及び該絶縁層を貫通して、導体回路と接続
する導体ポストを有する複数の回路基板を一括積層して
得られる多層配線板の位置ずれ検査方法であって、回路
基板面に形成された位置ずれ検査用ポストと、相対抗す
る回路基板面に形成された該位置ずれ検査用ポストの断
面積よりも大きく中抜きされた位置ずれ検査用ランドと
の電気的導通により、判定されることを特徴とする、多
層配線板の位置ずれ検査方法である。
【0008】
【発明の実施の形態】以下、本発明による位置ずれ検査
方法の実施形態について説明するが、本発明はこれによ
って何ら限定されるものではない。
【0009】本発明の多層配線板の位置ずれ検査方法
は、導体回路、絶縁層、及び該絶縁層を貫通して、導体
回路と接続する導体ポストを有する複数の回路基板を一
括積層して得られる多層配線板に適用されるものであ
り、この多層配線板の位置ずれ検査方法について、図を
用いて説明する。
【0010】本発明の位置ずれ検査方法は、多層配線板
102(図1(b))を構成する各層の回路基板表面に
形成された導通確認用端子104の導通確認をし、導通
していないならば、該当する層の位置あわせは有効範囲
内であり、導通しているならば、位置あわせは有効範囲
外である確認ができるものである。このときの位置ずれ
検査部分103の導通していないときのイメージ図を図
1(a)に示す。
【0011】本発明において、位置ずれ検査部分103
としては、例えば、接続層の一方の面に露出して形成さ
れた位置ずれ検査用ポスト100、もう一方の面に露出
して形成された導通確認用端子104とを、導体ポスト
により層間接続、更には導通確認用導体回路105によ
り接続した接続層側検査部分と、相対する被接続層の表
面に位置ずれ検査用ランド101を形成し、前記同様に
して導通確認用導体回路及び導体ポスト形成して、もう
一方の面に導通確認用端子を形成した被接続層検査部分
とから成るものが挙げられる。
【0012】本発明において、多層配線板102には、
各回路基板ごとに位置ずれ検査用ポスト100、位置ず
れ検査用ランド101および導通確認用導体回路105
が内装されていて、多層配線板102に各層の導通確認
用端子104が表層に露出して形成されている必要があ
る。
【0013】本発明における位置精度としては、各回路
基板に形成された位置ずれ検査用端子104において、
位置ずれ検査用ランド101の抜けた円形の径をD1、
位置ずれ検査用ポスト100の径をD2としたとき、
±(D1−D2)/2 ≦ 位置精度
で、表すことができ、それぞれの径を調整することで、
位置精度を決定できる。例えば、位置ずれ検査用ランド
101の抜けた円形の径はφ150μm、位置ずれ検査
用ポスト100の径をφ50μmとすれば、位置精度≦
±50μmの検査が容易にできる。
【0014】本発明の位置ずれ検査の特徴は、導通を検
査するだけで、多層配線板の位置ずれ検査を確実に行え
るものであるので、例えば、フライングプローブチェッ
カーを用いることにより、大量に、早く、自動的に検査
を行える。
【0015】また、位置ずれ検査後に、図1(b)に示
すとおり、位置ずれ検査部分103を、予め多層配線板
102の周囲に設計し、切断面106a、106bで切
断し除去すると、多層配線板には位置ずれ検査部分が残
らず、配線パターンを制限することがなくなる。
【0016】
【発明の効果】本発明によれば、位置ずれ検査用ランド
と位置ずれ検査用ポストの導通確認をすることで、位置
精度を小さくした多層配線板の各層の位置ずれが容易か
つ有効に確認できる。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for inspecting the position of a multilayer wiring board. 2. Description of the Related Art With the recent demand for higher functionality and lighter and smaller electronic devices, high-density integration and high-density mounting of electronic components have been progressing. Semiconductor packages to be used are becoming smaller and have more pins than ever before. In recent years, build-up multilayer wiring boards have been adopted. The build-up multilayer wiring board is formed by stacking an insulating layer made of only a resin and a conductor. In order to stack the layers at once, a via hole is provided in each layer, a via post is formed by filling the via hole with a conductive material, and a solder layer is provided on the upper end thereof. Each layer is provided with a solder layer and a land corresponding thereto, and the via posts and the lands can be stacked and pressurized at once so that the via posts and the lands are joined by soldering. Since the layers are collectively laminated, each layer can be manufactured individually, which leads to lower costs and simplified processes as compared with the conventional lamination method. [0004] However, this multilayer wiring board needs to be inspected because there is a possibility that a defect occurs due to displacement. As a method of inspecting the positional deviation, there are a positional deviation inspection using X-rays and a positional deviation inspection due to conduction. [0005] In the method of inspecting the displacement using X-rays, the displacement within the multilayer wiring board can be observed with an X-ray device. However, the X-ray device is disadvantageous in that it is expensive. It takes time to inspect each item visually. In the method of the position shift inspection by conduction, the accuracy of the position shift can be checked by forming a position shift test via post and a position shift test land on each layer and checking the conduction in the layer. For example, after the positional deviation inspection land is circular, its diameter is set to Da, the diameter of the positional deviation inspection post is set to Db, and the multilayer wiring board is formed by batch lamination. Measure the continuity of the land. However, according to this method, even if the via hole for positional deviation inspection is not on the land for positional deviation inspection, the determination is good if the via post for positional deviation inspection and the land for positional deviation inspection are in slight contact. .
Therefore, since the position accuracy is expressed by ± (Da + Db) / 2 ≦ position accuracy, the position accuracy is ± (Da−Db) / 2 ≦ position accuracy, which is a method of calculating the position accuracy with respect to the diameter of a normal post and land. Position accuracy is increased. For this reason, there has been a problem that the conductor circuit and the conductor posts are becoming finer and more difficult to cope with strict positional accuracy. SUMMARY OF THE INVENTION An object of the present invention is to provide a method for easily and effectively detecting a positional deviation of a multilayer wiring board with reduced positional accuracy. That is, the present invention provides a method of laminating a plurality of circuit boards having a conductor circuit, an insulating layer, and a conductor post penetrating the insulating layer and connecting to the conductor circuit. A method for inspecting the positional deviation of a multilayer wiring board obtained by the method described above, wherein the cross-sectional area of the positional deviation inspection post formed on the circuit board surface and the cross-sectional area of the position deviation inspection post formed on the opposing circuit board surface This is a method for inspecting the positional deviation of a multilayer wiring board, characterized in that the judgment is made based on the electrical continuity with the land for the positional deviation inspection, which is largely hollowed out. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of a method for inspecting a position shift according to the present invention will be described, but the present invention is not limited thereto. [0009] A method for inspecting a misalignment of a multilayer wiring board according to the present invention is obtained by laminating a plurality of circuit boards each having a conductor circuit, an insulating layer, and a conductor post penetrating the insulating layer and connecting to the conductor circuit. This method is applied to a multi-layered wiring board to be used, and a method of inspecting the position of the multi-layered wiring board will be described with reference to the drawings. In the method for inspecting the positional deviation according to the present invention, the continuity of the continuity check terminal 104 formed on the surface of the circuit board of each layer constituting the multilayer wiring board 102 (FIG. 1B) is confirmed, and the continuity is not confirmed. Then, the alignment of the corresponding layer is within the effective range, and if it is conductive, it can be confirmed that the alignment is out of the effective range. FIG. 1A shows an image when the position shift inspection portion 103 is not conducting at this time. In the present invention, the position shift inspection portion 103
As an example, a misalignment inspection post 100 exposed on one surface of the connection layer and a conduction confirmation terminal 104 exposed on the other surface are connected to each other by a conductor post. Furthermore, a connection layer side inspection portion connected by the conduction confirmation conductor circuit 105 and a position displacement inspection land 101 are formed on the surface of the opposing connected layer, and a conduction confirmation conductor circuit and a conductor post are formed in the same manner as described above. And a connected layer inspection portion having a conduction confirmation terminal formed on the other surface. In the present invention, the multilayer wiring board 102 includes:
For each circuit board, a post 100 for position deviation inspection, a land 101 for position deviation inspection, and a conductor circuit 105 for conduction confirmation
It is necessary that the conduction confirmation terminals 104 of each layer are formed on the multilayer wiring board 102 so as to be exposed to the surface layer. The position accuracy in the present invention is as follows.
The diameter of the circular shape from which the land for inspection for positional deviation 101 has passed is D1,
When the diameter of the displacement inspection post 100 is D2, it can be expressed by ± (D1−D2) / 2 ≦ position accuracy, and by adjusting each diameter,
Position accuracy can be determined. For example, if the diameter of the circle from which the displacement inspection land 101 has passed is φ150 μm and the diameter of the displacement inspection post 100 is φ50 μm, the positional accuracy ≦
Inspection of ± 50 μm can be easily performed. The feature of the position shift inspection of the present invention is that the position shift inspection of the multilayer wiring board can be surely performed only by inspecting the continuity. Inspection can be performed automatically. Further, after the position shift inspection, as shown in FIG. 1B, a position shift inspection portion 103 is designed around the multilayer wiring board 102 in advance, and cut and removed at the cut surfaces 106a and 106b. There is no position shift inspection portion left on the board, and the wiring pattern is not restricted. According to the present invention, the continuity between the displacement inspection land and the displacement inspection post is confirmed, so that the displacement of each layer of the multilayer wiring board with reduced positional accuracy is easy and effective. Can be confirmed.
【図面の簡単な説明】
【図1】位置ずれ検査部分のイメージ斜視図および、位
置ずれ検査部分が内蔵された多層配線板の一例を示す断
面図である。
【符号の説明】
100:位置ずれ検査用ポスト
101:位置ずれ検査用ランド
102:多層配線板
103:位置ずれ検査部分
104:導通確認用端子
105:導通確認用導体回路
106a、106a:切断面BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a perspective view showing an image of a position shift inspection part and a cross-sectional view showing an example of a multilayer wiring board having a position shift inspection part built therein. [Description of Reference Numerals] 100: misalignment inspection post 101: misalignment inspection land 102: multilayer wiring board 103: misalignment inspection portion 104: conduction confirmation terminal 105: conduction confirmation conductor circuit 106a, 106a: cut surface
Claims (1)
して、導体回路と接続する導体ポストを有する複数の回
路基板を一括積層して得られる多層配線板の位置ずれ検
査方法であって、回路基板面に形成された位置ずれ検査
用ポストと、相対抗する回路基板面に形成された該位置
ずれ検査用ポストの断面積よりも大きく中抜きされた位
置ずれ検査用ランドとの電気的導通により、判定される
ことを特徴とする、多層配線板の位置ずれ検査方法。1. A multilayer wiring board obtained by laminating a plurality of circuit boards having a conductor circuit, an insulating layer, and a conductor post penetrating through the insulating layer and connecting to the conductor circuit. A position shift inspection method, wherein a position shift test post formed on a circuit board surface and a position shift hollowed out larger than the cross-sectional area of the position shift test post formed on an opposing circuit board surface A method for inspecting positional deviation of a multilayer wiring board, wherein the method is determined by electrical conduction with an inspection land.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2002087066A JP2003283145A (en) | 2002-03-26 | 2002-03-26 | Method of inspecting misregistration of multilayer wiring board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2002087066A JP2003283145A (en) | 2002-03-26 | 2002-03-26 | Method of inspecting misregistration of multilayer wiring board |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2003283145A true JP2003283145A (en) | 2003-10-03 |
Family
ID=29233431
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2002087066A Pending JP2003283145A (en) | 2002-03-26 | 2002-03-26 | Method of inspecting misregistration of multilayer wiring board |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2003283145A (en) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007059454A (en) * | 2005-08-22 | 2007-03-08 | Mitsumi Electric Co Ltd | Multilayer wiring board, and method of checking for bvh disconnection |
JP2009021401A (en) * | 2007-07-12 | 2009-01-29 | Panasonic Corp | Printed wiring board and printed wiring board inspection method |
JP2009200205A (en) * | 2008-02-21 | 2009-09-03 | Panasonic Corp | Circuit board, inspecting method for circuit board, and manufacturing method of circuit board |
JP2011066252A (en) * | 2009-09-18 | 2011-03-31 | Ngk Spark Plug Co Ltd | Multi-pattern wiring board and manufacturing method of the same |
JP2015070253A (en) * | 2013-10-01 | 2015-04-13 | 京セラ株式会社 | Multiple wiring board |
CN114113147A (en) * | 2021-11-17 | 2022-03-01 | 佛山市南海区广工大数控装备协同创新研究院 | Multilayer PCB (printed Circuit Board) stacking information extraction and level fool-proof detection method |
-
2002
- 2002-03-26 JP JP2002087066A patent/JP2003283145A/en active Pending
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007059454A (en) * | 2005-08-22 | 2007-03-08 | Mitsumi Electric Co Ltd | Multilayer wiring board, and method of checking for bvh disconnection |
JP2009021401A (en) * | 2007-07-12 | 2009-01-29 | Panasonic Corp | Printed wiring board and printed wiring board inspection method |
JP2009200205A (en) * | 2008-02-21 | 2009-09-03 | Panasonic Corp | Circuit board, inspecting method for circuit board, and manufacturing method of circuit board |
JP2011066252A (en) * | 2009-09-18 | 2011-03-31 | Ngk Spark Plug Co Ltd | Multi-pattern wiring board and manufacturing method of the same |
JP2015070253A (en) * | 2013-10-01 | 2015-04-13 | 京セラ株式会社 | Multiple wiring board |
CN114113147A (en) * | 2021-11-17 | 2022-03-01 | 佛山市南海区广工大数控装备协同创新研究院 | Multilayer PCB (printed Circuit Board) stacking information extraction and level fool-proof detection method |
CN114113147B (en) * | 2021-11-17 | 2024-05-14 | 佛山市南海区广工大数控装备协同创新研究院 | Multilayer PCB lamination information extraction and hierarchical fool-proof detection method |
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