JP2012103104A - Test device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To stabilize power supply voltage when simultaneously measuring a plurality of devices under test.SOLUTION: A test device 2a simultaneously tests a plurality of DUT 1. A common main power supply 10 supplies power to a power supply terminal P1 of the plurality of DUT 1. A power supply compensation circuit 20 includes a switch element which is controlled according to a control signal S, injects a compensation pulse current Iinto the power supply terminals P1 of the plurality of DUT 1, and/or pulls the compensation pulse current Iinto a different path from the plurality of DUT 1. For example, a pattern generator PG produces a common test patten Sto the plurality of DUT 1. The pattern generator PG changes a control pattern Saccording to the number of the DUT 1 so as to produce the compensation pulse current Iof amount proportional to the number of the DUT 1 under operation.

Description

  The present invention relates to a power supply stabilization technique.

  When testing a semiconductor integrated circuit (hereinafter referred to as DUT) such as a CPU (Central Processing Unit), DSP (Digital Signal Processor), and memory using CMOS (Complementary Metal Oxide Semiconductor) technology, flip-flops and latches in the DUT are When the clock is supplied, a current flows, and when the clock is stopped, the circuit becomes static and the current decreases. Therefore, the total operating current (load current) of the DUT varies from moment to moment depending on the contents of the test.

  A power supply circuit that supplies power to the DUT is configured using, for example, a regulator, and can ideally supply constant power regardless of the load current. However, an actual power supply circuit has an output impedance that cannot be ignored, and an impedance component that cannot be ignored exists between the power supply circuit and the DUT, so that the power supply voltage fluctuates due to load fluctuations.

  The fluctuation of the power supply voltage seriously affects the test margin of the DUT. In addition, fluctuations in the power supply voltage affect the operation of other circuit blocks in the test apparatus, such as a pattern generator that generates a pattern to be supplied to the DUT, and a timing generator that controls the pattern transition timing. Deteriorating accuracy.

  In the technique described in Patent Document 2, in addition to a main power supply that supplies a power supply voltage to a device under test, a compensation circuit including a switch that is controlled to be turned on and off by an output of a driver is provided. Then, a compensation control pattern for the switch element is defined in association with the test pattern so as to cancel the fluctuation of the power supply voltage that may occur according to the test pattern supplied to the device under test. During the actual test, the power supply voltage can be kept constant by switching the switch of the compensation circuit according to the control pattern while supplying the test pattern to the device under test.

JP 2007-205813 A International Publication No. 10 / 029709A1 Pamphlet

  Semiconductor device manufacturers want to reduce test time. Therefore, the test apparatus has a function of simultaneously testing a plurality of devices under test. When simultaneously measuring a plurality of devices under test, it is required to stabilize the power supply voltage for each device under test.

  The present invention has been made in view of such circumstances, and one exemplary object of one aspect thereof is to provide a test apparatus capable of stabilizing a power supply voltage when simultaneously measuring a plurality of devices under test. is there.

  One embodiment of the present invention relates to a test apparatus that simultaneously tests a plurality of devices under test each having a power supply terminal and an input / output terminal. The test apparatus includes a common main power supply that supplies power to power supply terminals of a plurality of devices under test, a power supply compensation circuit, a pattern generator, and a driver group. The power supply compensation circuit includes a switch element that is controlled in accordance with a control signal, generates a compensation pulse current when the switch element is turned on, and supplies the compensation pulse current to power supplies of a plurality of devices under test from a path different from the main power supply. A compensation pulse current is drawn into a different path from the plurality of devices under test from the power source current injected into the terminals and / or flowing from the main power source to the power terminals of the devices under test. The pattern generator generates a test pattern describing a test signal to be supplied to each input / output terminal of a plurality of devices under test, and a control pattern describing a control signal determined according to the test pattern. Each of the driver groups is provided for each input / output terminal, and a plurality of drivers that output test signals corresponding to the test pattern to the corresponding input / output terminals, and switch elements of the power compensation circuit according to the control signal corresponding to the control pattern And a driver for controlling.

  According to this aspect, the potential of the power supply terminals of the plurality of devices under test is kept constant by controlling the amount of the compensation current according to the total current of the operating currents flowing through each of the plurality of devices under test. A desired fluctuation can be generated in the terminal. In this configuration, since the main power supply and the power supply compensation circuit can be shared by a plurality of devices under test, there is an advantage from the viewpoint of hardware resources.

The pattern generator may generate a common test pattern for a plurality of devices under test. The pattern generator can change the control pattern according to the number of devices under test so that a compensation pulse current in an amount proportional to the number of devices under test is generated among the devices under test. Good.
When testing a plurality of devices under test at the same time, the devices under test for which pass or fail has been determined are excluded from the test, and the test sequence proceeds. Therefore, appropriate power supply compensation and power supply emulation can be realized by changing the amount of compensation pulse current according to the number of devices under test currently operating.

  The pattern generator may generate individual test patterns for a plurality of devices under test. The pattern generator outputs a control pattern obtained by synthesizing a plurality of control patterns corresponding to each of the test patterns given to the plurality of devices under test to a driver that controls the power supply compensation circuit.

  Another aspect of the present invention also relates to a test apparatus for simultaneously testing a plurality of devices under test each having a power supply terminal and an input / output terminal. The test apparatus includes a common main power supply that supplies power to power supply terminals of a plurality of devices under test, a plurality of power supply compensation circuits each provided for each device under test, a pattern generator, and a driver group. Prepare. Each power supply compensation circuit includes a switch element that is controlled in accordance with a control signal, generates a compensation pulse current when the switch element is turned on, and supplies the compensation pulse current from a path different from the main power supply to a device under test. The compensation pulse current is drawn into a different path from the corresponding device under test from the power source current injected into the power source terminal and / or flowing from the main power source to the power source terminal of the corresponding device under test. The pattern generator controls the test pattern that describes the test signal to be supplied to each input / output terminal of a plurality of devices under test and the control signal for each of the plurality of power supply compensation circuits determined according to the test pattern. Generate a pattern. Each driver group is provided for each input / output terminal, and a plurality of drivers that output test signals corresponding to the test pattern to the corresponding input / output terminals, and each driver compensation circuit is provided for each corresponding control pattern. And a plurality of drivers for controlling the switch elements of the corresponding power supply compensation circuit according to the control signal according to.

  According to this aspect, by providing the power supply compensation circuit for each device under test, the potential of the power supply terminal can be kept constant or a desired fluctuation can be generated for each device under test. In this configuration, since the main power supply can be shared by a plurality of devices under test, there is an advantage from the viewpoint of hardware resources.

  The pattern generator may generate a common test pattern for a plurality of devices under test. The pattern generator may output the control pattern to a driver that controls the power supply compensation circuit corresponding to the device under test among the plurality of devices under test.

  The test pattern may be defined for each of a plurality of devices under test. The pattern generator may output a control pattern defined for the test pattern for each device under test to a driver that controls the corresponding power supply compensation circuit.

  Note that any combination of the above-described constituent elements and the constituent elements and expressions of the present invention replaced with each other between methods and apparatuses are also effective as an aspect of the present invention.

  According to an aspect of the present invention, it is possible to stabilize the power supply voltage when simultaneously measuring a plurality of devices under test.

It is a circuit diagram which shows the structure of the test apparatus which concerns on embodiment. It is a flowchart which shows an example of the method of calculating a control pattern. It is a wave form diagram which shows an example of operating current _IOP , power supply current _IDD , source compensation current _ICMP, and source pulse current _ISRC . 4A and 4B are circuit diagrams illustrating a configuration example of the power supply compensation circuit. FIGS. 5A to 5C are circuit diagrams illustrating another configuration example of the power supply compensation circuit. It is a block diagram which shows the structure of the test apparatus which concerns on 1st Embodiment. It is a time chart which shows the operation example of the 1st mode of the test apparatus of FIG. It is a time chart which shows the operation example of the 2nd mode of the testing apparatus of FIG. It is a block diagram which shows the structure of the test apparatus which concerns on 2nd Embodiment.

  The present invention will be described below based on preferred embodiments with reference to the drawings. The same or equivalent components, members, and processes shown in the drawings are denoted by the same reference numerals, and repeated descriptions are omitted as appropriate. The embodiments do not limit the invention but are exemplifications, and all features and combinations thereof described in the embodiments are not necessarily essential to the invention.

  In this specification, “the state in which the member A is connected to the member B” means that the member A and the member B are physically directly connected, or the member A and the member B are electrically connected. The case where it is indirectly connected through another member that does not affect the state is also included. Similarly, “the state in which the member C is provided between the member A and the member B” refers to the case where the member A and the member C or the member B and the member C are directly connected, as well as an electrical condition. It includes the case of being indirectly connected through another member that does not affect the connection state.

  FIG. 1 is a circuit diagram showing a configuration of a test apparatus 2 according to the embodiment. FIG. 1 shows a semiconductor device (hereinafter referred to as DUT) 1 to be tested in addition to a test apparatus 2.

The DUT 1 includes a plurality of pins, at least one of which is a power supply terminal P1 for receiving the power supply voltage V _DD , and at least one other is a ground terminal P2. A plurality of input / output (I / O) terminals P3 are provided to receive data from the outside or to output data to the outside, and at the time of testing, test signals (tests) output from the test apparatus 2 Pattern) S _TEST is received or data corresponding to the test signal S _TEST is output to the test apparatus 2. FIG. 1 shows a configuration for giving a test signal to the DUT 1 among the configurations of the test apparatus 2, and a configuration for evaluating a signal from the DUT 1 is omitted.

  The test apparatus 2 includes a main power supply 10, a pattern generator PG, a plurality of timing generators TG and a waveform shaper FC, a plurality of drivers DR, and a power supply compensation circuit 20.

  The test apparatus 2 includes a plurality of n channels CH1 to CHn, some of which (CH1 to CH4) are allocated to the plurality of I / O terminals P3 of the DUT1. Although FIG. 1 shows a case where n = 6, the actual number of channels of the test apparatus 2 is on the order of hundreds to thousands.

The main power supply 10 generates a power supply voltage V _DD to be supplied to the power supply terminal P1 of the DUT 1. For example, the main power supply 10 is composed of a linear regulator, a switching regulator, and the like, and feedback-controls the power supply voltage V _DD supplied to the power supply terminal P1 so as to coincide with the target value. The capacitor Cs is provided to smooth the power supply voltage V _DD . The main power supply 10 generates a power supply voltage for other blocks inside the test apparatus 2 in addition to a power supply voltage for the DUT 1. The output current from the main power supply 10 to the power terminal P1 of DUT1, referred to as the power supply current _{I DD.}

The main power supply 10 are the voltage and current source having a response speed of the finite, there is a case where the load current, i.e. can not follow the abrupt change in the operating current I _OP of DUT1. For example, when the operating current I _OP changes stepwise, the power supply voltage V _DD may overshoot or undershoot, or be accompanied by subsequent ringing. Variations in the power supply voltage V _DD prevent accurate testing of DUT 1. This is because when an error is detected in DUT 1, it cannot be distinguished whether it is due to defective manufacturing of DUT 1 or due to fluctuations in power supply voltage V _DD .

The power supply compensation circuit 20 is provided to compensate for the response speed of the main power supply 10. The designer of the DUT 1 can estimate the time transition such as the operation rate of the internal circuit of the DUT 1 in a state where a certain known test signal S _TEST (test pattern S _PTN ) is supplied, so the operating current I _{OP of the} DUT 1 The time waveform can be accurately predicted. Here, the prediction includes calculation using computer simulation, actual measurement for devices having the same configuration, and the method is not particularly limited.

On the other hand, if the response speed (gain, feedback band) of the main power source 10 is known, the power source current I _DD generated by the main power source 10 in response to the predicted operating current I _OP can also be predicted. Then, the power supply voltage V _DD can be stabilized by making up the difference between the predicted operating current I _OP and the power supply current I _DD by the power supply compensation circuit 20.
A differential or integral relationship is established between the power supply voltage V _DD ′ and the power supply current I _DD . Specifically, depending on whether the impedance of the main power supply 10 and the path from the main power supply 10 to the power supply terminal P1 is dominant, capacitive, inductive, or resistive, the relationship between voltage and current differentiation and integration Is determined.

The power supply compensation circuit 20 includes a source compensation circuit 20a and a sink compensation circuit 20b. The source compensation circuit 20a can be switched on and off according to the control signal _SCNTa . When the source compensation circuit 20a is turned on in response to the control signal _SCNTa , a compensation pulse current (also referred to as a source pulse current) I _SRC is generated. The power supply compensation circuit 20 injects the source pulse current I _SRC into the power supply terminal P1 from a different path from the main power supply 10.

Similarly, the sink compensation circuit 20b can be switched on and off in accordance with the control signal _SCNTb . When sync compensation circuit 20b is turned on in response to the control signal _{S CNTb,} the compensation pulse current _{I SINK} (also referred to as a sink pulse current) is generated. Power compensation circuit 20 draws from the power supply current _{I DD} flowing into the power source terminal P1, the sync pulse current _{I SINK,} a separate path from the DUT1.

Between the operating current I _OP flowing into the power supply terminal P1 of the DUT 1, the power supply current I _DD output from the main power supply 10, and the compensation current _ICMP output from the power supply compensation circuit 20, Formula (1), (2) holds.
I _OP = I _DD + I _CMP (1)
_{I CMP = I SRC -I SINK ...} (2)
That is, the positive component of the compensation current _{I CMP} is supplied from the source compensation circuit 20a as the source pulse current _{I SRC,} negative components of the compensation current _{I CMP} is supplied from the sink compensation circuit 20b as a sink pulse current _{I SINK} .

Of the driver _DR 1 _{~DR 6,} the driver DR ₆ is assigned to the source compensation circuit 20a, the driver DR ₅ are assigned to the sink compensation circuit 20b. The other at least one driver DR _{1 to} DR ₄ is assigned to at least one I / O terminal P 3 of the DUT 1. The pattern generator PG, the drivers DR ₅ and DR ₆ , and the interface circuits 4 ₅ and 4 ₆ can be understood as control circuits that control the power supply compensation circuit 20.

The waveform shaper FC and the timing generator TG are collectively referred to as an interface circuit 4. The plurality of 4 ₁ to 4 ₆ are provided for each of the channels CH _{1 to} CH ₆ , in other words, for each of the drivers DR ₁ to DR ₆ . The i-th (1 ≦ i ≦ 6) interface circuit 4 _{i shapes the} input pattern signal S _PTNi into a signal format suitable for the driver DR, and outputs it to the corresponding driver DR _i .

The pattern generator PG generates a pattern signal _SPTN for the interface circuits 4 ₁ to 4 ₆ based on the test program. Specifically, for the drivers DR _{1 to} DR ₄ assigned to the I / O terminal P3 of the DUT 1, the pattern generator PG describes a test pattern S _PTNi that describes the test signal S _TESTi that each driver DR _i should generate. Is output to the interface circuit 4 _i corresponding to the driver DR _i . The test pattern S _PTNi includes data indicating the level in each cycle (unit interval) of the test signal S _TESTi and data describing the timing at which the signal level transitions.

The pattern generator PG generates the control patterns _{S PTN_CMP} for compensation which is determined according to the required compensation current _{I CMP.} Control pattern _{S PTN_CMP} includes a control pattern _{S PTN_CMPa} describing a control signal _{S CNTa} be generated driver DR ₆ which is assigned to the source compensation circuit 20a is, sink compensation circuit 20b to the assigned driver DR ₅ is controlled to be generated A control pattern S _{PTN_CMPb} describing the signal S _CNTb is included. The control patterns S _{PTN_CMPa} and S _{PTN_CMPb} include data designating the on / off state of the source compensation circuit 20a and the sink compensation circuit 20b in each cycle, and data describing the timing for switching on / off.

The pattern generator PG generates control patterns S _{PTN_CMPa} and S _{PTN_CMPb} that can compensate for the test patterns S _{PTN1 to} S _PTN4 , that is, according to the variation of the operating current of the DUT 1, and the corresponding interface circuit 4 _6. 4 and ₅ are output.

As described above, if the test patterns S _{PTN1 to} S _PTN4 are known, the time waveform of the operating current I _OP of the DUT 1 can be predicted, and the compensation current I _CMP to be generated in order to keep the power supply voltage V _DD constant, that is, The time waveforms of I _SRC and I _SINK can be calculated.
When the predicted operating current I _OP is larger than the power supply current I _DD , the power supply compensation circuit 20 generates the source compensation current I _SRC to compensate for the insufficient current. Since the current waveform required for the source compensation current I _SRC can be predicted, the source compensation circuit 20a is controlled so that it can be appropriately obtained. For example, the source compensation circuit 20a may be controlled by pulse width modulation. Alternatively, pulse amplitude modulation, ΔΣ modulation, pulse density modulation, pulse frequency modulation, or the like may be used.

FIG. 2 is a flowchart illustrating an example of a method for calculating a control pattern. Based on the test pattern and circuit information input to the DUT 1, the operating current I _{OP of the} DUT 1 is estimated (S100). Further, when the DUT 1 is connected to the main power source 10 as a load, when the event occurs in the DUT 1, the power source current I _DD output from the main power source 10 is calculated (S102). Then, when it is desired to achieve an ideal power is the difference between the estimated operating current _{I OP} and the power supply current _{I DD,} the compensation current _{I CMP} to be generated by the power supply compensation circuit 20 (S104).

Then, by applying ΔΣ modulation, PWM (pulse width modulation), PDM (pulse density modulation), PAM (pulse amplitude modulation), PFM (pulse frequency modulation), etc. to the waveform of the compensation current _ICMP to be generated, a bit is obtained. A stream control pattern _{SPTN_CMP} is generated (S106). For example, the compensation current _ICMP may be sampled every test cycle, and the sampled compensation current _ICMP may be pulse-modulated.

FIG. 3 is a waveform diagram showing an example of the operating current I _OP , the power supply current I _DD , the source compensation current _ICMP, and the source pulse current I _SRC . It is assumed that the operating current I _{OP of the} DUT 1 to which a certain test signal S _TEST is supplied increases stepwise. In response to this, the power supply current I _DD is supplied from the main power supply 10, but it does not become an ideal step waveform due to the limitation of the response speed, and the current to be supplied to the DUT 1 is insufficient. As a result, unless the compensation current I _SRC is supplied, the power supply voltage V _DD decreases as shown by a broken line.

The power supply compensation circuit 20 generates a source compensation current _ICMP corresponding to the difference between the operating current _IOP and the power supply current _IDD . The source compensation current I _CMP is given by the source pulse current I _SRC generated according to the control signal S _CNTa . The source compensation current _ICMP needs to be the maximum amount immediately after the change of the operating current _IOP , and then needs to be gradually reduced. Thus, for example, the necessary source compensation current _ICMP can be generated by reducing the on-time (duty ratio) of the source compensation circuit 20a with time using PWM (pulse width modulation).

When all the channels of the test apparatus 2 operate synchronously according to the test rate, the cycle of the control signal _{SCNTa is} the cycle of data supplied to the DUT 1 (unit interval), an integral multiple thereof, or an integral fraction. Equivalent to. For example, in the unit interval is 4ns system, the control signal if the _S period of the _CNTa is 4ns, each pulse of the ON period _{T ON} contained in the control signal _{S CNTa} can be adjusted between 0～4Ns. The response speed of the main power source 10 is on the order of a few hundred ns~ number .mu.s, the waveform of the compensation current I _CMP can be controlled by hundreds of pulses contained in the control signal S _CNTa. A method of deriving the control signal _SCNTa necessary for generating the source compensation current I _{SRC from} the waveform will be described later.

If the operating current _{I OP} to the opposite is smaller than the power supply current _{I DD,} the power supply compensation circuit 20 as the sink compensation current _{I CMP} is obtained by generating a sync pulse current _{I SINK,} pull the excessive current.

By providing the power supply compensation circuit 20, the lack of response speed of the main power supply 10 can be compensated, and the power supply voltage V _DD can be kept constant as shown by a solid line in FIG. 3. Further, as described above, since the power supply compensation circuit 20 can generate a pulse current having a stable amplitude, the power supply voltage can be compensated with high accuracy.

  The above is the description of the entire test apparatus 2.

Next, a specific configuration example of the power supply compensation circuit 20 will be described.
4A and 4B are circuit diagrams illustrating a configuration example of the power supply compensation circuit 20.
Reference is made to FIG. The source compensation circuit 20a includes a voltage source 22 that generates a voltage Vx higher than the power supply voltage V _DD and a source switch SW1. The source switch SW1 is provided between the output terminal of the voltage source 22 and the power supply terminal P1.
If the voltage Vx and the power supply voltage V _DD are constant, the amplitude of the source current I _SRC is as follows when the source switch SW1 is on.
I _SRC = (Vx−V _DD ) / R _ON1
Given in. R _ON1 is the ON resistance of the source switch SW1. 4A and 4B have an advantage that the power supply compensation circuit 20 can be configured to be small.

The sink compensation circuit 20b includes a sink switch SW2 provided between the power supply terminal P1 and the ground terminal. If the power supply voltage _{V DD} is constant, in a state where the sync switch SW2 is turned on, the amplitude of sink current _{I SINK} is
I _SINK = V _DD / R _ON2
Given in. R _ON2 is an on-resistance of the sink switch SW2.

Turning to FIG. The source compensation circuit 20a includes a source current source 24a and a source switch SW1. The source current source 24a generates a reference current that defines the amplitude of the source pulse current _ISRC . The source switch SW1 is provided on the path of the reference current from the source current source 24a.
The sink compensation circuit 20b includes a sink switch SW2 and a sink current source 24b. Sink current source 24b generates a reference current for defining the amplitude of the sync pulse current _{I SINK.} The sink switch SW2 is provided on the path of the reference current from the sink current source 24b.

Source pulse current _{I SRC,} the amplitude of the sync pulse current _{I SINK} may several A are required. In this case, the sizes of the source switch SW1 and the sink switch SW2 in FIGS. 4A and 4B are increased, and the gate capacitance is also increased. Due to this gate capacitance, the switching response speed of the source switch SW1 and sink switch SW2 may be reduced, and a desired current may not be generated.
The source switch SW1, or variations in the ON resistance _{R ON1, R ON2} sink switch SW2, the control signal _{S CNTa,} the amplitude of the _{S CNTb} varies, the degree of on of each switch varies, the pulse current _{I SRC,} I There is a possibility that the amplitude of _SINK may fluctuate.

When such a problem becomes significant, the following technique may be used to solve the problem. FIGS. 5A to 5C are circuit diagrams illustrating another configuration example of the power supply compensation circuit 20.
The source compensation circuit 20a in FIG. 5A includes a current D / A converter 26a, a first transistor M1a, a second transistor M2a, and a source switch SW1.

The current D / A converter 26a generates a reference current I _REF corresponding to the digital setting signal D _SET . The first transistor M1a and the second transistor M2a form a current mirror circuit, and generates a sync pulse current _{I SINK} of the reference current _{I REF} and multiplying a predetermined coefficient (mirror ratio K).

Specifically, the first transistor M1a is a P-channel MOSFET, and is provided on the path of the reference current _IREF . The second transistor M2 is also a P-channel MOSFET, and its gate is commonly connected to the gate and drain of the first transistor M1a.

In FIG. 5A, the source switch SW1 is provided between the gate of the first transistor M1a and the gate of the second transistor M2a. For example, the source switch SW1 may be configured with a transfer gate as shown in FIG. 5A, may be configured with only an N-channel MOSFET, or may be configured with only a P-channel MOSFET. The on / off state of the source switch SW1 is switched according to the control signal _SCNTa .

  In FIG. 5A, the drain N2 of the first transistor M1a is connected to the terminal N1 on the gate side of the first transistor M1a of the source switch SW1.

While the control signal _SCNTa is at a high level, the source switch SW1 is turned on. Then, the source pulse current I _SRC proportional to the reference current I _REF is discharged from the output terminal P4 of the source compensation circuit 20a. While the control signal _SCNTa is at a low level, the source switch SW1 is turned off and the current mirror circuit does not operate, so that the source pulse current I _SRC becomes zero.

As described above, according to the source compensation circuit 20a of FIG. 5A, the source pulse current I _SRC that is switched in accordance with the control signal _SCNTa can be generated.
According to the source compensation circuit 20a of FIG. 5A, the stability of the amplitude of the source pulse current I _SRC can be improved. Further, since the driver DR is driven not by a switch through which a large current flows but by a switch provided at the gate of the current mirror circuit, high-speed switching is possible.

Further, the source compensation circuit 20a of FIG. 5 (a), the source switch SW1 is also in the off state, the reference current _{I REF} continues to flow in the first transistor M1a, the bias state of the first transistor M1a is maintained. Therefore, there is an advantage that the switching response speed of the source compensation circuit 20a with respect to the switching of the source switch SW1 is high.

  The sink compensation circuit 20b can be configured by switching the conductivity of the transistor of the source compensation circuit 20a and inverting the top and bottom. FIG. 5A shows a configuration example of the sink compensation circuit 20b. The sink compensation circuit 20b includes a current D / A converter 26b, N-channel MOSFET transistors M1b and M2b, and a sink switch SW2. The sink compensation circuit 20b has the same advantages as the source compensation circuit 20a.

5B and 5C show only the configuration of the sink compensation circuit 20b, and the source compensation circuit 20a is omitted.
In FIG. 5B, the position of the sink switch SW2 is different from that in FIG. In FIG. 5B, the drain N2 of the first transistor M1b is connected to the terminal N3 on the gate side of the second transistor M2b of the sink switch SW2.
With this configuration, similarly to the configuration of FIG. 5 (a), it has a stable amplitude, can generate a sync pulse current I _SINK switching speed.
In FIG. 5B, the reference current _IREF is cut off when the sink switch SW2 is off. Therefore, there is an advantage that the current consumption of the circuit can be reduced.

In FIG. 5C, the sink switch SW2 is provided between a gate N4 commonly connected to the first transistor M1b and the second transistor M2b and a fixed voltage terminal such as a ground terminal. If the sink switch SW2 is turned on while the control signal _SCNTb # (# indicates logic inversion) is at a high level, the gate voltages of the first transistor M1 and the second transistor M2 become the ground voltage, so that the current mirror circuit is turned off. and sink pulse current _{I sINK} is interrupted. When the control signal _{S CNTb} # is low, when the sink switch SW2 is turned off, the current mirror circuit is turned on, flows sink pulse current _{I SINK.}

According to the configuration of FIG. 5 (c), the similar to FIG. 5 (a), (b) , it has a stable amplitude, can generate a sync pulse current _{I SINK} switching speed. Needless to say, the modifications of FIGS. 5B and 5C are also applicable to the source compensation circuit 20a.
Furthermore, the configuration shown in FIG. 5C may be combined with the configuration shown in FIG.

Further, the current flowing through the internal elements constituting the DUT 1, that is, the operating current I _OP varies due to process variations. That is, the waveform of the operating current of the DUT 1 to which a certain test pattern is supplied increases or decreases due to process variations. Therefore, prior to DUT1 testing process, by adjusting the amplitude of the compensation pulse current calibrate process, even as the operating current I _OP of DUT1 is varied by the process variations, to keep the power environment constant it can. This calibration can be realized by changing the value of the digital set value D _SET for the current D / A converters 26a and 26b.

  The above is the configuration example of the power supply compensation circuit 20.

  The test apparatus has a function of simultaneously testing a plurality of DUTs 1. When simultaneously measuring a plurality of devices under test, it is required to stabilize the power supply voltage for each device under test.

(First embodiment)
FIG. 6 is a block diagram showing a configuration of the test apparatus 2a according to the first embodiment. FIG. 6 illustrates a case in which N (N is an integer of 2 or more) DUTs 1 are simultaneously measured.

The main power supply 10 is provided commonly to a plurality of _{DUT1 1 to N,} and supplies power to a plurality of _{DUT1 1 to N.} The power supply compensation circuit 20 is also provided in common for the plurality of DUTs 11 to _N. The power supply compensation circuit 20 includes one or both of the source compensation circuit 20a and the sink compensation circuit 20b described above. The power supply compensation circuit 20 generates a compensation current I _CMP (I _SRC , I _SINK ) according to the control signal S _{CNT (a, b)} , and the compensation current I _CMP is separated from the main power supply 10 through a plurality of DUTs 1. Is injected into the power supply terminal P1 (source compensation circuit 20a). Or the power supply compensation circuit 20, the control signal generates a compensation current _{I CMP} according to the _{S CNT,} the power supply current _{I DD} flowing to the power supply terminal P1 of the plurality of DUT1 from the main power source 10, the compensation current _{I CMP,} a plurality DUT1 (Sink compensation circuit 20b).

The pattern generator PG generates a test pattern S _PTN that describes the test signal S _TEST to be supplied to each I / O terminal P3 of the plurality of _{DUTs 1,} and a control pattern S _{PTN_CMP} that describes the control signal S _CNT . The control pattern S _{PTN_CMP} is determined according to the test pattern S _PTN .

The driver group (also referred to as pin electronics) includes a plurality of drivers DR. The driver DR _{I / O} is provided for each I / O terminal P3, and outputs a test signal S _TEST corresponding to the test pattern _SPTN to the corresponding I / O terminal P3. The driver _{DR CMP} is the control signal _{S CNT} according to the control pattern _{S PTN_CMP,} controls the switching elements of the power supply compensation circuit 20 (source switch SW1, a sink switch SW2). In FIG. 6, the interface circuit 4 of FIG. 1 is omitted.

  The test apparatus 2a can be operated in any one of the following modes or by switching between them.

(First mode)
In this mode, the test pattern is defined in common for a plurality of DUTs 1. That is, the same set of test signals S _TEST (test vector) is given to the plurality of DUTs 1.

  When measuring a plurality of DUTs 1 at the same time, the DUT 1 for which a pass or a failure is determined in the course of the test may be excluded from the subsequent processing. Alternatively, when a certain DUT 1 finishes a certain process first, there is a case where another DUT 1 waits until the other DUT 1 completes the process. That is, in a test for a plurality of DUTs 1, not all DUTs 1 are always operating.

Therefore, the pattern generator PG responds to the number M of the operating DUTs 1 so that the compensation current _ICMP is generated in an amount proportional to the number M (M ≦ N) of the operating DUTs 1 among the plurality of DUTs 1. Thus, the control pattern _{SPTN_CMP} is changed. If the variation of DUT 1 is ignored, the operating current I _{OP of} DUT 1 to which the same test signal S _TEST is applied becomes equal. Therefore, the power supply compensation circuit 20 may generate a compensation current _{I CMP} of an amount proportional to the number M of DUT1 during operation. The amount of the compensation current I _CMP may be changed by adjusting the duty ratio of the compensation pulse currents I _SRC and I _SINK , or may be changed by adjusting their amplitudes. The pattern generator PG is provided with information on the number M of operating _{DUTs 1} , and the control pattern _{SPTN_CMP} is changed according to the number M.

FIG. 7 is a time chart showing an operation example of the first mode of the test apparatus 2a of FIG. For example, in periods T1, T2, and T3, different test patterns are generated, and a DUT that passes all the test patterns is determined as a non-defective product. Therefore, although the waveform of the operating current I _OP in each period is different, FIG. 7 shows the operating current I _{OP in the} periods T1, T2, and T3 as the same for the sake of simplicity. In the period T1, M = 3 DUTs 1 are operating. When the DUT1 ₃ is determined to be failed by the test in the period T1, in the subsequent period T2, the operating current _IOP3 of the DUT1 ₃ becomes zero and M = 2. As a result, the amplitude of the compensation current _ICMP becomes smaller than the period T1. When DUT1 ₁ in the period T2 is determined failed, the period T3, M = 1, and the result it is sufficient to compensate for changes in the operating current _{I OP2} of DUT1 _2, the amplitude of the compensation current _{I CMP1} is 1 period T1 / 3.

In other words, when supplying one test pattern _{S PTN} to one DUT1, unit compensation current _{I CMP_U} to be supplied to one of DUT1 is calculated, the unit control pattern _{S PTN_CMP_U} accordingly defined. The compensation current _ICMP to be generated by the power supply compensation circuit 20 when M DUTs 1 are valid is:
I _CMP = I _{CMP_U} × M
It is. Power compensation circuit 20, so that the compensation current _{I CMP} is obtained by correcting the unit control pattern _{S PTN_CMP_U,} generates the control patterns _{S PTN_CMP.} In the correction, the pulse width specified by the unit control pattern _{SPTN_CMP_U} may be multiplied by M, or the pulse amplitude specified by the unit control pattern _{SPTN_CMP_U} may be multiplied by M.

Alternatively, when ranking a plurality of DUTs 1 by performance, for example, when classifying those that operate at high speed as class A products, those that operate at medium speed as class B products, and those that operate at low speeds as class C products, performs a fast test in T1, the DUT1 ₃ which has passed is determined that the a grade, thereafter a non-operation by excluding from the test subject. Subsequently performed medium speed test in the period T2 and may determine DUT1 ₁ which passed as B grade. In this case, the passed DUT is excluded from further processing.

(Second mode)
In this mode, the test pattern _SPTN is defined independently for each of the plurality of DUTs 1. Pattern generator other words PG is individually generates a test pattern _{S PTN} for a plurality of DUT1. The individual control pattern _{S PTN_CMP_U} is defined for each test pattern _{S PTN.} The pattern generator PG generates a control pattern S _{PTN_CMP} by synthesizing a plurality of individual control patterns S _{PTN_CMP_U} corresponding to the test patterns S _PTN given to the plurality of _{DUTs 1} , and supplies the control pattern S _{PTN_CMP} to the driver DR _CMP that controls the power supply compensation circuit 20. Output.

When the test pattern S _PTN supplied to the i-th DUT1 _i is known, its operating current I _OPi is estimated, and a unit compensation current I _{CMP_Ui} necessary to compensate it is calculated. At this time, the compensation current I _CMP for compensating the total ΣI _OP of the operation currents I _OP of the plurality of DUTs is:
I _CMP = Σ _{i = 1: N} I _{CMP_Ui}
It becomes. To generate this compensation current _{I CMP,} power compensation circuit 20 synthesizes a plurality of individual control pattern _{S PTN_CMP_U1} ~S _{PTN_CMP_UN,} generates the control patterns _{S PTN_CMP.} For example, the synthesis may target the pulse width of the compensation pulse current. That is, when the pulse width defined by the control pattern S _{PTN_CMP} is ΔT and the pulse width defined by each individual control pattern S _{PTN_CMP_Ui} is ΔT _i ,
ΔT = Σ _{i = 1: N} ΔT _i
The control pattern _{SPTN_CMP} may be defined so that

Alternatively, the synthesis may target the amplitude of the compensation pulse current. That is, when the amplitude defined by the control pattern S _{PTN_CMP} is A and the amplitude defined by each individual control pattern S _{PTN_CMP_Ui} is A _i ,
A = Σ _{i = 1: N} A _i
The control pattern _{SPTN_CMP} may be defined so that

FIG. 8 is a time chart showing an operation example of the second mode of the test apparatus 2a of FIG. Separate test patterns S _PTN are supplied to the two DUTs 1, and different operating currents I _OP1 and I _OP2 flow. Power compensation circuit 20, the operation current _{I OP1, I OP2} unit compensation current _I CMP_U1 be generated for _each, to produce a compensation current _{I CMP} obtained by combining the _{I CMP_U2.} As a result, the power supply voltage V _DD of the plurality of DUTs 1 can be stabilized.

Even in this mode, when a certain DUT 1 becomes inactive, the individual control pattern _{SPTN_CMP_U} corresponding to the DUT 1 may be excluded.

(Third mode)
In the third mode, as in the second mode, the test pattern _SPTN is defined independently for each of the plurality of DUTs 1. Pattern generator other words PG is individually generates a test pattern _{S PTN} for a plurality of DUT1.
When the test pattern S _PTN supplied to the i-th DUT1 _i is known, its operating current I _OPi is estimated, and a unit compensation current I _{CMP_Ui} necessary to compensate it is calculated. At this time, the compensation current I _CMP for compensating the total ΣI _OP of the operation currents I _OP of the plurality of DUTs is:
I _CMP = Σ _{i = 1: N} I _{CMP_Ui}
It becomes. In the third mode, the control pattern _{S PTN_CMP} for generating a compensation current _{I CMP} is specified, the unit compensating pattern _{S PTN_CMP_U} the second mode is not specified, not perform the synthesis process of the pattern.

According to the test apparatus 2a according to the first embodiment, depending on the total current of the operating current I _OP flowing through the plurality of DUT1 respectively, the compensation current can control the amount of I _CMP, power of a plurality of DUT1 The potential V _{DD of the} terminal P1 can be kept constant.

In the first and second modes, even if the number M of operating DUTs 1 changes during the test sequence, the compensation amount can be optimized accordingly.
Furthermore, in this configuration, since the main power supply 10 and the power supply compensation circuit 20 can be shared by a plurality of DUTs 1, there is an advantage from the viewpoint of hardware resources.

(Second Embodiment)
FIG. 9 is a block diagram showing a configuration of a test apparatus 2b according to the second embodiment. In the test apparatus 2b of FIG. 9, a power supply compensation circuit 20 is provided for each DUT1. Other configurations are the same as those of the test apparatus 2a of FIG.

  The test apparatus 2b can be operated in any of the following plural modes or by switching them.

(First mode)
In this mode, the test pattern _SPTN is defined in common for the plurality of DUTs 1. That is, the same set of test signals S _TEST (test vector) is given to the plurality of DUTs 1. Then, the system calculates the operating current _{I OP} and the unit compensation current _{I CMP_U} flows to one in response to the test pattern _{S PTN} DUT1, the unit control pattern _{S PTN_CMP_U} is defined.

The pattern generator PG outputs a control pattern _{SPTN_CMP_U} to the driver DR _CMP that controls the power supply compensation circuit 20 corresponding to the operating DUT 1 among the plurality of _DUTs 1. The driver DR _CMP assigned to the non-operating power supply compensation circuit 20 is disabled.

(Second mode)
In the second mode, the test pattern _SPTN is defined for each of the plurality of DUTs 1. The control pattern S _{PTN_CMP} is defined for each test pattern S _PTN . The pattern generator PG outputs a test pattern _SPTN to the driver DR _{I / O} assigned to the i-th DUT1 _i, and sends the test pattern _SPTN to the driver DR _CMP assigned to the i-th power compensation circuit 20 _i. A control pattern S _{PTN_CMP} defined for the test pattern S _PTN is output.

  According to the second embodiment, the plurality of power supply compensation circuits 20 can be controlled independently, and the potential of the power supply terminal P1 can be kept constant for each DUT1. Alternatively, different voltage fluctuations can be generated for each power supply terminal P1 of the DUT 1. Also, with this configuration, since the main power supply 10 can be shared by a plurality of DUTs 1, there is an advantage from the viewpoint of hardware resources.

  Although the present invention has been described based on the embodiments, the embodiments merely show the principle and application of the present invention, and the embodiments depart from the idea of the present invention defined in the claims. Many modifications and changes in the arrangement are allowed within the range not to be performed.

In the embodiment, the case where the main power supply 10 is provided in common to the plurality of DUTs 11 to _N has been described, but the present invention is not limited thereto. That is, the main power supply 10 may be provided independently for the plurality of DUTs 11 to _N.

In the embodiment, a case has been described in which the compensation current _ICMP realizes an ideal power supply environment in which the fluctuation of the power supply voltage is zero, that is, the output impedance is zero. However, the present invention is not limited thereto. In other words, to calculate the waveform of a compensation current I _CMP to cause deliberate supply voltage variation, it may have been prescribed to control patterns S _{PTN_CMP} as its compensation current waveform is obtained. In this case, an arbitrary power supply environment can be emulated according to the control pattern _{SPTN_CMP} .

  In the embodiment, the case where the power supply compensation circuit 20 includes the source compensation circuit 20a and the sink compensation circuit 20b has been described. However, the present invention is not limited to this, and only one of the configurations may be employed.

If the source compensation circuit 20a provided only may generate a constant current I _DC to the source compensation circuit 20a. When the power supply current I _DD is insufficient with respect to the operating current I _OP , the current I _SRC generated by the source compensation circuit 20a may be relatively increased from the steady current I _DC . On the other hand, when the power supply current I _DD is excessive with respect to the operating current I _OP , the current I _SRC generated by the source compensation circuit 20a may be relatively decreased from the steady current I _DC .
When the sink compensation circuit 20b is provided only it may generate a constant current I _DC to the sink compensation circuit 20b. When the power supply current _{I DD} is insufficient relative to the operating current _{I OP} is the current _{I SINK} sink compensation circuit 20b is generated, may be relatively decreased from constant current _{I DC.} Conversely, when the power supply current _{I DD} is excessive relative to the operating current _{I OP} is the current _{I SINK} sink compensation circuit 20b is generated, may be relatively increased from a steady current _{I DC.}
Thus, the current consumption of the entire test device is increased steady current I _DC component therewith in exchange for, only a single switch, the compensation current I _SRC, it is possible to generate I _SINK.

DESCRIPTION OF SYMBOLS 1 ... DUT, 2 ... Test apparatus, PG ... Pattern generator, TG ... Timing generator, FC ... Waveform shaper, 4 ... Interface circuit, DR ... Driver, 10 ... Main power supply, 20 ... Power supply compensation circuit, 20a ... Source Compensation circuit, 20b ... sink compensation circuit, P1 ... power supply terminal, P2 ... ground terminal, P3 ... I / O terminal, SW1 ... source switch, SW2 ... sink switch, 22 ... voltage source, 24a ... source current source, 24b ... sink Current source, 26 ... current D / A converter, M1 ... first transistor, M2 ... second transistor, 100 ... printed circuit board.

Claims (10)

A test apparatus for simultaneously testing a plurality of devices under test each having a power supply terminal and an input / output terminal,
A common main power supply for supplying power to the power supply terminals of the plurality of devices under test;
A switching element controlled in accordance with a control signal; generating a compensation pulse current in a state in which the switching element is turned on; And / or a power compensation circuit that draws the compensation pulse current in a different path from the plurality of devices under test from a power source current flowing from the main power source to the power terminals of the plurality of devices under test, and
A test pattern that describes a test signal to be supplied to each input / output terminal of the plurality of devices under test, and a pattern generator that generates a control pattern that describes the control signal determined according to the test pattern;
Each of the power supply compensation circuits is provided for each of the input / output terminals, and outputs a test signal corresponding to the test pattern to the corresponding input / output terminal, and the control signal corresponding to the control pattern. A driver group including a driver for controlling the switch element;
A test apparatus comprising: The pattern generator generates a common test pattern for the plurality of devices under test;
The pattern generator is configured to control the control pattern according to the number of devices under test so that the compensation pulse current is generated in an amount proportional to the number of devices under operation among the devices under test. The test apparatus according to claim 1, wherein the test apparatus is changed.   The test apparatus according to claim 2, wherein the pattern generator changes a pulse width of a compensation pulse current defined by the control pattern.   The test apparatus according to claim 2, wherein the pattern generator changes an amplitude of a compensation pulse current defined by the control pattern. The pattern generator generates individual test patterns for the plurality of devices under test;
The pattern generator generates a control pattern by combining a plurality of individual control patterns corresponding to the test patterns given to the plurality of devices under test, and outputs the control pattern to a driver that controls the power supply compensation circuit. The test apparatus according to claim 1.   6. The pattern generator adds a pulse width of a compensation pulse current defined by each of the plurality of individual control patterns to define a pulse width of a compensation pulse current defined by the control pattern. The test apparatus described.   The said pattern generator adds the amplitude of the compensation pulse current prescribed | regulated by each of these several individual control patterns, and prescribes | regulates the amplitude of the compensation pulse current which the said control pattern prescribes | regulates. Test equipment. A test apparatus for simultaneously testing a plurality of devices under test each having a power supply terminal and an input / output terminal,
A common main power supply for supplying power to the power supply terminals of the plurality of devices under test;
Each includes a switch element that is provided for each device under test and is controlled according to a control signal, generates a compensation pulse current when the switch element is turned on, and separates the compensation pulse current from the main power source. From the power supply current that is injected from the path to the power supply terminal of the corresponding device under test and / or flows from the main power supply to the power supply terminal of the corresponding device under test, A plurality of power supply compensation circuits,
A test pattern describing a test signal to be supplied to each input / output terminal of the plurality of devices under test, and a control pattern describing a control signal for each of the plurality of power supply compensation circuits determined according to the test pattern. A pattern generator to generate,
A plurality of drivers each provided for each of the input / output terminals and outputting a test signal corresponding to the test pattern to the corresponding input / output terminals, and a corresponding control pattern provided for each of the power supply compensation circuits. A driver group including a plurality of drivers that control the switch elements of the corresponding power supply compensation circuit by the control signal according to
A test apparatus comprising: The pattern generator generates a common test pattern for the plurality of devices under test;
The said pattern generator outputs the said control pattern to the driver which controls the said power supply compensation circuit corresponding to the to-be-tested device under operation among these several to-be-tested devices. Testing equipment. The pattern generator generates individual test patterns for the plurality of devices under test;
The pattern generator outputs an individual control pattern defined for a test pattern for each device under test to a driver that controls the power supply compensation circuit corresponding to the device under test. 8. The test apparatus according to 8.

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