JP2012098180A - Test device and power supply device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a circuit that can generate a compensation current having a stable amplitude and switching at high speed.SOLUTION: A sink compensation circuit 12c generates a compensation pulse current I, and draws the compensation pulse current into a path different from DUT1. A current D/A converter 14 generates a reference current Iaccording to a digital setting signal D. A first transistor M1 and second transistor M2 are MOSFETs and constitute a current mirror circuit. A switching element SW1 is arranged between a gate of the first transistor M1 and a gate of the second transistor M2.

Description

  The present invention relates to a power supply stabilization technique.

  When testing a semiconductor integrated circuit (hereinafter referred to as DUT) such as a CPU (Central Processing Unit), DSP (Digital Signal Processor), and memory using CMOS (Complementary Metal Oxide Semiconductor) technology, flip-flops and latches in the DUT are When the clock is supplied, a current flows, and when the clock is stopped, the circuit becomes static and the current decreases. Therefore, the total operating current (load current) of the DUT varies from moment to moment depending on the contents of the test.

  A power supply circuit that supplies power to the DUT is configured using, for example, a regulator, and can ideally supply constant power regardless of the load current. However, an actual power supply circuit has an output impedance that cannot be ignored, and an impedance component that cannot be ignored exists between the power supply circuit and the DUT, so that the power supply voltage fluctuates due to load fluctuations.

  The fluctuation of the power supply voltage seriously affects the test margin of the DUT. In addition, fluctuations in the power supply voltage affect the operation of other circuit blocks in the test apparatus, such as a pattern generator that generates a pattern to be supplied to the DUT, and a timing generator that controls the pattern transition timing. Deteriorating accuracy.

  In the technique described in Patent Document 2, in addition to a main power supply that supplies a power supply voltage to a device under test, a compensation circuit including a switch that is controlled to be turned on and off by an output of a driver is provided. Then, a compensation control pattern for the switch element is defined in association with the test pattern so as to cancel the fluctuation of the power supply voltage that may occur according to the test pattern supplied to the device under test. During the actual test, the power supply voltage can be kept constant by switching the switch of the compensation circuit according to the control pattern while supplying the test pattern to the device under test.

JP 2007-205813 A International Publication No. 10 / 029709A1 Pamphlet

In order to correct the power supply voltage by the compensation circuit or to accurately emulate the power supply environment, the stability of the amplitude of the compensation current supplied by the compensation circuit is required.
Here, a case where a large current of about several A is required for the compensation pulse current is also assumed. When a switch element is provided on the compensation pulse current path, it is necessary to increase the size of the switch element. Therefore, the switching speed is limited by the capacitance of the switch element, and there is a possibility that a pulse current having a desired amplitude cannot be generated.

  An aspect of the present invention has been made in such a situation, and one of exemplary purposes of the aspect is to provide a circuit having a stable amplitude and capable of generating a compensation current that switches at high speed. is there.

  One embodiment of the present invention relates to a power supply apparatus that supplies a power supply voltage to a semiconductor device. The power supply apparatus includes a main power supply that supplies power to the power supply terminal of the semiconductor device and a switch element that is controlled according to a control signal. The power supply apparatus generates a compensation pulse current when the switch element is turned on, A power supply compensation circuit that injects a compensation pulse current into a separate path from the semiconductor device from a power supply current that flows from the main power supply to the semiconductor device through a path different from the power supply, or in accordance with the operating state of the semiconductor device. And a control unit for controlling the switch element. The power compensation circuit includes a current D / A converter that generates a current corresponding to a digital setting signal, and a first transistor of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) provided on the output current path of the current D / A converter. A second transistor that is connected to the first transistor so as to form a current mirror circuit and generates a current proportional to an output current of the current D / A converter, a gate of the first transistor, and a gate of the second transistor And a switch element provided therebetween.

  According to this aspect, the current D / A converter constantly generates a stable current, and the current mirror circuit amplifies the output current of the current D / A converter, so that the amplitude of the compensation pulse current can be stabilized. Since the current mirror circuit is switched instead of switching the path of the compensation pulse current, it can be operated at a high frequency.

The drain of the first transistor may be connected to a terminal on the gate side of the first transistor of the switch element.
In this case, even when the switch element is turned off, the bias state of the first transistor is maintained and the output current of the current D / A converter is not cut off, so that high-speed switching is possible.

The drain of the first transistor may be connected to the terminal on the gate side of the second transistor of the switch element.
In this case, since the path of the output current of the current D / A converter is interrupted, the current consumption when the switch element is in the OFF state can be reduced.

  Yet another embodiment of the present invention is also a power supply device. This power supply apparatus includes a main power supply that supplies power to a power supply terminal of a semiconductor device and a switch element that is controlled in accordance with a control signal. The power supply apparatus generates a compensation pulse current when the switch element is turned on, and generates the compensation pulse current. A power supply compensation circuit that injects a compensation pulse current into a different path from the semiconductor device from the power supply current that flows from the main power supply to the power supply terminal or flows from the main power supply to the semiconductor device, depending on the operating state of the semiconductor device And a control unit for controlling the switch element. The power compensation circuit includes a current D / A converter that generates a current corresponding to a digital setting signal, and a first transistor of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) provided on the output current path of the current D / A converter. A second transistor that is connected to the first transistor so as to form a current mirror circuit, and generates a current proportional to the output current of the current D / A converter, and a gate that is connected in common to the first and second transistors And a switch element provided between the fixed voltage terminals.

  According to this aspect, the current D / A converter constantly generates a stable current, and the current mirror circuit amplifies the output current of the current D / A converter, so that the amplitude of the compensation pulse current can be stabilized. Further, since the current mirror circuit is switched instead of switching the current D / A converter, a compensation pulse current having a high frequency or a small duty ratio can be generated.

  Note that any combination of the above-described constituent elements and the constituent elements and expressions of the present invention replaced with each other between methods and apparatuses are also effective as an aspect of the present invention.

  According to an aspect of the present invention, a current that switches at high speed with a stable amplitude can be generated.

It is a circuit diagram which shows the structure of the test apparatus which concerns on embodiment. 2A to 2C are circuit diagrams illustrating configuration examples of the sink compensation circuit. It is a circuit diagram which shows the structure of the sink compensation circuit which concerns on a comparison technique. It is a circuit diagram which shows the structural example of a source compensation circuit. It is a flowchart which shows an example of the method of calculating a control pattern. It is a wave form diagram which shows an example of an operating current, a power supply current, a source compensation current, and a source pulse current.

  The present invention will be described below based on preferred embodiments with reference to the drawings. The same or equivalent components, members, and processes shown in the drawings are denoted by the same reference numerals, and repeated descriptions are omitted as appropriate. The embodiments do not limit the invention but are exemplifications, and all features and combinations thereof described in the embodiments are not necessarily essential to the invention.

  In this specification, “the state in which the member A is connected to the member B” means that the member A and the member B are physically directly connected, or the member A and the member B are electrically connected. The case where it is indirectly connected through another member that does not affect the state is also included. Similarly, “the state in which the member C is provided between the member A and the member B” refers to the case where the member A and the member C or the member B and the member C are directly connected, as well as an electrical condition. It includes the case of being indirectly connected through another member that does not affect the connection state.

  FIG. 1 is a circuit diagram showing a configuration of a test apparatus 2 according to the embodiment. FIG. 1 shows a semiconductor device (hereinafter referred to as DUT) 1 to be tested in addition to a test apparatus 2.

The DUT 1 includes a plurality of pins, at least one of which is a power supply terminal P1 for receiving the power supply voltage V _DD , and at least one other is a ground terminal P2. A plurality of input / output (I / O) terminals P3 are provided to receive data from the outside or to output data to the outside, and at the time of testing, test signals (tests) output from the test apparatus 2 Pattern) S _TEST is received or data corresponding to the test signal S _TEST is output to the test apparatus 2. FIG. 1 shows a configuration for giving a test signal to the DUT 1 among the configurations of the test apparatus 2, and a configuration for evaluating a signal from the DUT 1 is omitted.

  The test apparatus 2 includes a main power supply 10, a pattern generator PG, a plurality of timing generators TG and a waveform shaper FC, a plurality of drivers DR, and a power supply compensation circuit 12.

  The test apparatus 2 includes a plurality of n channels CH1 to CHn, some of which (CH1 to CH4) are allocated to the plurality of I / O terminals P3 of the DUT1. Although FIG. 1 shows a case where n = 6, the actual number of channels of the test apparatus 2 is on the order of hundreds to thousands.

The main power supply 10 generates a power supply voltage V _DD to be supplied to the power supply terminal P1 of the DUT 1. For example, the main power supply 10 is composed of a linear regulator, a switching regulator, and the like, and feedback-controls the power supply voltage V _DD supplied to the power supply terminal P1 so as to coincide with the target value. The capacitor Cs is provided to smooth the power supply voltage V _DD . The main power supply 10 generates a power supply voltage for other blocks inside the test apparatus 2 in addition to a power supply voltage for the DUT 1. The output current from the main power supply 10 to the power terminal P1 of DUT1, referred to as the power supply current _{I DD.}

The main power supply 10 are the voltage and current source having a response speed of the finite, there is a case where the load current, i.e. can not follow the abrupt change in the operating current I _OP of DUT1. For example, when the operating current I _OP changes stepwise, the power supply voltage V _DD may overshoot or undershoot, or be accompanied by subsequent ringing. Variations in the power supply voltage V _DD prevent accurate testing of DUT 1. This is because when an error is detected in DUT 1, it cannot be distinguished whether it is due to defective manufacturing of DUT 1 or due to fluctuations in power supply voltage V _DD .

The power supply compensation circuit 12 is provided to compensate for the response speed of the main power supply 10. The designer of the DUT 1 can estimate the time transition such as the operation rate of the internal circuit of the DUT 1 in a state where a certain known test signal S _TEST (test pattern S _PTN ) is supplied, so the operating current I _{OP of the} DUT 1 The time waveform can be accurately predicted. Here, the prediction includes calculation using computer simulation, actual measurement for devices having the same configuration, and the method is not particularly limited.

On the other hand, if the response speed (gain, feedback band) of the main power source 10 is known, the power source current I _DD generated by the main power source 10 in response to the predicted operating current I _OP can also be predicted. Then, the power supply voltage V _DD can be stabilized by compensating the predicted difference between the operating current I _OP and the power supply current I _DD by the power supply compensation circuit 12.
A differential or integral relationship is established between the power supply voltage V _DD ′ and the power supply current I _DD . Specifically, depending on whether the impedance of the main power supply 10 and the path from the main power supply 10 to the power supply terminal P1 is dominant, capacitive, inductive, or resistive, the relationship between voltage and current differentiation and integration Is determined.

The power supply compensation circuit 12 includes a source compensation circuit 12b and a sink compensation circuit 12c. The source compensation circuit 12b can be switched on and off according to the control signal _SCNT1 . When the source compensation circuit 12b is turned on in response to the control signal _SCNT1 , a compensation pulse current (also referred to as a source pulse current) I _SRC is generated. The power supply compensation circuit 12 injects the source pulse current I _SRC into the power supply terminal P1 from a different path from the main power supply 10.

Similarly, the sink compensation circuit 12c can be switched on and off in accordance with the control signal _SCNT2 . When sync compensation circuit 12c is turned on in response to the control signal _{S CNT2,} the compensation pulse current _{I SINK} (also referred to as a sink pulse current) is generated. Power compensation circuit 12 draws from the power supply current _{I DD} flowing into the power source terminal P1, the sync pulse current _{I SINK,} a separate path from the DUT1.

2A to 2C are circuit diagrams illustrating a configuration example of the sink compensation circuit 12c.
Each of the sink compensation circuits 12c of FIGS. 2A to 2C includes a current D / A converter 14, a first transistor M1, a second transistor M2, and a switch element SW1.

The current D / A converter 14 generates a reference current I _REF corresponding to the digital setting signal D _SET . The first transistor M1 and the second transistor M2 form a current mirror circuit, and generates a sync pulse current _{I SINK} of the reference current _{I REF} by a predetermined coefficient (mirror ratio K) times.

Specifically, the first transistor M1 is an N-channel MOSFET and is provided on the path of the reference current I _REF . The second transistor M2 is also an N-channel MOSFET, and its gate is connected in common with the gate and source of the first transistor M1.

2A and 2B, the switch element SW1 is provided between the gate of the first transistor M1 and the gate of the second transistor M2. For example, the switch element SW1 may be configured with a transfer gate as shown in FIG. 2A, may be configured with only an N-channel MOSFET, or may be configured with only a P-channel MOSFET. The on / off state of the switch element SW1 is switched according to the control signal _SCNT2 .

  In FIG. 2A, the drain N2 of the first transistor M1 is connected to the terminal N1 on the gate side of the first transistor M1 of the switch element SW1.

The switch element SW1 is turned on while the control signal _SCNT2 is at a high level. Then from the output terminal P4 of the sink compensation circuit 12c, sink pulse current _{I SINK} proportional to the reference current _{I REF} is crowded pulling. Control signal _{S CNT2} period of low level, the switch element SW1 is turned off, since the current mirror circuit does not operate, so the sink pulse current _{I SINK} is zero.

According to the sink compensation circuit 12c in FIG. 2 (a), it can generate a sync pulse current _{I SINK} for switching in response to the control signal _{S CNT2.} The advantage of the sink compensation circuit 12c becomes clear by comparison with the circuit according to the comparison technique of FIG.
The sink compensation circuit according to the comparison technique of FIG. 3 includes a switch element SW2 provided between the power supply terminal P1 and the ground terminal. If the power supply voltage _{V DD} is constant, in a state where the switch element SW2 is turned on, the amplitude of sink current _{I SINK} is
I _SINK = V _DD / R _ON
Given in. R _ON is the ON resistance of the switch SW2.

Wherein the amplitude of the sync pulse current I _SINK may several A are required. As a result, the size of the switch element SW2 increases, and the gate capacitance also increases. Due to this gate capacitance, the switching response speed of the switch element SW2 may decrease, and a desired current may not be generated.
Also, or variations in the on-resistance _{R ON} of the switch element SW2, the amplitude of the control signal _{S CNT2} varies, variations on resistance _{R ON,} the amplitude of the sync pulse current _{I SINK} is likely to fluctuate.

In contrast, according to the sink compensation circuit 12c in FIG. 2 (a), it is possible to increase the stability of the amplitude of the sync pulse current _{I SINK.} Further, since the driver DR is driven not by a switch through which a large current flows but by a switch provided at the gate of the current mirror circuit, high-speed switching is possible.

In the sink compensation circuit 12c of FIG. 2A, the reference current _IREF continues to flow through the first transistor M1 even when the switch element SW1 is in the OFF state, and the bias state of the first transistor M1 is maintained. Therefore, there is an advantage that the switching response speed of the sink compensation circuit 12c with respect to switching of the switch element SW1 is high.

Reference is made to FIG. In FIG. 2B, the position of the switch element SW1 is different from that in FIG. In FIG. 2B, the drain N2 of the first transistor M1 is connected to the terminal N3 on the gate side of the second transistor M2 of the switch element SW1.
With this configuration, similarly to the arrangement in FIG. 2 (a), have a stable amplitude, it can generate a sync pulse current I _SINK switching speed.
In FIG. 2B, the reference current _IREF is cut off when the switch element SW1 is off. Therefore, there is an advantage that the current consumption of the circuit can be reduced.

In FIG. 2C, the switch element SW1 is provided between a gate N4 commonly connected to the first transistor M1 and the second transistor M2 and a fixed voltage terminal such as a ground terminal. If the switch element SW1 is turned on while the control signal _SCNT2 # (# indicates logic inversion) is at a high level, the gate voltages of the first transistor M1 and the second transistor M2 become the ground voltage, so that the current mirror circuit is turned off. and sink pulse current _{I sINK} is interrupted. When the control signal _{S CNT2} # is low, the switch element SW1 is turned off, the current mirror circuit is turned on, flows sink pulse current _{I SINK.}

According to the configuration of FIG. 2 (c), similarly to FIG. 2 (a), (b) , have a stable amplitude, can generate a sync pulse current _{I SINK} switching speed.
Note that the configuration shown in FIG. 2C may be combined with the configuration shown in FIG.

  Next, a specific configuration example of the source compensation circuit 12b will be described. The source compensation circuit 12b can be configured by inverting the sink compensation circuit 12c upside down. FIG. 4 is a circuit diagram showing a configuration example of the source compensation circuit 12b. The first transistor M1 and the second transistor M2 may be composed of P-channel MOSFETs. The configuration of FIG. 4 corresponds to FIG. A person skilled in the art understands that the source compensation circuit 12b corresponding to FIGS. 2B and 2C can be configured.

Returning to FIG. Between the operating current I _OP flowing into the power terminal P 1 of the DUT 1, the power source current I _DD output from the main power source 10, and the compensation current I _CMP output from the power source compensation circuit 12, from the current conservation law, (2) holds.
I _OP = I _DD + I _CMP (1)
_{I CMP = I SRC -I SINK ...} (2)
That is, the positive component of the compensation current _{I CMP} is supplied from the source compensation circuit 12b as a source pulse current _{I SRC,} negative components of the compensation current _{I CMP} is supplied from the sink compensation circuit 12c as a sink pulse current _{I SINK} .

Of the driver _DR 1 _{~DR 6,} the driver DR ₆ is assigned to the source compensation circuit 12b, the driver DR ₅ are assigned to the sink compensation circuit 12c. The other at least one driver DR _{1 to} DR ₄ is assigned to at least one I / O terminal P 3 of the DUT 1. The pattern generator PG, the drivers DR ₅ and DR ₆ , and the interface circuits 4 ₅ and 4 ₆ can be understood as control circuits that control the power supply compensation circuit 12.

The waveform shaper FC and the timing generator TG are collectively referred to as an interface circuit 4. The plurality of 4 ₁ to 4 ₆ are provided for each of the channels CH _{1 to} CH ₆ , in other words, for each of the drivers DR ₁ to DR ₆ . The i-th (1 ≦ i ≦ 6) interface circuit 4 _{i shapes the} input pattern signal S _PTNi into a signal format suitable for the driver DR, and outputs it to the corresponding driver DR _i .

The pattern generator PG generates a pattern signal _SPTN for the interface circuits 4 ₁ to 4 ₆ based on the test program. Specifically, for the drivers DR _{1 to} DR ₄ assigned to the I / O terminal P3 of the DUT 1, the pattern generator PG describes a test pattern S _PTNi that describes the test signal S _TESTi that each driver DR _i should generate. Is output to the interface circuit 4 _i corresponding to the driver DR _i . The test pattern S _PTNi includes data indicating the level in each cycle (unit interval) of the test signal S _TESTi and data describing the timing at which the signal level transitions.

The pattern generator PG generates the control patterns _{S PTN_CMP} for compensation which is determined according to the required compensation current _{I CMP.} Control pattern _{S PTN_CMP} includes a source compensation circuit 12b describes the control signal _{S CNT1} driver DR ₆ is to be generated which is assigned to the control pattern _{S PTN_CMP1,} sink compensation circuit 12c to the assigned driver DR ₅ is controlled to be generated A control pattern S _{PTN_CMP2} describing the signal S _CNT2 is included. Each of the control patterns S _{PTN_CMP1} and S _{PTN_CMP2} includes data designating on / off states of the source compensation circuit 12b and the sink compensation circuit 12c in each cycle, and data describing timing for switching on / off.

The pattern generator PG generates control patterns S _{PTN_CMP1} and S _{PTN_CMP2} that can compensate for the test patterns S _{PTN1 to} S _PTN4 , that is, according to fluctuations in the operating current of the DUT 1, and corresponding interface circuits 4 _6. 4 and ₅ are output.

As described above, if the test patterns S _{PTN1 to} S _PTN4 are known, the time waveform of the operating current I _OP of the DUT 1 can be predicted, and the compensation current I _CMP to be generated in order to keep the power supply voltage V _DD constant, that is, The time waveforms of I _SRC and I _SINK can be calculated.
If the predicted operating current I _OP is larger than the power supply current I _DD , the power supply compensation circuit 12 generates a source compensation current I _SRC to compensate for the insufficient current. Since the current waveform required for the source compensation current I _SRC can be predicted, the source compensation circuit 12b is controlled so that it can be appropriately obtained. For example, the source compensation circuit 12b may be controlled by pulse width modulation. Alternatively, pulse amplitude modulation, ΔΣ modulation, pulse density modulation, pulse frequency modulation, or the like may be used.

FIG. 5 is a flowchart illustrating an example of a method for calculating a control pattern. Based on the test pattern and circuit information input to the DUT 1, the operating current I _{OP of the} DUT 1 is estimated (S100). Further, when the DUT 1 is connected to the main power source 10 as a load, when the event occurs in the DUT 1, the power source current I _DD output from the main power source 10 is calculated (S102). Then, when it is desired to achieve an ideal power is the difference between the estimated operating current _{I OP} and the power supply current _{I DD,} the compensation current _{I CMP} to be generated by the power supply compensation circuit 12 (S104).

Then, by applying ΔΣ modulation, PWM (pulse width modulation), PDM (pulse density modulation), PAM (pulse amplitude modulation), PFM (pulse frequency modulation), etc. to the waveform of the compensation current _ICMP to be generated, a bit is obtained. A stream control pattern _{SPTN_CMP} is generated (S106). For example, the compensation current _ICMP may be sampled every test cycle, and the sampled compensation current _ICMP may be pulse-modulated.

FIG. 6 is a waveform diagram showing an example of the operating current I _OP , the power supply current I _DD , the source compensation current I _SRC and the source pulse current I _SRC . It is assumed that the operating current I _{OP of the} DUT 1 to which a certain test signal S _TEST is supplied increases stepwise. In response to this, the power supply current I _DD is supplied from the main power supply 10, but it does not become an ideal step waveform due to the limitation of the response speed, and the current to be supplied to the DUT 1 is insufficient. As a result, unless the compensation current I _SRC is supplied, the power supply voltage V _DD decreases as shown by a broken line.

The power supply compensation circuit 12 generates a source compensation current _ICMP corresponding to the difference between the operating current _IOP and the power supply current _IDD . The source compensation current I _CMP is given by the source pulse current I _SRC generated according to the control signal S _CNT1 . The source compensation current _ICMP needs to be the maximum amount immediately after the change of the operating current _IOP , and then needs to be gradually reduced. Thus, for example, the necessary source compensation current _ICMP can be generated by reducing the on-time (duty ratio) of the source compensation circuit 12b with time using PWM (pulse width modulation).

When all the channels of the test apparatus 2 operate synchronously according to the test rate, the cycle of the control signal _{SCNT1 is} the cycle of data supplied to the DUT 1 (unit interval), an integral multiple thereof, or a fraction of an integer. Equivalent to. For example, in the unit interval is 4ns system control if the period of the signal _{S CNT1} is 4ns, each pulse of the ON period _{T ON} contained in the control signal _{S CNT1} is, can be adjusted between 0～4Ns. The response speed of the main power source 10 is on the order of a few hundred ns~ number .mu.s, the waveform of the compensation current I _CMP can be controlled by hundreds of pulses contained in the control signal S _CNT1. A method of deriving the control signal _SCNT1 necessary for generating the source compensation current I _{SRC from} the waveform will be described later.

If the operating current _{I OP} to the opposite is smaller than the power supply current _{I DD,} the power supply compensation circuit 12 as the sink compensation current _{I CMP} is obtained by generating a sync pulse current _{I SINK,} pull the excessive current.

By providing the power supply compensation circuit 12, it is possible to compensate for the lack of response speed of the main power supply 10, and to keep the power supply voltage V _DD constant as shown by the solid line in FIG. As described above, since the power supply compensation circuit 12 can generate a pulse current having a stable amplitude, the power supply voltage can be compensated with high accuracy.

The current flowing through the internal elements constituting the DUT 1, that is, the operating current I _OP fluctuates due to process variations. That is, the waveform of the operating current of the DUT 1 to which a certain test pattern is supplied increases or decreases due to process variations. Therefore, prior to DUT1 testing process, by adjusting the amplitude of the compensation pulse current calibrate process, even as the operating current I _OP of DUT1 is varied by the process variations, to keep the power environment constant it can. This calibration can be realized by changing the value of the digital setting value D _SET for the current D / A converter 14.

  Although the present invention has been described based on the embodiments, the embodiments merely show the principle and application of the present invention, and the embodiments depart from the idea of the present invention defined in the claims. Many modifications and changes in the arrangement are allowed within the range not to be performed.

In the embodiment, a case has been described in which the compensation current _ICMP realizes an ideal power supply environment in which the fluctuation of the power supply voltage is zero, that is, the output impedance is zero. However, the present invention is not limited thereto. In other words, to calculate the waveform of a compensation current I _CMP to cause deliberate supply voltage variation, it may have been prescribed to control patterns S _{PTN_CMP} as its compensation current waveform is obtained. In this case, an arbitrary power supply environment can be emulated according to the control pattern _{SPTN_CMP} .

  In the embodiment, the case where the power supply compensation circuit 12 includes the source compensation circuit 12b and the sink compensation circuit 12c has been described. However, the present invention is not limited to this, and only one of the configurations may be employed.

When providing only source compensation circuit 12b, may be generated a steady current I _DC to the source compensation circuit 12b. When the power supply current I _DD is insufficient with respect to the operating current I _OP , the current I _SRC generated by the source compensation circuit 12b may be relatively increased from the steady current I _DC . On the contrary, when the power supply current I _DD is excessive with respect to the operating current I _OP , the current I _SRC generated by the source compensation circuit 12b may be relatively decreased from the steady current I _DC .
When the sink compensation circuit 12c provided only may generate a constant current I _DC to the sink compensation circuit 12c. When the power supply current _{I DD} is insufficient relative to the operating current _{I OP} is the current _{I SINK} sink compensation circuit 12c occurs, may be relatively decreased from constant current _{I DC.} Conversely, when the power supply current _{I DD} is excessive relative to the operating current _{I OP} is the current _{I SINK} sink compensation circuit 12c occurs, may be relatively increased from a steady current _{I DC.}
Thus, the current consumption of the entire test device is increased steady current I _DC component therewith in exchange for, only a single switch, the compensation current I _SRC, it is possible to generate I _SINK.

DESCRIPTION OF SYMBOLS 1 ... DUT, 2 ... Test apparatus, PG ... Pattern generator, TG ... Timing generator, FC ... Waveform shaper, 4 ... Interface circuit, DR ... Driver, 10 ... Main power supply, 12 ... Power supply compensation circuit, 12b ... Source Compensation circuit, 12c ... sink compensation circuit, P1 ... power supply terminal, P2 ... ground terminal, P3 ... I / O terminal, M1 ... first transistor, M2 ... second transistor, SW1 ... switch element, 14 ... current D / A converter .

Claims (8)

A power supply device for supplying a power supply voltage to a semiconductor device,
A main power supply for supplying power to the power supply terminal of the semiconductor device;
Including a switching element controlled in accordance with a control signal, generating a compensation pulse current in a state in which the switching element is turned on, and injecting the compensation pulse current to the power supply terminal from a path different from the main power supply, or A power supply compensation circuit that draws the compensation pulse current in a path different from the semiconductor device from a power supply current flowing from a main power supply to the semiconductor device;
A control unit that controls the switch element in accordance with an operating state of the semiconductor device;
With
The power supply compensation circuit is:
A current D / A converter that generates a current corresponding to the digital setting signal;
A first transistor of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) provided on an output current path of the current D / A converter;
A second transistor connected to form a current mirror circuit with the first transistor and generating a current proportional to an output current of the current D / A converter;
The switch element provided between the gate of the first transistor and the gate of the second transistor;
A power supply apparatus comprising:   2. The power supply device according to claim 1, wherein a drain of the first transistor is connected to a terminal of the switch element on a gate side of the first transistor.   2. The power supply device according to claim 1, wherein a drain of the first transistor is connected to a terminal of the switch element on a gate side of the second transistor. A test apparatus for testing a device under test,
A main power supply for supplying power to the power supply terminal of the device under test;
Including a switching element controlled in accordance with a control signal, generating a compensation pulse current in a state in which the switching element is turned on, and injecting the compensation pulse current to the power supply terminal from a path different from the main power supply, or A power supply compensation circuit that draws the compensation pulse current from a power supply current flowing from a main power supply to the device under test into a path different from the device under test
A plurality of drivers, one of which is assigned to the switch element and at least one of which is assigned to at least one input / output terminal of the device under test;
A plurality of interface circuits each provided for each of the drivers, and each of the plurality of interface circuits for shaping and outputting the input pattern signal to a corresponding driver;
A test pattern describing a test signal to be output by the driver assigned to the input / output terminal of the device under test is output to the interface circuit corresponding to the driver, and determined according to the test pattern. A pattern generator for outputting the control pattern to the interface circuit corresponding to the driver assigned to the switch element;
With
The power supply compensation circuit is:
A current D / A converter that generates a current corresponding to a digital setting signal;
A first transistor of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) provided on an output current path of the current D / A converter;
A second transistor connected to form a current mirror circuit with the first transistor and generating a current proportional to an output current of the current D / A converter;
The switch element provided between the gate of the first transistor and the gate of the second transistor;
A test apparatus comprising:   The test apparatus according to claim 4, wherein a drain of the first transistor is connected to a terminal of the switch element on a gate side of the first transistor.   The test apparatus according to claim 4, wherein a drain of the first transistor is connected to a terminal of the switch element on a gate side of the second transistor. A power supply device for supplying a power supply voltage to a semiconductor device,
A main power supply for supplying power to the power supply terminal of the semiconductor device;
Including a switching element controlled in accordance with a control signal, generating a compensation pulse current in a state in which the switching element is turned on, and injecting the compensation pulse current to the power supply terminal from a path different from the main power supply, or A power supply compensation circuit that draws the compensation pulse current in a path different from the semiconductor device from a power supply current flowing from a main power supply to the semiconductor device;
A control unit that controls the switch element in accordance with an operating state of the semiconductor device;
With
The power supply compensation circuit is:
A current D / A converter that generates a current corresponding to the digital setting signal;
A first transistor of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) provided on an output current path of the current D / A converter;
A second transistor connected to form a current mirror circuit with the first transistor and generating a current proportional to an output current of the current D / A converter;
The switch element provided between a commonly connected gate of the first and second transistors and a fixed voltage terminal;
A power supply apparatus comprising: A test apparatus for testing a device under test,
A main power supply for supplying power to the power supply terminal of the device under test;
Including a switching element controlled in accordance with a control signal, generating a compensation pulse current in a state in which the switching element is turned on, and injecting the compensation pulse current to the power supply terminal from a path different from the main power supply, or A power supply compensation circuit that draws the compensation pulse current from a power supply current flowing from a main power supply to the device under test into a path different from the device under test
A plurality of drivers, one of which is assigned to the switch element and at least one of which is assigned to at least one input / output terminal of the device under test;
A plurality of interface circuits each provided for each of the drivers, and each of the plurality of interface circuits for shaping and outputting the input pattern signal to a corresponding driver;
A test pattern describing a test signal to be output by the driver assigned to the input / output terminal of the device under test is output to the interface circuit corresponding to the driver, and determined according to the test pattern. A pattern generator for outputting the control pattern to the interface circuit corresponding to the driver assigned to the switch element;
With
The power supply compensation circuit is:
A current D / A converter that generates a current corresponding to the digital setting signal;
A first transistor of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) provided on an output current path of the current D / A converter;
A second transistor connected to form a current mirror circuit with the first transistor and generating a current proportional to an output current of the current D / A converter;
The switch element provided between a commonly connected gate of the first and second transistors and a fixed voltage terminal;
A test apparatus comprising:

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