[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

JP2012069734A - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法 Download PDF

Info

Publication number
JP2012069734A
JP2012069734A JP2010213216A JP2010213216A JP2012069734A JP 2012069734 A JP2012069734 A JP 2012069734A JP 2010213216 A JP2010213216 A JP 2010213216A JP 2010213216 A JP2010213216 A JP 2010213216A JP 2012069734 A JP2012069734 A JP 2012069734A
Authority
JP
Japan
Prior art keywords
layer
semiconductor device
resin layer
manufacturing
support substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2010213216A
Other languages
English (en)
Inventor
Soichi Honma
荘一 本間
Taku Kamoto
拓 加本
Yusuke Takano
勇佑 高野
Masayuki Miura
正幸 三浦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP2010213216A priority Critical patent/JP2012069734A/ja
Priority to TW100131342A priority patent/TWI446465B/zh
Priority to US13/235,417 priority patent/US20120077313A1/en
Publication of JP2012069734A publication Critical patent/JP2012069734A/ja
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13025—Disposition the bump connector being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13109—Indium [In] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13113—Bismuth [Bi] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13116—Lead [Pb] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13139—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/13164—Palladium [Pd] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/13169—Platinum [Pt] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/16146—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a via connection in the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
    • H01L2224/21—Structure, shape, material or disposition of high density interconnect preforms of an individual HDI interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
    • H01L2224/21—Structure, shape, material or disposition of high density interconnect preforms of an individual HDI interconnect
    • H01L2224/215—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48464—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area also being a ball bond, i.e. ball-to-ball
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48475—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball
    • H01L2224/48476—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area
    • H01L2224/48477—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area being a pre-ball (i.e. a ball formed by capillary bonding)
    • H01L2224/48484—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area being a pre-ball (i.e. a ball formed by capillary bonding) being a plurality of pre-balls disposed side-to-side
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
    • H01L2224/486—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48617—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950 °C
    • H01L2224/48624—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73259—Bump and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/81005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81009—Pre-treatment of the bump connector or the bonding area
    • H01L2224/8101—Cleaning the bump connector, e.g. oxide removal step, desmearing
    • H01L2224/81011—Chemical cleaning, e.g. etching, flux
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81009—Pre-treatment of the bump connector or the bonding area
    • H01L2224/8101—Cleaning the bump connector, e.g. oxide removal step, desmearing
    • H01L2224/81013—Plasma cleaning
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812—Applying energy for connecting
    • H01L2224/8121—Applying energy for connecting using a reflow oven
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/81815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81909—Post-treatment of the bump connector or bonding area
    • H01L2224/8191—Cleaning, e.g. oxide removal step, desmearing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/83005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06506—Wire or wire-like electrical connections between devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06565—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices having the same size and there being no auxiliary carrier between the devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01028—Nickel [Ni]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01075—Rhenium [Re]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/15321—Connection portion the connection portion being formed on the die mounting surface of the substrate being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Laser Beam Processing (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

【課題】配線層の形成時や支持基板の剥離時に、配線層のずれや基板の割れといった不具合が発生しにくい半導体装置の製造方法を提供する。
【解決手段】半導体装置の製造方法は、光の透過が抑制された第１の樹脂層３を支持基板２上に形成し、第１の樹脂層上に熱可塑性樹脂からなる第２の樹脂層４を形成する。第２の樹脂層上に絶縁層５および配線層８を形成し、配線層上に第１の半導体チップ１０を実装する。第１の樹脂層にレーザ光を照射して支持基板を剥離し、第２の樹脂層を除去することを特徴とする。
【選択図】図１３

Description

本発明の実施形態は半導体装置の製造方法に関する。
半導体装置には、単一の基板の両面に複数の半導体チップが実装される、いわゆる両面実装型の半導体装置や、一方の面に半導体チップが実装され、他方の面に端子が形成された片面実装型の半導体装置がある。上記のような半導体装置において、薄膜基板を用いた半導体装置の製造では、所定の支持基板上に基板や配線層が設けられる。そして、支持基板上の基板の一方の面に半導体チップが実装され、その後、支持基板が基板から剥離される。
特開２０００−３２３６１３号公報 特開平０５−２５９６３９号公報 特開２００４−２００６６８号公報
このような半導体装置では、配線層の形成時や支持基板の剥離時に、配線層のずれや基板の割れといった不具合が発生しにくい製造方法が望まれている。
本発明の実施の形態は、配線層の形成時や支持基板の剥離時に、配線層のずれや基板の割れといった不具合が発生しにくい半導体装置の製造方法を提供することを目的とする。
実施の形態の半導体装置の製造方法は、光の透過が抑制された第１の樹脂層を支持基板上に形成し、第１の樹脂層上に熱可塑性樹脂からなる第２の樹脂層を形成する。第２の樹脂層上に絶縁層および配線層を形成し、配線層上に第１の半導体チップを実装する。第１の樹脂層にレーザ光を照射して支持基板を剥離し、第２の樹脂層を除去することを特徴とする。
第１の実施の形態にかかる半導体装置の製造方法を説明する図である。 第１の実施の形態にかかる半導体装置の製造方法を説明する図である。 第１の実施の形態にかかる半導体装置の製造方法を説明する図である。 第１の実施の形態にかかる半導体装置の製造方法を説明する図である。 第１の実施の形態にかかる半導体装置の製造方法を説明する図である。 第１の実施の形態にかかる半導体装置の製造方法を説明する図である。 第１の実施の形態にかかる半導体装置の製造方法を説明する図である。 第１の実施の形態にかかる半導体装置の製造方法を説明する図である。 第１の実施の形態にかかる半導体装置の製造方法を説明する図である。 第１の実施の形態にかかる半導体装置の製造方法を説明する図である。 第１の実施の形態にかかる半導体装置の製造方法を説明する図である。 第１の実施の形態にかかる半導体装置の製造方法を説明する図である。 第１の実施の形態にかかる半導体装置の製造方法を説明する図である。 第１の実施の形態にかかる半導体装置の製造方法を説明する図である。 第１の実施の形態にかかる半導体装置の製造方法を説明する図である。 第１の実施の形態にかかる半導体装置の製造方法を説明する図である。 第１の実施の形態にかかる半導体装置の製造方法を説明する図である。 第１の実施の形態にかかる半導体装置の製造方法を説明する図である。 第１の実施の形態にかかる半導体装置の製造方法を説明する図である。 第１の実施の形態にかかる半導体装置の製造方法を説明するフローチャートである。 第２の実施の形態にかかる半導体装置の製造方法を説明する図である。 第２の実施の形態にかかる半導体装置の製造方法を説明する図である。 第２の実施の形態にかかる半導体装置の製造方法を説明する図である。 第２の実施の形態にかかる半導体装置の製造方法を説明する図である。 第２の実施の形態にかかる半導体装置の製造方法を説明する図である。 第２の実施の形態にかかる半導体装置の製造方法を説明する図である。 第２の実施の形態にかかる半導体装置の製造方法を説明する図である。 第２の実施の形態にかかる半導体装置の製造方法を説明する図である。 第２の実施の形態にかかる半導体装置の製造方法を説明するフローチャートである。 第３の実施の形態にかかる半導体装置の製造方法を説明する図である。 第３の実施の形態にかかる半導体装置の製造方法を説明する図である。 第３の実施の形態にかかる半導体装置の製造方法を説明する図である。 第３の実施の形態にかかる半導体装置の製造方法を説明する図である。 第３の実施の形態にかかる半導体装置の製造方法を説明する図である。 第３の実施の形態にかかる半導体装置の製造方法を説明する図である。 第３の実施の形態にかかる半導体装置の製造方法を説明する図である。 第３の実施の形態にかかる半導体装置の製造方法を説明する図である。 第３の実施の形態にかかる半導体装置の製造方法を説明する図である。 第３の実施の形態にかかる半導体装置の製造方法を説明する図である。 第３の実施の形態にかかる半導体装置の製造方法を説明するフローチャートである。 複数個の半導体チップを積層させてモールド封止させる場合の途中工程を例示する図である。 再配線を行った面にさらに半導体チップをＦＣ実装した半導体装置を例示する図である。
以下に添付図面を参照して、実施の形態にかかる半導体装置の製造方法を詳細に説明する。なお、この実施の形態により本発明が限定されるものではない。
（第１の実施の形態）
図１〜１９は、第１の実施の形態にかかる半導体装置の製造方法を説明する図である。図２０は、第１の実施の形態にかかる半導体装置の製造方法を説明するフローチャートである。なお、以下の説明において、有機絶縁層５のうち、支持基板２側の面を第二面５ｄとし、その裏側の面を第一面５ｃとする（図９などを参照）。
まず、支持基板２となる８インチガラスウエハの表面に、光の透過が抑制された光吸収層（第１の樹脂層）３を形成する（ステップＳ１、図１も参照）。光吸収層３は、光の透過を抑える透過阻害材を合成樹脂に混合したものが用いられる。透過阻害材は、例えばカーボンブラック、グラファイト粉末や鉄、酸化チタンなどの金属酸化物、あるいは染料や顔料である。光吸収層３は、後の工程において、レーザ光の照射によって分解される。
光吸収層３は、０．１μｍ以上であって５μｍ以下の厚さで形成されるのが好ましい。例えば、光吸収層３を１．５μｍの厚さで形成する。光吸収層３の厚さが０．１μｍ未満の場合は、レーザ光の照射時に光吸収が効率的に行われず、光吸収層３がうまく分解されない場合がある。また、光吸収層３の厚さが５μｍを超えると、一部の光吸収層３が分解されずに、残存してしまう場合がある。
次に、光吸収層３上に熱可塑性樹脂層（第２の樹脂層）４を形成する（ステップＳ２、図２も参照）。熱可塑性樹脂層４は、１μｍ以上であって５０μｍ以下の厚さで形成される。例えば、熱可塑性樹脂層４は、１５μｍの厚さで形成される。熱可塑性樹脂層４の材料としては、ポリスチレン系、メタクリル樹脂系、ポリエチレン系、ポリプロピレン系、セルロース系、ポリアミド系、ポリフェニレンサルファイド（ＰＰＳ）系、ポリエーテルエーテルケトン（ＰＥＥＫ）系、液晶ポリマー（ＬＣＰ）系、ポリテトラフロロエチレン（ＰＴＦＥ）系、ポリエーテルイミド（ＰＥＩ）系、ポリアリレート（ＰＡＲ）系、ポリサルフォン（ＰＳＦ）系、ポリエーテルサルフォン（ＰＥＳ）系、ポリアミドイミド（ＰＡＩ）系などの合成樹脂を使用することができる。なお、光吸収層３として、熱可塑性材料に光の透過を抑える透過阻害材を混合したものを用いれば、光吸収層３上の熱可塑性樹脂層４を省略することも可能である。
熱可塑性樹脂層４の厚さが１μｍ未満では、光吸収層３にレーザ光が照射された際に、熱の影響でダメージを受ける可能性がある。また、熱可塑性樹脂層４の厚さが５０μｍを超えると、その上部に形成される有機絶縁層５の開口に歪みが発生する場合がある。
また、熱可塑性樹脂層４の材料としては、ガラス転移温度が１５０℃以上であって２８０℃以下のものを使用する。ガラス転移温度が１５０℃未満の場合は、高温時に軟化し有機絶縁層の開口がゆがむ問題が発生する。また、ガラス転移温度が２８０℃を超える合成樹脂については合成樹脂の作製そのものが難しくなる。
また、熱可塑性樹脂層４の材料としては、分解温度が２００℃以上であって４００℃以下のものを使用する。分解温度が２００℃未満の場合は、有機絶縁層５のキュア工程において、高温に耐えきれず分解されてしまうおそれがある。また、分解温度が４００℃を超える樹脂については合成樹脂の作製そのものが難しくなる。
また、熱可塑性樹脂層４の材料としては、２５℃での弾性率が０．０１ＧＰａ以上であって１０ＧＰａ以下であるものを使用する。弾性率が０．０１ＧＰａ未満の場合は、弾性率が低いため、有機絶縁層５の開口に歪みが発生したり、開口のテーパが広がったりしてしまう場合がある。また、弾性率が１０ＧＰａを超える合成樹脂については、合成樹脂にフィラーを入れる必要があり、開口を形成することが困難になる。
また、熱可塑性樹脂層４の熱膨張係数ＣＴＥ１が有機絶縁層の熱膨張係数ＣＴＥ２に対して「ＣＴＥ２×０．７以上であってＣＴＥ２×１．３以下」とする。ＣＴＥ２×０．７未満や、ＣＴＥ×１．３を超える場合は有機絶縁層５を形成した場合、開口部分が歪む問題が発生しやすくなる。
また、熱可塑性樹脂層４の材料としては、有機絶縁層５に含まれる溶剤に耐性のあるものを選択して使用する必要がある。耐性の無い材料を使用した場合には、有機絶縁層５を形成したときに、有機絶縁層５に含まれる溶剤によって熱可塑性樹脂層４が溶解して有機絶縁層５に混合してしまい、後に残渣となって除去が難しくなる。
次に、熱可塑性樹脂層４の上に有機絶縁層（絶縁層）５としてポリイミドを３μｍの厚さで形成する（ステップＳ３、図３も参照）。次に、露光現像によって、有機絶縁層５に開口５ａを形成する（ステップＳ４、図４も参照）。開口５ａは、第二面５ｄの接続パッドが形成される位置に対応させて形成される。開口５ａは、例えば、２０μｍの径寸法、４０μｍのピッチで形成される。
次に、有機絶縁層５の表面、開口５ａの形成の内側面、および開口５ａの形成によって露出された熱可塑性樹脂層４の表面に、めっきのシード層としてＴｉ膜・Ｃｕ膜６を形成する（ステップＳ５、図５も参照）。Ｔｉ膜・Ｃｕ膜６は、厚さが０．０５μｍのＴｉ膜と、厚さが０．１μｍのＣｕ膜で構成される。
次に、Ｔｉ膜・Ｃｕ膜６の上にレジスト７を厚さが５μｍとなるように塗布し、露光現像によって、第一の配線層（３μｍ幅）用の開口を形成する（ステップＳ６、図６も参照）。次に、シード層であるＴｉ膜・Ｃｕ膜６を電極として、電解Ｃｕめっきを行い３μｍの第一の配線層８を形成する（ステップＳ７、図７も参照）。
次に、レジスト７を除去し、さらにシード層のＣｕ膜・Ｔｉ膜６をエッチングする（ステップＳ８、図８も参照）。Ｃｕ膜・Ｔｉ膜６のうち、Ｃｕ膜のエッチングには硫酸と過酸化水素水を混合させたものを用い、Ｔｉ膜のエッチングにはアンモニア水と過酸化水素水を混合させたものを用いる。
次に、ポリイミドなどを塗布して有機絶縁層５を積層し、第１の半導体チップとして第一面５ｃに実装される半導体チップ１０の金属バンプ１０ａに対応する箇所に、２０μｍ径（４０μｍピッチ）で開口５ｂを形成する（ステップＳ９、図９も参照）。次に、有機絶縁層５の第一面５ｃ上に、半導体チップ１０をフリップチップ実装する（ステップＳ１０、図１０も参照）。
半導体チップ１０の金属バンプ１０ａは、ＳｎＡｇで構成される。なお、開口５ｂの形成によって露出された第一の配線層８に、Ｎｉ／Ｐｄ／Ａｕ膜を形成した後にＳｎＡｇバンプを形成してもよい。
また、金属バンプ１０ａとしては、ＳｎＡｇバンプ以外にＡｕ、Ｓｎ、Ａｇ、Ｃｕ、Ｂｉ、Ｉｎ、Ｇｅ、Ｎｉ、Ｐｄ、Ｐｔ、Ｐｂなどを使用してもよい。また、これらの金属の合金、混合物でもよい。金属バンプ１０ａのピッチは４０μｍピッチで２０μｍ径のバンプである。ＦＣ実装は金属バンプ１０ａ上にフラックスを塗布して配線パッド上にフリップチップボンダーで搭載し、リフロー炉に入れて接続を行い、その後、フラックスを洗浄液で除去する。またはフラックスを用いずにＳｎＡｇバンプの酸化膜を、プラズマを用いて除去し、フリップチップボンダーを用いてパルスヒートで接続を行ってもよい。有機絶縁層５の第一面５ｃ上には、複数の半導体チップがフリップチップ実装される。
半導体チップ１０をフリップチップ実装後、チップ下に樹脂を流し込んでアンダーフィル１７を形成し（ステップＳ１１、図１１も参照）、さらに第一面５ｃ上を熱硬化性樹脂１３でモールド封止する（ステップＳ１２、図１２も参照）。
次に、支持基板２側から光吸収層３に向けてレーザ光を印加する（ステップＳ１３、図１３も参照）。レーザ光は支持基板２を透過して光吸収層３に到達する。光吸収層３は、光の透過が抑制されているので、印加されたレーザ光を吸収して温度が上昇する。これにより、光吸収層３が分解されるので、光吸収層３の部分で支持基板２を剥離する（ステップＳ１４、図１４も参照）。光吸収層３が分解されるので、支持基板２の剥離を円滑に行いやすくなり、有機絶縁層５に亀裂が入るなどの不具合の発生を抑えることができる。
印加するレーザ光としては、例えば、ＹＡＧレーザ、ルビーレーザ、エキシマレーザ、ＣＯ２レーザ、Ｈｅ−Ｎｅレーザ、Ａｒイオンレーザ、半導体レーザなどを用いることができる。レーザ光の波長は、１０．６μｍ、１０６４ｎｍの赤外線や、６９４ｎｍ、６３３ｎｍ、５３２ｎｍ、５１４ｎｍ、４８８ｎｍの可視光や、３５５ｎｍ、３５１ｎｍ、３０８ｎｍ、２４８ｎｍなどの紫外線など、種々の波長を使用することが可能である。また、レーザは連続波、パルス波ともに使用することができる。
支持基板２を剥離した後に、光吸収層３、および熱可塑性樹脂層４をアセトンなどの溶剤で除去する（ステップＳ１５、図１５も参照）。ここで、熱可塑性樹脂層４は溶剤に溶解することが必要である。残渣が残っている場合はさらにプラズマを印加して除去してもよい。
光吸収層３、および熱可塑性樹脂層４を除去したあとに、有機絶縁層５の開口５ａから露出しているＴｉ膜・Ｃｕ膜６をエッチングにより除去する（ステップＳ１６、図１６も参照）。Ｃｕ膜のエッチングには硫酸と過酸化水素水を混合させたものを用い、Ｔｉ膜のエッチングにはアンモニア水と過酸化水素水を混合させたものを用いる。
裏面に接続パッドとなるＣｕが露出するので、そのＣｕ面へ無電解めっきにより、Ｎｉ・Ｐｄ・Ａｕ膜１４を形成する（ステップＳ１７、図１７も参照）。Ｎｉ・Ｐｄ・Ａｕ膜１４は、Ｎｉを３μｍ、Ｐｄを０．０５μｍ、Ａｕを０．５μｍの厚さで形成することで構成される。
次に、有機絶縁層５の第一面５ｃと同様に、第２の半導体チップとしての半導体チップ１０を第二面５ｄ上にフリップチップ実装する（ステップＳ１８、図１８も参照）。以上の工程により、半導体装置の中間体１５が製造される。その後、プリント基板１６にマウントペーストを用いて中間体１５を搭載し、Ａｕワイヤー２９を用いてプリント基板１６上にワイヤーボンディングする。さらに樹脂モールドを行い、裏面にボールを搭載することで（ステップＳ１９、図１９も参照）、半導体装置が完成する。
上述の工程に従って、半導体装置を製造し、温度サイクル試験に供して、その信頼性を調べた。なお温度サイクル試験は−５５℃（３０ｍｉｎ）〜２５℃（５ｍｉｎ）〜１２５℃（３０ｍｉｎ）を１サイクルとして行った。その結果３０００サイクル後でも第一面５ｃおよび第二面のフリップチップ接続箇所には破断の発生はほとんど認められなかった。
なお、有機絶縁層５としては、ポリイミドの他にも、ＰＢＯ（ポリベンゾオキサゾール）、フェノール系樹脂、アクリル系樹脂などを使用してもよい。第一の配線層８の材料にはＣｕを例示したが、Ａｌ、Ａｇ、Ａｕなども使用できる。また、ガラスを支持基板２として配線層を形成したが、シリコン、サファイヤなどを使用してもよい。すなわち、支持基板２には、レーザ光が透過する材料であれば種々のものを使用することができる。
また、本実施の形態では、第一の配線層８のみの１層の構成を例示しているが、配線層を多層構成にしてもよい。配線層を多層構成にする場合には、ステップＳ８の工程を実施した後に、ステップＳ３〜ステップＳ８までの工程を繰り返して、第二の配線層、第三の配線層などを形成する。例えば、ステップＳ８に相当する工程の次に、ポリイミドをさらに塗布して有機絶縁層を積層するとともに、露光現像によりＶｉａ層を形成する。レジストを５μｍ塗布し、露光現像によって、第二の配線層（３μｍ幅）の開口を形成する。シード層を電極として電解Ｃｕめっきを行い３μｍの第一の配線層を形成する。レジストを除去し、さらにシード層のＣｕ膜とＴｉ膜をエッチングする。Ｃｕ膜は硫酸と過酸化水素水を混合させたものを用い、Ｔｉ膜はアンモニア水と過酸化水素水を混合させたものを用いる。
また、本実施の形態では、両面実装型の半導体装置を例示して説明したがこれに限られない。例えば、一方の面に半導体チップが実装され、他方の面に端子が形成された片面実装型の半導体装置の製造において、本実施の形態の製造方法を適用してもよい。
（第２の実施の形態）
図２１〜２８は、第２の実施の形態にかかる半導体装置の製造方法を説明する図である。図２９は、第２の実施の形態にかかる半導体装置の製造方法を説明するフローチャートである。実施の形態１と同様の構成については同様の符号を付して、詳細な説明を省略する。
第２の実施の形態にかかる半導体装置の製造方法は、図２９に示すように、ステップＳ９までは実施の形態１で説明したものと同様の手順になっている。
そして、ステップＳ９の工程の後で、ポリイミドなどの有機膜を塗布して有機絶縁層５を積層するとともに、第一面５ｃの接続パッドに対応する部分に、短辺７０μｍ長辺１００ｕｍの開口を１００μｍピッチで形成する（ステップＳ２１、図２１も参照）。配線層は１層の例を説明したが、もちろん２層の構成や、それ以上の層で構成されてもよい。
次に、開口した接続パッド上にＮｉ・Ｐｄ・Ａｕ膜２４を形成する（ステップＳ２２、図２２も参照）。Ｎｉ・Ｐｄ・Ａｕ膜２４は、無電解めっきによりＮｉを３μｍ、Ｐｄを０．０５μｍ、Ａｕを０．５μｍの厚さで形成する。
半導体チップ２０を有機絶縁層５上にマウント材２５を用いてマウントする（ステップＳ２３、図２３も参照）。マウント材２５には、例えば樹脂を用いる。また、マウント材２５に用いる樹脂は、エポキシ系、アクリル系、ポリイミド系などの液状樹脂やフィルム状の樹脂を用いる。なお、本実施の形態２で用いる半導体チップ２０には、金属バンプ１０ａは設けられておらず、表面にＡｌパッド２０ａが形成されている。そのため、半導体チップ２０は、有機絶縁層５に対してフリップチップ実装ではなく、マウント材２５を用いたマウントがなされる。
有機絶縁層５上にマウントする半導体チップ２０は１個でもよいし、２個以上積層して多段にチップを形成してもよい。次に、マウントした半導体チップ２０のＡｌパッド２０ａを、Ａｕワイヤー２９を用いたワイヤーボンディングによってＮｉ・Ｐｄ・Ａｕ膜２４と電気的に接続する（ステップＳ２４、図２４も参照）。
次に、有機絶縁層５の第一面５ｃ上を熱硬化性樹脂１３でモールド封止する（ステップＳ２５、図２５も参照）。そして、実施の形態１で説明した手順と同様に、ステップＳ１３〜ステップＳ１７の工程を経て、樹脂体２７が製造される（図２６，２７も参照）。
そして、この樹脂体をダイシングにより個片化し、個片化したパッケージをさらに基板２８上に樹脂を使用してマウントする（ステップＳ２６）。図２８に示すように個片化されたパッケージを積層してもよい。積層されたパッケージに対して、さらにワイヤーボンディングを行う（ステップＳ２７）。次に、全体をモールド樹脂で覆い、基板２８の裏面にボール搭載を行うことで（ステップＳ２８）、半導体装置が完成する。
上述の工程に従って、半導体装置を製造し、温度サイクル試験に供して、その信頼性を調べた。なお温度サイクル試験は−５５℃（３０ｍｉｎ）〜２５℃（５ｍｉｎ）〜１２５℃（３０ｍｉｎ）を１サイクルとして行った。その結果３０００サイクル後でもワイヤーボンディング部分の破断の発生はほとんど認められなかった。配線層に形成した電極パッドが剥離層に向かって小さくなっていることと、配線層の外周にモールド樹脂があることにより、配線層の伸び縮みが抑えられ、電極パッドにかかる応力が小さくなり、リフローや、ＴＣＴ（Ｔｈｅｒｍａｌ Ｃｙｃｌｉｎｇ Ｔｅｓｔ）時の電極パッドと配線の破断が発生しにくくなっている。
なお、有機絶縁層５としては、ポリイミドの他にも、ＰＢＯ（ポリベンゾオキサゾール）、フェノール系樹脂、アクリル系樹脂などを使用してもよい。第一の配線層８の材料にはＣｕを例示したが、Ａｌ、Ａｇ、Ａｕなども使用できる。また、ガラスを支持基板２として配線層を形成したが、シリコン、サファイヤなどを使用してもよい。すなわち、支持基板２には、レーザ光が透過する材料であれば種々のものを使用することができる。
（第３の実施の形態）
図３０〜３９は、第３の実施の形態にかかる半導体装置の製造方法を説明する図である。図４０は、第３の実施の形態にかかる半導体装置の製造方法を説明するフローチャートである。上記実施の形態と同様の構成については同様の符号を付して、詳細な説明を省略する。
まず、支持基板２となる８インチガラスウエハの表面に、光の透過が抑制された光吸収層（第１の樹脂層）３を形成する（ステップＳ３１）。光吸収層３は、光の透過を抑える透過阻害材を合成樹脂に混合したものが用いられる。透過阻害材は、例えばカーボンブラック、グラファイト粉末や鉄、酸化チタンなどの金属酸化物、あるいは染料や顔料である。光吸収層３は、後の工程において、レーザ光の照射によって分解される。
光吸収層３は、０．１μｍ以上であって５μｍ以下の厚さで形成されるのが好ましい。例えば、光吸収層３を１．５μｍの厚さで形成する。光吸収層３の厚さが０．１μｍ未満の場合は、レーザ光の照射時に光吸収が効率的に行われず、光吸収層３がうまく分解されない場合がある。また、光吸収層３の厚さが５μｍを超えると、一部の光吸収層３が分解されずに、残存してしまう場合がある。
次に、光吸収層３上に熱可塑性樹脂層（第２の樹脂層）４を形成する（ステップＳ３２、図３０も参照）。熱可塑性樹脂層４は、１μｍ以上であって５０μｍ以下の厚さで形成される。例えば、熱可塑性樹脂層４は、１５μｍの厚さで形成される。熱可塑性樹脂層４の材料としては、ポリスチレン系、メタクリル樹脂系、ポリエチレン系、ポリプロピレン系、セルロース系などの合成樹脂を使用することができる。
熱可塑性樹脂層４の厚さが１μｍ未満では、光吸収層３にレーザ光が照射された際に、熱の影響でダメージを受ける可能性がある。また、熱可塑性樹脂層４の厚さが５０μｍを超えると、その上部へマウントする半導体チップ２０の位置ずれが発生しやすくなる。
また、熱可塑性樹脂層４の材料としては、ガラス転移温度が１５０℃以上であって２８０℃以下のものを使用する。ガラス転移温度が１５０℃未満の場合は、高温時に軟化してしまい、その上部へマウントする半導体チップ２０の位置ずれが発生しやすくなる。また、ガラス転移温度が２８０℃を超える合成樹脂については合成樹脂の作製そのものが難しくなる。熱可塑性樹脂層４には、接着性の性質を有しているものが用いられる。
次に、熱可塑性樹脂層４上に第１の半導体チップとして半導体チップ２０を位置合わせしてマウントする（ステップＳ３３、図３１も参照）。次に、半導体チップ２０がマウントされた熱可塑性樹脂層４の第一面４ａ上を熱硬化性樹脂１３でモールド封止する（ステップＳ３４、図３２も参照）。
次に、支持基板２側から光吸収層３に向けてレーザ光を印加する（ステップＳ３５、図３３も参照）。レーザ光は支持基板２を透過して光吸収層３に到達する。光吸収層３は、光の透過が抑制されているので、印加されたレーザ光を吸収して温度が上昇する。これにより、光吸収層３が分解されるので、光吸収層３の部分で支持基板２を剥離する（ステップＳ３６、図３４も参照）。光吸収層３が分解されるので、支持基板２の剥離を円滑に行いやすくなる。
印加するレーザ光としては、例えば、ＹＡＧレーザ、ルビーレーザ、エキシマレーザ、ＣＯ２レーザ、Ｈｅ−Ｎｅレーザ、Ａｒイオンレーザ、半導体レーザなどを用いることができる。レーザ光の波長は、１０．６μｍ、１０６４ｎｍの赤外線や、６９４ｎｍ、６３３ｎｍ、５３２ｎｍ、５１４ｎｍ、４８８ｎｍの可視光や、３５５ｎｍ、３５１ｎｍ、３０８ｎｍ、２４８ｎｍなどの紫外線など、種々の波長を使用することが可能である。また、レーザは連続波、パルス波ともに使用することができる。
支持基板２を剥離した後に、光吸収層３、および熱可塑性樹脂層４をアセトンなどの溶剤で除去する（ステップＳ３７、図３５も参照）。ここで、熱可塑性樹脂層４は溶剤に溶解することが必要である。残渣が残っている場合はさらにプラズマを印加して除去してもよい。
ステップＳ３６，Ｓ３７の工程を経ることで、半導体チップ２０のパッドが露出するため、この面に再配線を形成する（ステップＳ３８）。再配線を形成する工程は、例えば、まず有機絶縁層５を形成する（図３６も参照）。そして、有機絶縁層５に開口を形成する。この開口は、半導体チップ２０のパッドと一致する位置に形成される。次に、Ｔｉ／Ｃｕなどの膜をスパッタし、再配線を形成するためのレジストを形成し、配線用の開口を形成する。そして、レジストの開口部にＣｕめっきを行い、レジストを除去し、スパッタした膜をエッチングすることで再配線３１を形成する（図３７も参照）。
このように、再配線を形成した後、有機絶縁層５を積層し、開口を形成する（ステップＳ３９、図３８も参照）。次に、開口を行った部分にはんだボール３０を形成する（ステップＳ４０、図３９も参照）。さらにダイシングを行う（ステップＳ４１）ことでＦａｎｏｕｔタイプのＣＳＰを形成することができる。
上述の工程に従って、半導体装置を製造し、温度サイクル試験に供して、その信頼性を調べた。なお温度サイクル試験は−５５℃（３０ｍｉｎ）〜２５℃（５ｍｉｎ）〜１２５℃（３０ｍｉｎ）を１サイクルとして行った。その結果３０００サイクル後でも再配線を行った箇所の配線の破断の発生はほとんど認められなかった。
なお、再配線を形成するときに、熱硬化性樹脂４の剛性が足りない場合、熱可塑性樹脂層４に対して、ガラスや金属板を貼り付けて、剛性を上げた状態で、再配線の工程を行ってもよい。
また、有機絶縁層５としてはポリイミドの他にも、ＰＢＯ（ポリベンゾオキサゾール）、フェノール系樹脂、アクリル系樹脂などを使用してもよい。再配線の配線材料にはＣｕを例示したが、Ａｌ、Ａｇ、Ａｕなども使用できる。また、ガラスを支持基板２として配線層を形成したが、シリコン、サファイヤなどを使用してもよい。すなわち、支持基板２には、レーザ光が透過する材料であれば種々のものを使用することができる。
図４１は、複数個の半導体チップ２０を積層させてモールド封止させる場合の途中工程を例示する図である。図４１に示すように、チップを支持基板２（熱可塑性樹脂層４）上にマウントする半導体チップ２０は、複数個であってもよい。すなわち、最下層の第１の半導体チップ上に第３の半導体チップとしてさらに半導体チップ２０を積層してもよい。なお、複数個の半導体チップ２０は、例えば、予めＴＳＶで積層させた積層体をマウントしてもよい。また、ＴＳＶ用のチップを支持基板２（熱可塑性樹脂層４）上に１個ずつ積み上げながらＦＣ実装して積層させてもよい。
このように、支持基板２上で半導体チップ２０を予め積層すれば、最下層の半導体チップ２０、すなわち、支持基板２（熱可塑性樹脂層４）に直接マウントされる半導体チップ２０を、略平坦な支持基板２にマウントすることができる。したがって、最下層の半導体チップ２０に反りが発生しにくくなる。半導体チップ２０に反りがあると、半導体チップ２０同士の接続を確保しにくくなる。特に、半導体チップ２０に設けられるバンプのピッチが微細である場合に、半導体チップ２０に反りがあると、互いの接続を確保しにくくなる。一方、本実施の形態では、マウントされる半導体チップ２０の反りを抑えることができるので、半導体チップ２０同士を確実に接続させやすくなる。
図４２は、再配線を行った面にさらに半導体チップ２０をＦＣ実装した半導体装置を例示する図である。図４２に示すように、ステップＳ３８の再配線の工程の後に、再配線を行った面にさらに第４の半導体チップとして半導体チップ２０をＦＣ実装して半導体装置を構成してもよい。
なお、上記実施形態は例示であり、発明の範囲はそれらに限定されない。
２ 支持基板、３ 光吸収層（第１の樹脂層）、４ 熱可塑性樹脂層（第２の樹脂層）、５ 有機絶縁層、５ａ，５ｂ 開口、５ｃ 第一面、５ｄ 第二面、６ Ｔｉ膜・Ｃｕ膜、７ レジスト、８ 第一の配線層、１０ 半導体チップ、１０ａ 金属バンプ、１３ 熱硬化性樹脂、１４ Ｎｉ・Ｐｄ・Ａｕ膜、１５ 中間体、１６ プリント基板、１７ アンダーフィル、２０ 半導体チップ、２０ａ Ａｌパッド、２４ Ｎｉ・Ｐｄ・Ａｕ膜、２５ マウント材、２７ 樹脂体、２８ 基板。

Claims (5)

  1. 光の透過が抑制された第１の樹脂層を支持基板上に形成し、
    前記第１の樹脂層上に熱可塑性樹脂からなる第２の樹脂層を形成し、
    前記第２の樹脂層上に絶縁層および配線層を形成し、
    前記配線層上に第１の半導体チップを実装し、
    前記第１の樹脂層にレーザ光を照射して前記支持基板を剥離し、
    前記第２の樹脂層を除去する半導体装置の製造方法。
  2. 前記絶縁層内で前記配線層により電気的に導通された層間接続体を形成し、
    前記層間接続体に電気的に接続するように、前記第２の樹脂層の除去により露出された面に対し第２の半導体チップを実装する請求項１に記載の半導体装置の製造方法。
  3. 光の透過が抑制された第１の樹脂層を支持基板上に形成し、
    前記第１の樹脂層上に熱可塑性樹脂からなる第２の樹脂層を形成し、
    前記第２の樹脂層上に第１の半導体チップを実装し、
    前記第１の樹脂層にレーザ光を照射して前記支持基板を剥離し、
    前記第２の樹脂層を除去する半導体装置の製造方法。
  4. 前記支持基板は、透光性の材料で構成され、
    前記レーザ光は、前記支持基板を通して前記第１の樹脂層に照射される請求項１から３のいずれか１項に記載の半導体装置の製造方法。
  5. 前記第１の樹脂層は、光の透過を抑える透過阻害材を合成樹脂に混入させて構成される請求項１から４のいずれか１項に記載の半導体装置の製造方法。
JP2010213216A 2010-09-24 2010-09-24 半導体装置の製造方法 Pending JP2012069734A (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2010213216A JP2012069734A (ja) 2010-09-24 2010-09-24 半導体装置の製造方法
TW100131342A TWI446465B (zh) 2010-09-24 2011-08-31 Manufacturing method of semiconductor device
US13/235,417 US20120077313A1 (en) 2010-09-24 2011-09-18 Semiconductor device manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2010213216A JP2012069734A (ja) 2010-09-24 2010-09-24 半導体装置の製造方法

Publications (1)

Publication Number Publication Date
JP2012069734A true JP2012069734A (ja) 2012-04-05

Family

ID=45871068

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2010213216A Pending JP2012069734A (ja) 2010-09-24 2010-09-24 半導体装置の製造方法

Country Status (3)

Country Link
US (1) US20120077313A1 (ja)
JP (1) JP2012069734A (ja)
TW (1) TWI446465B (ja)

Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015170767A (ja) * 2014-03-07 2015-09-28 富士通株式会社 回路基板の製造方法
WO2015199030A1 (ja) * 2014-06-26 2015-12-30 凸版印刷株式会社 配線基板、半導体装置及び半導体装置の製造方法
JP2016111303A (ja) * 2014-12-10 2016-06-20 凸版印刷株式会社 配線基板、半導体装置及び半導体装置の製造方法
JP2016146402A (ja) * 2015-02-06 2016-08-12 凸版印刷株式会社 配線基板、半導体装置及び半導体装置の製造方法
JP2016178101A (ja) * 2015-03-18 2016-10-06 凸版印刷株式会社 配線基板積層体、これを用いた半導体装置及び半導体装置の製造方法
JP2017050464A (ja) * 2015-09-03 2017-03-09 凸版印刷株式会社 配線基板積層体、その製造方法及び半導体装置の製造方法
JP2017098481A (ja) * 2015-11-27 2017-06-01 日立化成株式会社 半導体装置の製造方法
JP2017103364A (ja) * 2015-12-02 2017-06-08 凸版印刷株式会社 配線基板積層体、半導体装置、及び半導体装置の製造方法
WO2017209178A1 (ja) * 2016-06-02 2017-12-07 富士フイルム株式会社 パターン製造方法、半導体装置の製造方法および積層体
WO2017217293A1 (ja) * 2016-06-15 2017-12-21 東レ株式会社 感光性樹脂組成物
JP2018018968A (ja) * 2016-07-28 2018-02-01 凸版印刷株式会社 配線基板積層体
WO2018043250A1 (ja) * 2016-08-29 2018-03-08 東レ株式会社 感光性樹脂組成物、硬化膜、有機ｅｌ表示装置、半導体電子部品、半導体装置
KR20180077115A (ko) * 2018-06-25 2018-07-06 최재규 투명 캐리어를 이용한 인쇄회로기판과 반도체 패키지의 제조방법
KR20190039379A (ko) * 2017-10-03 2019-04-11 신에쓰 가가꾸 고교 가부시끼가이샤 반도체 장치 및 그의 제조 방법, 그리고 적층체
CN110140083A (zh) * 2016-12-28 2019-08-16 阿尔卑斯阿尔派株式会社 透镜驱动装置
JP7574560B2 (ja) 2020-07-27 2024-10-29 Ｔｏｐｐａｎホールディングス株式会社 半導体パッケージ基板の製造方法

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9202714B2 (en) * 2012-04-24 2015-12-01 Micron Technology, Inc. Methods for forming semiconductor device packages
US20140252632A1 (en) * 2013-03-06 2014-09-11 Hans-Joachim Barth Semiconductor devices
JP5897486B2 (ja) * 2013-03-14 2016-03-30 株式会社東芝 半導体装置
TWI473228B (zh) * 2013-04-24 2015-02-11 矽品精密工業股份有限公司 半導體封裝件之製法
KR101731700B1 (ko) 2015-03-18 2017-04-28 앰코 테크놀로지 코리아 주식회사 반도체 디바이스 및 그 제조 방법
DE102015118742A1 (de) 2015-11-02 2017-05-04 Ev Group E. Thallner Gmbh Verfahren zum Bonden und Lösen von Substraten
US9947570B2 (en) * 2015-12-30 2018-04-17 International Business Machines Corporation Handler bonding and debonding for semiconductor dies
WO2020110619A1 (ja) * 2018-11-27 2020-06-04 リンテック株式会社 半導体装置の製造方法
JPWO2020235597A1 (ja) * 2019-05-22 2020-11-26
CN112479153B (zh) * 2020-10-21 2024-03-26 武汉鲲鹏微纳光电有限公司 种子层的刻蚀方法、晶圆级封装键合环及其制作方法

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100891269B1 (ko) * 2001-01-31 2009-04-06 소니 가부시끼 가이샤 반도체 장치 및 그 제조 방법
JP4649745B2 (ja) * 2001-02-01 2011-03-16 ソニー株式会社 発光素子の転写方法
JP4212255B2 (ja) * 2001-03-30 2009-01-21 株式会社東芝 半導体パッケージ
US6911375B2 (en) * 2003-06-02 2005-06-28 International Business Machines Corporation Method of fabricating silicon devices on sapphire with wafer bonding at low temperature
US6928726B2 (en) * 2003-07-24 2005-08-16 Motorola, Inc. Circuit board with embedded components and method of manufacture
JP3914239B2 (ja) * 2005-03-15 2007-05-16 新光電気工業株式会社 配線基板および配線基板の製造方法
JP5065586B2 (ja) * 2005-10-18 2012-11-07 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
KR20090018852A (ko) * 2006-06-06 2009-02-23 닛본 덴끼 가부시끼가이샤 반도체 패키지, 그 제조 방법, 반도체 장치 및 전자 기기
KR100883807B1 (ko) * 2007-05-21 2009-02-17 삼성전자주식회사 반도체 소자 패키지 및 그 제조 방법
US7795073B2 (en) * 2008-02-01 2010-09-14 Hynix Semiconductor Inc. Method for manufacturing stack package using through-electrodes
JP2010010644A (ja) * 2008-05-27 2010-01-14 Toshiba Corp 半導体装置の製造方法
JP2010092931A (ja) * 2008-10-03 2010-04-22 Toshiba Corp 半導体装置の製造方法及び半導体装置の製造装置
US8704350B2 (en) * 2008-11-13 2014-04-22 Samsung Electro-Mechanics Co., Ltd. Stacked wafer level package and method of manufacturing the same
US8617926B2 (en) * 2010-09-09 2013-12-31 Advanced Micro Devices, Inc. Semiconductor chip device with polymeric filler trench

Cited By (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015170767A (ja) * 2014-03-07 2015-09-28 富士通株式会社 回路基板の製造方法
EP3163607A4 (en) * 2014-06-26 2018-03-07 Toppan Printing Co., Ltd. Wiring board, semiconductor device and method for manufacturing semiconductor device
WO2015199030A1 (ja) * 2014-06-26 2015-12-30 凸版印刷株式会社 配線基板、半導体装置及び半導体装置の製造方法
TWI665765B (zh) * 2014-06-26 2019-07-11 日商凸版印刷股份有限公司 配線基板、半導體裝置及半導體裝置之製造方法
KR101995141B1 (ko) * 2014-06-26 2019-07-02 도판 인사츠 가부시키가이샤 배선 기판, 반도체 장치 및 반도체 장치의 제조 방법
KR20170018449A (ko) * 2014-06-26 2017-02-17 도판 인사츠 가부시키가이샤 배선 기판, 반도체 장치 및 반도체 장치의 제조 방법
CN106463473A (zh) * 2014-06-26 2017-02-22 凸版印刷株式会社 配线基板、半导体装置以及半导体装置的制造方法
US9735099B2 (en) 2014-06-26 2017-08-15 Toppan Printing Co., Ltd. Wiring substrate, semiconductor device and method for manufacturing semiconductor device
JPWO2015199030A1 (ja) * 2014-06-26 2017-05-25 凸版印刷株式会社 配線基板、半導体装置及び半導体装置の製造方法
JP2016111303A (ja) * 2014-12-10 2016-06-20 凸版印刷株式会社 配線基板、半導体装置及び半導体装置の製造方法
JP2016146402A (ja) * 2015-02-06 2016-08-12 凸版印刷株式会社 配線基板、半導体装置及び半導体装置の製造方法
JP2016178101A (ja) * 2015-03-18 2016-10-06 凸版印刷株式会社 配線基板積層体、これを用いた半導体装置及び半導体装置の製造方法
JP2017050464A (ja) * 2015-09-03 2017-03-09 凸版印刷株式会社 配線基板積層体、その製造方法及び半導体装置の製造方法
JP2017098481A (ja) * 2015-11-27 2017-06-01 日立化成株式会社 半導体装置の製造方法
JP2017103364A (ja) * 2015-12-02 2017-06-08 凸版印刷株式会社 配線基板積層体、半導体装置、及び半導体装置の製造方法
JPWO2017209178A1 (ja) * 2016-06-02 2019-03-22 富士フイルム株式会社 パターン製造方法、半導体装置の製造方法および積層体
WO2017209178A1 (ja) * 2016-06-02 2017-12-07 富士フイルム株式会社 パターン製造方法、半導体装置の製造方法および積層体
KR102138069B1 (ko) 2016-06-02 2020-07-27 후지필름 가부시키가이샤 패턴 제조 방법, 반도체 장치의 제조 방법 및 적층체
KR20190003680A (ko) * 2016-06-02 2019-01-09 후지필름 가부시키가이샤 패턴 제조 방법, 반도체 장치의 제조 방법 및 적층체
WO2017217293A1 (ja) * 2016-06-15 2017-12-21 東レ株式会社 感光性樹脂組成物
JP2018018968A (ja) * 2016-07-28 2018-02-01 凸版印刷株式会社 配線基板積層体
WO2018043250A1 (ja) * 2016-08-29 2018-03-08 東レ株式会社 感光性樹脂組成物、硬化膜、有機ｅｌ表示装置、半導体電子部品、半導体装置
CN110140083A (zh) * 2016-12-28 2019-08-16 阿尔卑斯阿尔派株式会社 透镜驱动装置
CN110140083B (zh) * 2016-12-28 2021-06-15 阿尔卑斯阿尔派株式会社 透镜驱动装置
JP2019067980A (ja) * 2017-10-03 2019-04-25 信越化学工業株式会社 半導体装置及びその製造方法、並びに積層体
KR20190039379A (ko) * 2017-10-03 2019-04-11 신에쓰 가가꾸 고교 가부시끼가이샤 반도체 장치 및 그의 제조 방법, 그리고 적층체
TWI787360B (zh) * 2017-10-03 2022-12-21 日商信越化學工業股份有限公司 半導體裝置及其製造方法，以及層合體
KR102637336B1 (ko) * 2017-10-03 2024-02-19 신에쓰 가가꾸 고교 가부시끼가이샤 반도체 장치 및 그의 제조 방법, 그리고 적층체
KR101971402B1 (ko) * 2018-06-25 2019-04-22 최재규 투명 캐리어를 이용한 인쇄회로기판의 제조방법
KR20180077115A (ko) * 2018-06-25 2018-07-06 최재규 투명 캐리어를 이용한 인쇄회로기판과 반도체 패키지의 제조방법
JP7574560B2 (ja) 2020-07-27 2024-10-29 Ｔｏｐｐａｎホールディングス株式会社 半導体パッケージ基板の製造方法

Also Published As

Publication number Publication date
TW201216385A (en) 2012-04-16
TWI446465B (zh) 2014-07-21
US20120077313A1 (en) 2012-03-29

Similar Documents

Publication Publication Date Title
TWI446465B (zh) Manufacturing method of semiconductor device
US9013037B2 (en) Semiconductor package with improved pillar bump process and structure
JP5375708B2 (ja) 半導体装置の製造方法
US10242972B2 (en) Package structure and fabrication method thereof
TWI237310B (en) Semiconductor device and manufacturing method of the same
JP2009260255A (ja) 半導体装置および多層配線基板ならびにそれらの製造方法
JP2009200274A (ja) 集積半導体装置
JP2009253283A (ja) 取外し可能な相互接続構造体
JP2011204765A (ja) 半導体装置の製造方法及び半導体装置
JP6201610B2 (ja) 電子装置の製造方法及び回路基板
WO2020090601A1 (ja) 半導体パッケージ用配線基板及び半導体パッケージ用配線基板の製造方法
JP2009253284A (ja) 取外し可能な相互接続構造体の製造方法
JP2020004926A (ja) 配線基板及び配線基板の製造方法
JP2011077398A (ja) 半導体装置の製造方法
JP5543754B2 (ja) 半導体パッケージ及びその製造方法
JP2015185615A (ja) 半導体装置および電子回路装置
JPWO2015198837A1 (ja) 半導体装置およびその製造方法
WO2011083524A1 (ja) 半導体装置及びその製造方法
JP7347440B2 (ja) 半導体パッケージ用配線基板の製造方法
JP7052464B2 (ja) 微細配線層付きコアレス基板の製造方法、および半導体パッケージの製造方法
JP6319013B2 (ja) 電子装置及び電子装置の製造方法
JP2024539420A (ja) マルチプル・ダイ・アセンブリ
TWI786491B (zh) 半導體裝置及其製造方法
WO2016098296A1 (ja) 半導体装置及びその製造方法
JP2021097104A (ja) 複合配線基板及び複合配線基板の製造方法