JP2012058653A - Method for driving plasma display device and plasma display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress black luminance by performing a stable writing operation without using a forced initialization operation and to suppress deterioration of display quality of an image with low luminance.SOLUTION: When a voltage obtained by deducting a voltage of a data electrode from a low pressure side voltage of a sustaining pulse is a first voltage and a voltage obtained by deducting a low pressure side voltage of a writing pulse from a low pressure side voltage of a scanning pulse is a third voltage, a voltage obtained by deducting the third voltage from the first voltage is equal to or higher than a discharge start voltage having the data electrode as an anode and a scanning electrode as a cathode. When gradation to be displayed without emitting light of a discharge cell in all subfields is defined as gradation "0", dither processing or error diffusion processing is performed for inputted image signals after performing nonlinear processing for replacing image signals which are less than a signal level corresponding to a prescribed gradation threshold with image signals corresponding to the gradation "0".

Description

  The present invention relates to a driving method of a plasma display device using an AC surface discharge type plasma display panel and a plasma display device.

  A plasma display panel (hereinafter abbreviated as “panel”) includes a plurality of discharge cells each having a display electrode pair consisting of a scan electrode and a sustain electrode and a data electrode, and is red with ultraviolet rays generated by gas discharge in the discharge cell. Color display is performed by exciting and emitting phosphors of green and blue colors.

  As a method for driving the panel, a subfield method, that is, a method in which a single field is formed using a plurality of subfields having an initialization period, an address period, and a sustain period, and gradation display is performed by combining subfields that emit light. Is common. An initialization operation is performed during the initialization period of each subfield, a write operation is performed during the write period, and a maintenance operation is performed during the sustain period. The initialization operation is an operation that generates initialization discharge and forms wall charges necessary for the subsequent address operation. The initializing operation includes a forced initializing operation that generates an initializing discharge regardless of the operation of the immediately preceding subfield, and a selective initializing operation that generates an initializing discharge in a discharge cell that has performed an address discharge in the immediately preceding subfield. There is. The address operation is an operation in which an address discharge is selectively generated in the discharge cells in accordance with an image to be displayed to form wall charges, and the sustain operation is to generate a sustain discharge by alternately applying a sustain pulse to the display electrode pair, This is an operation of causing the phosphor layer of the corresponding discharge cell to emit light. The light emission of the phosphor layer due to the sustain discharge is light emission related to gradation display, and the light emission associated with the forced initialization operation is light emission not related to gradation display.

  Among the subfield methods, a driving method is being studied in which the luminance of the gradation “0” for displaying black is lowered and light emission not related to gradation display is reduced as much as possible to improve the contrast. For example, Patent Document 1 discloses a driving method in which the forced initialization operation is performed once per field and the forced initialization operation is performed using a slowly changing ramp waveform voltage.

  Japanese Patent Application Laid-Open No. 2004-259542 discloses a gradation “0” for displaying black by further dividing light emission not related to gradation display by dividing the display electrode pair into n and performing the forced initialization operation once in n fields. A driving method is disclosed in which the brightness is further reduced and the contrast is further improved.

JP 2000-242224 A JP 2006-091295 A

  However, even with the driving methods described in Patent Document 1 and Patent Document 2, since the forced initialization operation is performed, light emission not related to gradation display occurs. This means that even a discharge cell displaying a black gradation “0” emits light, and there is a limit to improving the contrast. In addition, the forced initialization operation has a function of accumulating wall charges necessary for generating an address discharge in the subsequent address period, and in addition, a priming for surely generating an address discharge by shortening the discharge delay time. It also has the function of generating. Therefore, if the forced initializing operation is simply omitted, there is a problem that the address discharge does not occur, or the address delay becomes too long for the address discharge to become unstable, and normal image display cannot be performed. Therefore, when displaying an image with low brightness after an image with almost no light emitting discharge cells continues, or when displaying an image with low brightness in an image area in which no discharge cells with light emitting continue. There was also a problem that display quality deteriorated.

  The present invention has been made in view of these problems, and performs a stable writing operation without using a forced initialization operation to suppress black luminance and suppress a decrease in display quality of an image with low luminance. An object of the present invention is to provide a device driving method and a plasma display device.

  In order to achieve the above object, the present invention forms a single field using a plurality of subfields each having an address period, a sustain period, and an erase period, and includes a plurality of discharge cells each having a scan electrode, a sustain electrode, and a data electrode. A plasma display device driving method for driving a panel provided with a first voltage obtained by subtracting a voltage applied to a data electrode from a low-voltage side voltage of a sustain pulse applied to a scan electrode in the sustain period, and a sustain period The voltage obtained by subtracting the voltage applied to the data electrode from the high-voltage side voltage of the sustain pulse applied to the scan electrode in FIG. 2 is used as the second voltage, and is applied to the data electrode from the low-voltage side voltage of the scan pulse applied to the scan electrode in the writing period. When the voltage obtained by subtracting the low-voltage side voltage of the write pulse is the third voltage, the voltage obtained by subtracting the third voltage from the first voltage is applied to the data electrode. The voltage obtained by subtracting the third voltage from the second voltage is equal to or higher than the discharge start voltage using the electrode as the electrode and the scan electrode as the cathode, and the scan is performed using the data electrode as the anode and the scan electrode as the cathode. When the gradation that is less than the sum of the discharge start voltage with the electrode as the anode and the display without emitting the discharge cells in all subfields is gradation “0”, the input image signal In addition, a dither process or an error diffusion process is performed after performing non-linear processing that replaces an image signal having a signal level less than a signal level corresponding to a predetermined tone threshold with an image signal corresponding to tone “0”. According to this method, it is possible to provide a driving method of a plasma display device that suppresses black luminance by performing stable writing operation without using forced initialization operation and suppresses deterioration in display quality of an image with low luminance. .

  In the driving method of the plasma display device of the present invention, when the gradation to be displayed by emitting the discharge cell in one subfield having the smallest luminance weight is gradation “1”, the predetermined gradation threshold is gradation. The predetermined gradation threshold value when “0” or more and gradation “1” or less and the time for continuously displaying a black image is long is the predetermined gradation threshold when the time for continuously displaying a black image is short. It is desirable to set larger than the adjustment threshold.

  Also, the driving method of the plasma display device of the present invention divides the image display area into a plurality of small areas, and based on the time during which the black image is continuously displayed in each of the small areas, a predetermined floor for each corresponding small area. A key threshold may be set.

  The present invention also comprises a panel having a plurality of discharge cells each having a scan electrode, a sustain electrode, and a data electrode, and a plurality of subfields each having an address period, a sustain period, and an erase period. And a driving circuit that generates a voltage waveform and applies it to each electrode of the panel, wherein the driving circuit applies to the data electrode from the low-voltage side voltage of the sustain pulse applied to the scan electrode in the sustain period The voltage obtained by subtracting the voltage is set as the first voltage, the voltage obtained by subtracting the voltage applied to the data electrode from the high-voltage side voltage of the sustain pulse applied to the scan electrode in the sustain period is set as the second voltage, and the scan electrode is applied in the write period. When the voltage obtained by subtracting the low-voltage side voltage of the write pulse applied to the data electrode from the low-voltage side voltage of the scan pulse to be applied is the third voltage, The voltage obtained by subtracting the third voltage from the voltage is equal to or higher than the discharge start voltage using the data electrode as the anode and the scan electrode as the cathode, and the voltage obtained by subtracting the third voltage from the second voltage as the anode is used for scanning. Generates a drive voltage waveform that is less than the sum of the discharge start voltage with the electrode as the cathode and the discharge start voltage with the data electrode as the cathode and the scan electrode as the anode, and without causing the discharge cells to emit light in all subfields When the gradation to be displayed is gradation “0”, an image signal having a signal level lower than a signal level corresponding to a predetermined gradation threshold is replaced with an image signal corresponding to gradation “0” for the input image signal. After performing the non-linear process, a dither process or an error diffusion process is performed. With this configuration, it is possible to provide a plasma display device that suppresses the black luminance by performing a stable writing operation without using the forced initializing operation and suppresses the deterioration of the display quality of an image with low luminance.

  According to the present invention, a method for driving a plasma display apparatus and a plasma display apparatus that perform stable writing operation without using forced initialization operation to suppress black luminance and suppress deterioration in display quality of an image having low luminance. Can be provided.

It is a disassembled perspective view of the panel used for the plasma display apparatus in Embodiment 1 of this invention. It is an electrode array figure of the panel used for the plasma display apparatus. It is a drive voltage waveform figure applied to each electrode of the plasma display apparatus. It is a figure for demonstrating the definition of a 1st voltage, a 2nd voltage, and a 3rd voltage. It is a figure which shows an example of the method of measuring a discharge start voltage simply. It is a figure which shows an example of the dither pattern used for a dither process. It is a circuit block diagram of the plasma display apparatus in Embodiment 1 of the present invention. It is a circuit block diagram of the image signal processing circuit of the plasma display device. It is a figure which shows operation | movement of the nonlinear process part of the plasma display apparatus. It is a circuit diagram of the scan electrode drive circuit of the plasma display device. It is a circuit diagram of the sustain electrode drive circuit of the plasma display device. It is a circuit diagram of the data electrode drive circuit of the plasma display device. It is a figure which shows the division | segmentation of the image display area of the plasma display apparatus in Embodiment 2 of this invention. It is a circuit block diagram of the image signal processing circuit of the plasma display device.

  Hereinafter, a plasma display device according to an embodiment of the present invention will be described with reference to the drawings.

(Embodiment 1)
FIG. 1 is an exploded perspective view of panel 10 used in the plasma display device in accordance with the first exemplary embodiment of the present invention. A plurality of display electrode pairs 24 each including a scanning electrode 22 and a sustaining electrode 23 are formed on a glass front substrate 21. A dielectric layer 25 is formed so as to cover the display electrode pair 24, and a protective layer 26 is formed on the dielectric layer 25. The protective layer 26 is formed using magnesium oxide, which is a material having high electron emission performance, in order to easily generate discharge. A plurality of data electrodes 32 are formed on the back substrate 31, a dielectric layer 33 is formed so as to cover the data electrodes 32, and a grid-like partition wall 34 is formed thereon. A phosphor layer 35 that emits red, green, and blue light is provided on the side surface of the partition wall 34 and on the dielectric layer 33. For example, (Y, Gd) BO ₃ : Eu is used as the red phosphor, Zn ₂ SiO ₄ : Mn is used as the green phosphor, and BaMgAl ₁₀ O ₁₇ : Eu is used as the blue phosphor. Each of them uses a phosphor as a main component.

  The front substrate 21 and the rear substrate 31 are arranged to face each other so that the display electrode pair 24 and the data electrode 32 intersect each other with a minute discharge space interposed therebetween, and the outer periphery thereof is sealed with a sealing material such as glass frit. Has been. In the discharge space, for example, a mixed gas of neon and xenon is sealed as a discharge gas. The discharge space is partitioned into a plurality of sections by partition walls 34, and discharge cells are formed at the intersections between the display electrode pairs 24 and the data electrodes 32. These discharge cells discharge and emit light to display an image.

  Note that the structure of the panel 10 is not limited to the above-described structure, and for example, the panel 10 may include a stripe-shaped partition wall.

  FIG. 2 is an electrode array diagram of panel 10 used in the plasma display device in accordance with the exemplary embodiment of the present invention. The panel 10 includes n scan electrodes SC1 to SCn (scan electrodes 22 in FIG. 1) and n sustain electrodes SU1 to SUn (sustain electrodes 23 in FIG. 1) that are long in the row direction. M data electrodes D1 to Dm (data electrodes 32 in FIG. 1) that are long in the column direction are arranged. A discharge cell is formed at a portion where one pair of scan electrode SCi (i = 1 to n) and sustain electrode SUi intersects one data electrode Dj (j = 1 to m), and the discharge cell is in the discharge space. M × n are formed.

  Next, a driving voltage waveform for driving panel 10 and its operation will be described.

  The plasma display apparatus forms one field by using a plurality of subfields having an address period, a sustain period, and an erase period, and displays an image by controlling light emission / non-light emission of each discharge cell for each subfield. .

  In the present embodiment, the forced initializing operation for forcibly generating the initializing discharge is not performed regardless of the presence or absence of the previous discharge.

  In the address period, an address operation is performed in which address discharge is selectively generated in the discharge cells to emit light to form wall charges. In the sustain period, a sustain operation is performed in which a sustain pulse of the number corresponding to the luminance weight determined in advance for each subfield is alternately applied to the display electrode pair to generate a sustain discharge in the discharge cell that generated the address discharge. I do. In the erasing period, an erasing discharge is selectively generated only in the discharge cells that generated the address discharge in the immediately preceding address period, and the history of wall charges formed by the address discharge or the subsequent sustain discharge is erased, and the subsequent address discharge is performed. An erasing operation is performed to form necessary wall charges on each electrode.

  As a subfield configuration, for example, one field is divided into 10 subfields (SF1, SF2,..., SF10), and each subfield is (1, 2, 3, 6, 11, 18, 30). , 44, 60, 80). However, the present invention is not limited to the subfield configuration such as the number of subfields and the luminance weight.

  FIG. 3 is a waveform diagram of driving voltage applied to each electrode of the plasma display device in accordance with the exemplary embodiment of the present invention.

  In the address period of subfield SF1, voltage 0 (V) is applied to data electrode D1 to data electrode Dm, voltage Ve is applied to sustain electrode SU1 to sustain electrode SUn, and voltage Vc is applied to scan electrode SC1 to scan electrode SCn. To do. Next, a scan pulse of voltage Va is applied to scan electrode SC1 in the first row, and an address pulse of voltage Vd is applied to data electrode Dk corresponding to the discharge cell to emit light.

  Then, the voltage difference at the intersection between the data electrode Dk and the scan electrode SC1 is because the positive wall voltage on the data electrode Dk is added to the difference (Vd−Va) of the externally applied voltage, and exceeds the discharge start voltage VFds. Discharge occurs between data electrode Dk and scan electrode SC1. Then, the discharge generated between data electrode Dk and scan electrode SC1 extends between scan electrode SC1 and sustain electrode SU1, and an address discharge occurs. A positive wall voltage is accumulated on scan electrode SC1, a negative wall voltage is accumulated on sustain electrode SU1, and a negative wall voltage is also accumulated on data electrode Dk. Here, the wall voltage on the electrode represents a voltage generated by wall charges accumulated on the dielectric layer covering the electrode, the protective layer, the phosphor layer, and the like.

  In this manner, an address operation is performed in which an address discharge is caused in the discharge cells to be lit in the first row and wall voltage is accumulated on each electrode. On the other hand, the voltage at the intersection of the data electrode Dh to which the address pulse is not applied and the scan electrode SC1 does not exceed the discharge start voltage VFds, so the address discharge does not occur.

  Next, a scan pulse is applied to scan electrode SC2 in the second row, and an address pulse is applied to data electrode Dk corresponding to the discharge cell to emit light. Then, an address discharge occurs between data electrode Dk and scan electrode SC2 and between sustain electrode SU2 and scan electrode SC2, a positive wall voltage is accumulated on scan electrode SC2, and a negative wall voltage is applied on sustain electrode SU2. And a negative wall voltage is also accumulated on the data electrode Dk. In this manner, an address operation is performed in which an address discharge is caused in the discharge cell to be lit in the second row and wall voltage is accumulated on each electrode. On the other hand, the voltage at the intersection between the data electrode to which the address pulse is not applied and scan electrode SC2 does not exceed the discharge start voltage VFds, so that address discharge does not occur.

  Thereafter, the same address operation is performed until the scan electrode SCn in the n-th row, and wall charges necessary for the subsequent sustain discharge are formed.

  Here, for the following description, the first voltage V1, the second voltage V2, and the third voltage V3 are defined as shown in FIG. The voltage obtained by subtracting the voltage applied to the data electrode Dj from the low voltage side voltage of the sustain pulse applied to the scan electrode SCi in the sustain period to be described later as the first voltage, and the high voltage side of the sustain pulse applied to the scan electrode SCi in the sustain period The voltage obtained by subtracting the voltage applied to the data electrode Dj from the voltage is used as the second voltage, and the low voltage side voltage of the address pulse applied to the data electrode Dj is subtracted from the low voltage side voltage of the scan pulse applied to the scan electrode SCi in the address period. This voltage is taken as the third voltage.

  Further, a discharge start voltage with the data electrode Dj as an anode and the scan electrode SCi as a cathode is a discharge start voltage VFds, and a discharge start voltage with the data electrode Dj as a cathode and the scan electrode SCi as an anode is a discharge start voltage VFsd. The discharge with the data electrode Dj as the anode and the scan electrode SCi as the cathode is a discharge in which the electric field in the discharge cell when the discharge occurs is a high potential side on the data electrode Dj side and a low potential side on the scan electrode SCi side. It is. The discharge with the data electrode Dj as the cathode and the scan electrode as the anode is a discharge in which the electric field in the discharge cell when the discharge occurs is a low potential side on the data electrode Dj side and a high potential side on the scan electrode SCi side. . Since the protective layer 26 of magnesium oxide having high electron emission performance is formed on the scan electrode SCi side, the discharge start voltage VFds is lower than the discharge start voltage VFsd.

  At this time, the voltage Va of the scan pulse applied to the scan electrode SCi is set so as to satisfy the following two conditions (condition 1) and (condition 2).

(Condition 1) For all discharge cells, the voltage obtained by subtracting the third voltage V3 from the first voltage V1 is equal to or higher than the discharge start voltage VFds with the data electrode Dj as the anode and the scan electrode SCi as the cathode,
(V1-V3) ≧ VFds is satisfied.

(Condition 2) For all the discharge cells, a voltage obtained by subtracting the third voltage V3 from the second voltage V2 is a discharge start voltage VFds and a data electrode Dj with the data electrode Dj as an anode and the scan electrode SCi as a cathode. Less than the sum of the discharge start voltage VFsd with the scan electrode SCi as the anode and
(V2−V3) ≦ (VFds + VFsd) is satisfied.

  In the sustain period of subfield SF1, voltage 0 (V) is applied to sustain electrode SU1 through sustain electrode SUn, and a sustain pulse of voltage Vs is applied to scan electrode SC1 through scan electrode SCn. Then, in the discharge cell in which the address discharge has occurred, the voltage difference between scan electrode SCi and sustain electrode SUi is the voltage Vs plus the difference between the wall voltage on scan electrode SCi and the wall voltage on sustain electrode SUi. It exceeds the discharge start voltage VFss between scan electrode SCi and sustain electrode SUi. Then, a sustain discharge occurs between scan electrode SCi and sustain electrode SUi, and phosphor layer 35 emits light by the ultraviolet rays generated at this time. Then, a negative wall voltage is accumulated on scan electrode SCi, and a positive wall voltage is accumulated on sustain electrode SUi. Further, a positive wall voltage is accumulated on the data electrode Dk. On the other hand, the sustain discharge does not occur in the discharge cell in which the address discharge has not occurred, and the wall voltage at the end of the immediately preceding field is maintained.

  Subsequently, voltage 0 (V) is applied to scan electrode SC1 through scan electrode SCn, and a sustain pulse of voltage Vs is applied to sustain electrode SU1 through sustain electrode SUn. Then, the sustain discharge occurs again in the discharge cell in which the sustain discharge has occurred, and the phosphor layer 35 emits light. Then, a negative wall voltage is accumulated on sustain electrode SUi, and a positive wall voltage is accumulated on scan electrode SCi. Thereafter, similarly, sustain pulses of the number corresponding to the luminance weight are alternately applied to scan electrode SC1 through scan electrode SCn and sustain electrode SU1 through sustain electrode SUn, and the sustain discharge is continued in the discharge cells that have caused the address discharge. generate.

  In the subsequent erasing period of subfield SF1, voltage 0 (V) is applied to sustain electrode SU1 through sustain electrode SUn, and an upward ramp waveform voltage that gradually rises to voltage Vr is applied to scan electrode SC1 through scan electrode SCn. In the present embodiment, the voltage Vr is set to the same voltage as the voltage Vs. Then, a weak erasing discharge occurs between scan electrode SCi and sustain electrode SUi in the discharge cell in which the sustain discharge has been performed. Then, the wall voltage on scan electrode SCi and sustain electrode SUi is weakened.

  Thereafter, voltage Ve is applied to sustain electrode SU1 through sustain electrode SUn, and a downward ramp waveform voltage that gently falls from voltage 0 (V) toward voltage Vi is applied to scan electrode SC1 through scan electrode SCn. The voltage Vi is set to be equal to or slightly higher than the voltage Va of the scanning pulse.

  Then, a weak discharge is generated again in the discharge cell in which the weak erasing discharge is generated, and an excessive portion of the wall voltage on scan electrode SCi, sustain electrode SUi, and data electrode Dk is discharged, and writing is performed. It is adjusted to a wall voltage suitable for operation. In this way, the erase operation is completed.

  The subsequent operations in SF2 to SF10 are the same as those in SF1 except for the number of sustain pulses.

  In this embodiment, the voltage Vc is −145 (V), the voltage Va is −280 (V), the voltage Vs is 200 (V), the voltage Vr is 200 (V), the voltage Vi is −260 (V), The voltage Ve is 20 (V), and the voltage Vd is 60 (V). However, these voltage values are not limited to the values described above, and are desirably set optimally based on the discharge characteristics of the panel and the specifications of the plasma display device.

  Note that the discharge start voltage VFds and the discharge start voltage VFsd of the panel 10 used in the present embodiment are measured by the methods described later, and their values are as follows. The discharge start voltage varies depending on the phosphor, and the discharge start voltage VFds between the “data electrode-scan electrode” for the discharge cell coated with the red phosphor is 200 ± 10 (V), and the discharge start voltage VFsd is 320 ± 10 ( V), the discharge start voltage VFds between the “data electrode and the scan electrode” for the discharge cell coated with the green phosphor is 220 ± 10 (V), the discharge start voltage VFsd is 350 ± 10 (V), and the blue fluorescence The discharge start voltage VFds between the “data electrode and the scan electrode” for the discharge cell coated with the body was 200 ± 10 (V), and the discharge start voltage VFsd was 330 ± 10 (V). The discharge start voltage VFss between the “scan electrode and sustain electrode” is 250 ± 10 (V) for the discharge cells coated with red and blue phosphors, and for the discharge cells coated with green phosphors, It was 280 ± 10 (V).

  In the present embodiment, the voltage on the low voltage side of the sustain pulse is voltage 0 (V), and the voltage applied to the data electrode in the sustain period is voltage 0 (V), so the first voltage V1 is voltage 0 (V ). Further, since the low voltage side of the scan pulse is the voltage Va and the low voltage side voltage of the write pulse is the voltage 0 (V), the third voltage V3 is the voltage Va. Further, the maximum value of the discharge start voltage VFds is a voltage 230 (V) in consideration of variations. Therefore, (voltage V1−voltage V3) = − Va> (maximum value of VFds), that is, 280 (V)> 230 (V), and it is understood that (condition 1) is satisfied in all the discharge cells.

  Further, since the high voltage side of the sustain pulse is the voltage Vs and the voltage applied to the data electrode in the sustain period is the voltage 0 (V), the second voltage V2 is the voltage Vs. The minimum value of the sum of the discharge start voltage VFsd and the discharge start voltage VFds is a voltage 500 (V). Therefore, the minimum value of (second voltage V2−third voltage V3) = Vs−Va <(VFds + VFsd), that is, 480 (V) <500 (V), and (condition 2) also applies to all discharge cells. You can see that you are satisfied.

  Further, as apparent from the above voltage, a voltage lower than the low voltage side voltage Va of the scan pulse is applied to the scan electrode by applying a voltage not lower than the low voltage side voltage Va of the scan pulse and not higher than the high voltage side voltage Vs of the sustain pulse. A voltage exceeding the high voltage Vs of the sustain pulse is not applied. Therefore, a discharge cell that has not performed address discharge does not emit light.

  As apparent from the above voltage, when the voltage Va is set low so as to satisfy (Condition 1), the absolute value | Va | of the low-voltage side voltage Va of the scan pulse is the absolute value of the high-voltage side voltage Vs of the sustain pulse. It becomes larger than the value | Vs |.

  As described above, in this embodiment, the forcibly initializing operation is performed by setting the drive voltage waveform applied to each electrode, in particular, the voltage Va of the scan pulse so as to satisfy (Condition 1) and (Condition 2). Even if it is not used, the write operation can be generated stably. The reason is considered as follows.

  First, (Condition 1) will be described. In order to generate the address discharge, it is necessary to start the discharge between the data electrode Dj and the scan electrode SCi. In order to start a discharge by applying a relatively low voltage Vd to the data electrode Dj, a voltage substantially equal to the discharge start voltage VFds is applied between the data electrode Dj and the scan electrode SCi when a scan pulse is applied to the scan electrode SCi. A sufficient wall voltage must be stored on the data electrode Dj so that it is applied in between. As described above, in this embodiment, the forced initialization operation is not performed, and no discharge is generated in the discharge cells displaying black. Therefore, the wall voltage cannot be actively controlled, and the wall voltage of the discharge cell displaying black is indefinite. However, even in such a discharge cell, if there are a few charged particles in the discharge space, they move to each electrode so as to relax the electric field inside the discharge space and adhere to the wall of the discharge cell. Accumulate wall voltage.

  First, the wall voltage accumulated in this way will be described. During the sustain period, a large amount of charged particles are generated in the discharge cell that generates the sustain discharge, and when these particles diffuse, a small amount of charged particles are supplied to the space inside the discharge cell that displays black without causing the sustain discharge. It is thought that. In the discharge cell displaying black, the wall voltage is slowly accumulated so as to alleviate the potential difference between the electrodes by the voltages applied to scan electrode SCi, sustain electrode SUi, and data electrode. If the voltage at which the wall voltage gradually approaches (finally settles) is defined as the neglected wall voltage, the neglected wall voltage when the sustain pulse is continuously applied alternately to the scan electrode SCi and the sustain electrode SUi is the high voltage of the sustain pulse. The voltage is between the side voltage and the low voltage. Actually, since a drive voltage waveform other than the sustain pulse is also applied, it can be considered that the neglected wall voltage of each discharge cell is substantially close to the low-voltage side voltage of the sustain pulse.

  The neglected wall voltage is greatly affected by the charging characteristics of the phosphor applied inside the discharge cell. In this embodiment, the charging characteristics of the phosphor are +20 (μC / g) for the red phosphor, −30 (μC / g) for the green phosphor, and +10 (μC / g) for the blue phosphor, respectively. Since only the green phosphor is charged to a negative potential, the left wall voltage is lower than that of the red and blue phosphors.

  Next, the voltage inside the discharge cell in the address period will be described. On the data electrode Dj of the discharge cell displaying black, the wall voltage is gradually accumulated toward the low voltage side voltage of the sustain pulse or the neglected wall voltage close thereto. On the other hand, the voltage Va of the scan pulse in the present embodiment is a voltage that satisfies (Condition 1). Therefore, a wall voltage sufficient to generate the address discharge is accumulated on the data electrode Dj, and the address discharge can be generated without performing any forced initialization operation.

  In addition, the wall voltage of the discharge cell displaying black slowly approaches the left wall voltage, and when the voltage obtained by adding the wall voltage to the voltage between the “data electrode-scan electrode” approaches the discharge start voltage during the erasing period, the dark current is generated. The wall voltage on the data electrode Dj is lowered. And since the dark current flowing at this time plays a role of priming to assist the address discharge, it is considered that a stable address discharge can be generated without causing a large discharge delay even in a discharge cell displaying black. be able to.

  In this way, by setting the drive voltage applied to each electrode to satisfy (Condition 1), in particular, by setting the scan pulse voltage Va low so as to satisfy (Condition 1), the forced initialization operation is not performed. The wall voltage necessary for addressing can be accumulated, and priming for stabilizing the address discharge can also be generated.

  Next, (Condition 2) will be described. If the voltage Va of the scan pulse is too low, a discharge occurs regardless of whether or not an address operation is performed when the sustain pulse voltage Vs is applied to the scan electrode SCn in the sustain period, and an image cannot be displayed. In order to suppress this erroneous discharge, it is necessary to set the voltage between the “data electrode-scanning electrode” to be equal to or lower than the discharge start voltage VFsd when the sustain pulse voltage Vs is applied. This condition is (Condition 2).

  Thus, in the present embodiment, the drive voltage waveform is set so as to satisfy (Condition 1) and (Condition 2) in all the discharge cells. Therefore, it is possible to display an image without light emission not related to gradation display by omitting the forced initialization operation while stably generating the writing operation.

  Note that the discharge start voltage VFsd, the discharge start voltage VFds, and the wall voltage are, for example, IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. ED-24, NO. 7, JULY, 1977 "Measurement of a Plasma in the AC Plasma Display panel Using RF Capacitance and Microwave Techniques". Or you may measure simply as follows. An example of a method for simply measuring the discharge start voltage will be described with reference to FIG.

  First, an operation for erasing wall charges is performed. Specifically, as shown in the wall charge erasing period of FIG. 5, a pulsed voltage Vers sufficiently higher than the expected discharge start voltage is alternately applied between the electrodes to be measured, for example, the data electrode and the scan electrode. To do. Next, the discharge start is observed. Specifically, as shown in the measurement period of FIG. 5, a pulsed voltage Vmsr lower than the expected discharge start voltage is applied to one electrode, for example, the data electrode, and the light emission associated with the discharge at that time is photogenerated. Detection is performed using a light detection sensor such as Maru. When no discharge is observed, after performing an operation of erasing wall charges during the wall charge erasing period, light emission is observed by applying a pulsed voltage Vmsr with a slightly increased absolute value of voltage during the measurement period.

  This operation is repeated, and the absolute value of the minimum voltage Vmsr in which light emission is observed in the measurement period is the discharge start voltage. At this time, if the voltage Vmsr applied in the measurement period is a positive voltage, the discharge start voltage VFds with the data electrode as the anode and the scan electrode as the cathode can be measured. If the voltage Vmsr applied during the measurement period is a negative voltage, the discharge start voltage VFsd with the data electrode as the cathode and the scan electrode as the anode can be measured.

  If the discharge start voltage is known, the voltage at which discharge starts is measured for the discharge cell in which the wall voltage is accumulated, and the wall voltage can be known as the difference between the voltage value and the discharge start voltage measured in advance. .

  Next, a method for displaying gradation will be described. In the present embodiment, one field is composed of a plurality of subfields with predetermined luminance weights, and an actual image display is performed by selecting a plurality of light emission patterns from an arbitrary combination of subfields. Used for. For example, in order to display the black gradation “0”, the discharge cells are not caused to emit light in all the subfields, and in order to display the gradation “1”, the discharge is performed only in the subfield SF1 having the smallest luminance weight. What is necessary is just to make a cell light-emit. In order to display the gradation “9”, the discharge cells may be caused to emit light in the subfield SF1, the subfield SF2, and the subfield SF4.

  The plasma display device displays an image by causing a discharge cell to emit light a number of times proportional to the luminance weight of each subfield and controlling the subfield to emit light. Therefore, the brightness that can be displayed by the plasma display device is not continuous but takes a jump value and is additive. Therefore, the displayable luminance is an equidistant sequence such as gradation “0”, gradation “1”, gradation “2”,..., Gradation “255”.

  However, the brightness perceived by humans is logarithmic with respect to luminance, as is generally known. As described above, the brightness that can be displayed on the panel takes values that are skipped at equal intervals, but the brightness that is proportional to the logarithm of the displayable luminance is not equal. For this reason, the brightness that can be displayed is large at low luminance, and the smoothness of the image is impaired.

  If the luminance used for display is limited to displayable luminance in this way, the gradation display capability on a dark screen is reduced. Therefore, in this embodiment, dither processing or error diffusion processing is performed on the image signal to display pseudo gray levels, and the gray level display capability is supplemented by increasing the gray levels that can be displayed.

  Next, regarding the dither processing, black gradation “0” displayed without emitting discharge cells in all subfields and gradation “0” displayed by emitting discharge cells in one subfield having the smallest luminance weight. As an example, a method of displaying pseudo gray levels between “1” and “1” will be described.

  FIG. 6 is a diagram illustrating an example of a dither pattern used for dither processing. A black rectangle indicates a pixel that displays a gradation “0”, and a white rectangle indicates a pixel that displays a gradation “1”. FIG. 6 shows seven gradations “1/8”, “2/8”, “3/8”, “4/8”, “4” between the gradation “0” and the gradation “1”. 7 dither patterns displaying gradations of “5/8”, “6/8”, and “7/8” are shown.

  Next, a method for creating such a dither pattern will be described. In order to display (N−1) intermediate gray levels between the gray level “a” and the gray level “b” using the gray level “a” and the gray level “b”, first, the display screen is displayed. The pixel block is divided into a set of N pixels, and the first gradation “a” is displayed with n pixels (n = 1, 2,..., N−1) of the pixel block, and the remaining ( N−n) The second gradation “b” is displayed by the pixel. Then, by forming the display screen by arranging the pixel blocks without overlapping each other, a gradation “(na + (N−n)) between the first gradation“ a ”and the second gradation“ b ”is formed. b) / N ”is generated.

  In this manner, an arbitrary number of intermediate gradations that can be displayed between arbitrary gradations can be artificially increased.

  In addition to the above-described dither process, a well-known error diffusion process can be used as a method for displaying a pseudo gray level. Further, a method combining dither processing and error diffusion processing (for example, see JP-A-2004-88404) may be used.

  Next, a drive circuit for driving the panel 10 will be described. FIG. 7 is a circuit block diagram of plasma display device 40 in accordance with the exemplary embodiment of the present invention. The plasma display device 40 forms one field using the panel 10 having a plurality of discharge cells having scan electrodes, sustain electrodes, and data electrodes, and a plurality of subfields having an address period, a sustain period, and an erase period. And a drive circuit for generating a drive voltage waveform and applying the waveform to each electrode of the panel 10. The drive circuit includes an image signal processing circuit 41, a data electrode drive circuit 42, a scan electrode drive circuit 43, a sustain electrode drive circuit 44, a timing generation circuit 45, and a power supply circuit (not shown) that supplies necessary power to each circuit block. It has.

  The image signal processing circuit 41 performs non-linear processing to be described later on the input image signal, and converts it into image data indicating light emission / non-light emission of the discharge cells in each of the subfields.

  The data electrode drive circuit 42 generates an address pulse to be applied to each of the data electrodes D1 to Dm during the address period based on the image data, and applies the address pulse to each of the data electrodes D1 to Dm.

  The timing generation circuit 45 constitutes one field using a plurality of subfields having a write period, a sustain period, and an erase period based on the vertical and horizontal synchronization signals, and various timing signals for controlling the operation of each circuit block. Is supplied to each circuit block.

  The scan electrode drive circuit 43 has a drive voltage waveform set so as to satisfy the above-described two conditions (condition 1) and (condition 2). The scan electrode drive circuit 43 generates the drive voltage waveform based on the timing signal and generates each scan electrode. SC1 is applied to each of the scan electrodes SCn. Sustain electrode drive circuit 44 generates the drive voltage waveform described above based on the timing signal and applies it to sustain electrode SU1 through sustain electrode SUn.

  FIG. 8 is a circuit block diagram showing details of the image signal processing circuit 41 of the plasma display device 40 according to the embodiment of the present invention. The image signal processing circuit 41 includes a black image detection unit 411, an integration unit 412, a gradation threshold setting unit 413, a delay unit 415, a nonlinear processing unit 416, an intermediate gradation processing unit 417, and an image data conversion unit 418.

  The black image detection unit 411 detects an image signal of an image (hereinafter, abbreviated as “black image”) in which almost no discharge cells emit light from the input image signal. In this embodiment, the black image detection unit 411 is configured using a comparator that compares the signal level corresponding to the gradation “0” with the image signal. If the ratio exceeding the signal level corresponding to the gradation “0” with respect to the input image signal of one field is 0.2% or less, the field is detected as a black image. In other words, if the lighting rate of the discharge cell predicted from the input image signal of one field is 0.2% or less, the field is detected as a black image.

  The accumulating unit 412 measures the time when the black image detecting unit 411 continuously detects the black image, that is, the time Tk for displaying the black image continuously (hereinafter abbreviated as “black image continuing time Tk”). In the present embodiment, accumulating unit 412 is configured using a counter that operates in a field cycle. The counter is incremented in the field where the black image detection unit 411 detects the black image, and the counter is reset in the field where the black image detection unit 411 does not detect the black image. Accordingly, the counter outputs the number of fields in which the black image detection unit 411 has continuously detected the black image as the black image duration Tk.

  The gradation threshold setting unit 413 sets a predetermined gradation threshold K (hereinafter simply referred to as “gradation threshold K”) (0 ≦ K ≦ 1) based on the output of the integration unit 412. The gradation threshold value K is determined depending on the black image duration time Tk. When the black image duration time Tk = “0”, the gradation threshold value K = “0”. As the black image duration time Tk becomes longer, the gradation threshold value K becomes larger. The gradation threshold value K → “1” at the black image duration Tk → ∞. As described above, the gradation threshold K is the gradation “0” or more and the gradation “1” or less, and the gradation threshold K when the black image duration Tk is long is the same as that when the black image duration Tk is short. It is set to be larger than the gradation threshold value K. The gradation threshold setting unit 413 can be configured using, for example, a ROM table. Or you may calculate using a calculation formula.

  The delay unit 415 is provided to match the phase of the output of the gradation threshold setting unit 413 and the image signal input to the nonlinear processing unit 416. In this embodiment, the delay unit 415 is a field memory that delays the image signal by one field. It is configured.

  The nonlinear processing unit 416 replaces an image signal having a signal level lower than the signal level corresponding to the gradation threshold value K with an image signal having a signal level corresponding to gradation “0”, that is, black.

  FIG. 9 is a diagram illustrating the operation of the nonlinear processing unit 416 of the plasma display device 40 according to the embodiment of the present invention. The horizontal axis represents an image signal (input signal) input to the nonlinear processing unit 416, and the vertical axis represents An image signal (output signal) output from the nonlinear processing unit 416 is illustrated. However, the signal levels of the input signal and the output signal are shown in terms of gradation.

  If the signal level of the input signal is equal to or higher than the gradation threshold K, the nonlinear processing unit 416 outputs the input signal as it is as an output signal. If the signal level of the input signal is less than the gradation threshold value K, the signal level is replaced with the signal level corresponding to the gradation “0” and output. As described above, the gradation threshold value K is determined depending on the black image duration time Tk. When the black image duration time Tk = “0”, the gradation threshold value K = “0”, and as the black image duration time Tk increases. The gradation threshold value K increases, and the gradation threshold value K → “1” at the black image duration Tk → ∞. In this way, the nonlinear processing unit 416 performs nonlinear processing on the input image signal.

  The intermediate gradation processing unit 417 performs dither processing on the image signal that has been subjected to nonlinear processing using, for example, a dither pattern as shown in FIG. The dither processing can be realized by using a circuit described in, for example, Japanese Patent Application Laid-Open No. 2004-138383. An error diffusion process may be performed instead of the dither process. Furthermore, for example, a combination of dither processing and error diffusion processing may be performed using a circuit described in JP-A-2004-88404.

  The image data conversion unit 418 inputs an image signal that has been subjected to dither processing or error diffusion processing, and corresponds to “1” and “0” of each bit of the digital signal for light emission / non-light emission in each of the subfields. Output the image data. The image data conversion unit 418 can be configured by a conversion table using, for example, a ROM.

  As described above, in the present embodiment, the input image signal is subjected to nonlinear processing for replacing an image signal having a signal level lower than the signal level corresponding to the gradation threshold value K with an image signal corresponding to the gradation “0”. Thereafter, dither processing or error diffusion processing is performed. In other words, when the gradation “1” or lower is displayed using dither processing, error diffusion processing, or the like, nonlinear processing is performed to replace the signal level of the corresponding image signal with the signal level for gradation “0”. The reason for performing such nonlinear processing will be described below.

  When the gradation “1” or lower is displayed in a pseudo manner using, for example, dither processing, there are discharge cells that emit light only once in several fields, as shown in FIG. In such a discharge cell, priming is insufficient and the probability of occurrence of a discharge failure increases. If the black image duration time Tk becomes longer, the probability that a discharge failure will occur further increases, and the luminance is determined depending on the probability that a discharge failure will occur. The risk of damage increases.

  Therefore, in the present embodiment, an area in which image display quality is likely to be impaired by replacing an image signal having a signal level lower than the signal level corresponding to the gradation threshold K with an image signal having a signal level corresponding to the gradation “0”. Press to force black. As a result, there is no possibility that a pattern unrelated to the image signal is displayed, and a decrease in image display quality can be suppressed.

  Such a phenomenon becomes more prominent as the black image duration Tk becomes longer. Therefore, the gradation threshold value K is set to increase as the black image duration Tk becomes longer.

  FIG. 10 is a circuit diagram of scan electrode driving circuit 43 of plasma display device 40 in accordance with the exemplary embodiment of the present invention. Scan electrode drive circuit 43 includes sustain pulse generation circuit 50, ramp waveform voltage generation circuit 60, and scan pulse generation circuit 70.

  Sustain pulse generation circuit 50 includes power recovery circuit 51, switching element Q55, switching element Q56, and switching element Q59, and generates sustain pulses to be applied to scan electrode SC1 through scan electrode SCn. The power recovery circuit 51 recovers and reuses power when driving the scan electrodes SC1 to SCn. Switching element Q55 clamps scan electrode SC1 through scan electrode SCn to voltage Vs, and switching element Q56 clamps scan electrode SC1 through scan electrode SCn to voltage 0 (V). The switching element Q59 is a separation switch, and is provided to prevent a current from flowing backward through a parasitic diode or the like of the switching element constituting the scan electrode driving circuit 43.

  Scan pulse generating circuit 70 includes switching element Q71H1 to switching element Q71Hn, switching element Q71L1 to switching element Q71Ln, and switching element Q72. Then, a scan pulse is generated based on the power source of voltage Va and the power source E71 of voltage (Vc−Va) superimposed on the reference potential of the scan pulse generating circuit 70 (the potential of the node A shown in FIG. 9). Scan pulses are sequentially applied to each of scan electrode SC1 through scan electrode SCn at the timing shown in FIG. Scan pulse generation circuit 70 outputs the output voltage of sustain pulse generation circuit 50 as it is during the sustain operation. That is, the voltage at node A is output to scan electrode SC1 through scan electrode SCn.

  The ramp waveform voltage generation circuit 60 includes a Miller integration circuit 61 and a Miller integration circuit 63, and generates the ramp waveform voltage shown in FIG. Miller integrating circuit 61 includes transistor Q61, capacitor C61, and resistor R61. By applying a constant voltage to input terminal IN61, Miller integrating circuit 61 generates an upward ramp waveform voltage that gradually increases toward voltage Vr. Miller integrating circuit 63 includes transistor Q63, capacitor C63, and resistor R63, and applies a constant voltage to input terminal IN63 to generate a downward ramp waveform voltage that gradually decreases toward voltage Vi. The switching element Q69 is also a separation switch, and is provided to prevent a current from flowing backward through a parasitic diode or the like of the switching element constituting the scan electrode drive circuit 43.

  In addition, these switching elements and transistors can be configured using generally known elements such as MOSFETs and IGBTs. These switching elements and transistors are controlled by timing signals corresponding to the switching elements and transistors generated by the timing generation circuit 45.

  FIG. 11 is a circuit diagram of sustain electrode drive circuit 44 of plasma display device 40 in accordance with the exemplary embodiment of the present invention. Sustain electrode drive circuit 44 includes sustain pulse generation circuit 80 and constant voltage generation circuit 85.

  Sustain pulse generation circuit 80 includes power recovery circuit 81, switching element Q83, and switching element Q84, and generates sustain pulses to be applied to sustain electrode SU1 through sustain electrode SUn. The power recovery circuit 81 recovers and reuses the power when driving the sustain electrodes SU1 to SUn. Switching element Q83 clamps sustain electrode SU1 through sustain electrode SUn to voltage Vs, and switching element Q84 clamps sustain electrode SU1 through sustain electrode SUn to voltage 0 (V).

  Constant voltage generation circuit 85 includes switching element Q86 and switching element Q87, and applies voltage Ve to sustain electrode SU1 through sustain electrode SUn.

  In addition, these switching elements can also be comprised using generally known elements, such as MOSFET and IGBT. These switching elements are also controlled by timing signals corresponding to the respective switching elements generated by the timing generation circuit 45.

  FIG. 12 is a circuit diagram of data electrode drive circuit 42 of plasma display device 40 in accordance with the exemplary embodiment of the present invention. Data electrode drive circuit 42 includes switching element Q91H1 to switching element Q91Hm and switching element Q91L1 to switching element Q91Lm. The voltage 0 (V) is applied to the data electrode Dj by turning on the switching element Q91Lj, and the voltage Vd is applied to the data electrode Dj by turning on the switching element Q91Hj.

  Using such a drive circuit, the drive voltage waveform of the panel shown in FIG. 3 can be generated. However, the drive circuits shown in FIGS. 9 to 11 are examples, and the present invention is not limited to the circuit configurations of these drive circuits.

(Embodiment 2)
Embodiment 2 of the present invention will be described with reference to the drawings. Also in the second embodiment, description will be made assuming that panel 10 similar to that in the first embodiment is driven using the same subfield configuration as in the first embodiment.

  Also in the second embodiment, nonlinear processing is performed in which an image signal having a signal level lower than the signal level corresponding to the gradation threshold is replaced with an image signal having a signal level corresponding to gradation “0”. However, the second embodiment is different from the first embodiment in that the image display area is divided into a plurality of small areas, and nonlinear processing is performed using a gradation threshold value corresponding to each small area. That is, it is detected whether the image displayed in each small area is a black image, the time for which the black image continues for each small area is calculated, and the gradation threshold for each small area is calculated. Is set, and nonlinear processing is performed on the image signal based on the gradation threshold value of each small region.

  FIG. 13 is a diagram showing division of an image display area of panel 10 used in the plasma display device in accordance with the exemplary embodiment of the present invention. In the present embodiment, the image display area of the panel 10 is divided into 135 in the vertical direction and 20 in the horizontal direction, and is divided into a total of 135 × 20 = 2700 small areas. Hereinafter, each small region is indicated by (p, q). Here, 1 ≦ p ≦ 135 and 1 ≦ q ≦ 20. However, the method of dividing the image display area is not limited to the above, and is preferably set according to the discharge characteristics of the panel, the specifications of the plasma display device, and the like.

  FIG. 14 is a circuit block diagram of image signal processing circuit 46 of the plasma display device in accordance with the second exemplary embodiment of the present invention. The same reference numerals are assigned to the same circuit blocks as those in the first embodiment.

  The image signal processing circuit 46 includes a small region black image detection unit 461 (1, 1) to a small region black image detection unit 461 (135, 20), a small region integration unit 462 (1, 1) to a small region integration unit 462 ( 135, 20), a selection unit 463, a gradation threshold setting unit 413, a delay unit 415, a nonlinear processing unit 416, an intermediate gradation processing unit 417, and an image data conversion unit 418, and performs nonlinear processing on the input image signal. At the same time, it is converted into image data indicating light emission / non-light emission of the discharge cells in each of the subfields.

  The small area black image detection unit 461 (p, q) is provided corresponding to the small area (p, q), and detects an image signal in which an image displayed in the small area (p, q) is a black image. Also in the second embodiment, each of the small area black image detection units 461 (p, q) is configured using a comparator. If the lighting rate of the discharge cells in the small region (p, q) predicted from the input image signal of one field is 10% or less, the image displayed in the small region (p, q) in that field is black. Detect as an image.

  The small region integration unit 462 (p, q) is a time Tk (p, q) (hereinafter referred to as “small region black image duration time” when the small region black image detection unit 461 (p, q) continuously detects a black image. Tk (p, q) "is abbreviated). Also in the present embodiment, each of the small area integrating units 462 (p, q) is configured using a counter that operates in a field period. When the small area black image detection unit 461 (p, q) detects a black image, the counter of the small area integration unit 462 (p, q) is counted up, and the small area black image detection unit 461 (p, q) ) Does not detect a black image, the counter of the small area integrating unit 462 (p, q) is reset. As a result, the small region integration unit 462 (p, q) determines the number of fields in which the small region black image detection unit 461 (p, q) continuously detects the black image as the small region black image duration Tk (p, q). ).

  The selection unit 463 is configured to output the small region black image duration Tk (1, 1) to the small region black image duration Tk output from the small region integration unit 462 (1, 1) to the small region integration unit 462 (135, 20). The small area black image duration Tk (p, q) is selected from (135, 20) in accordance with the timing of the small area (p, q) where the input image signal is displayed, and is set as the black image duration Tk. Output. Therefore, unlike the black image duration Tk in the first embodiment, the black image duration Tk output from the selection unit 463 changes with time within one field in accordance with the timing of the image signal.

  Similar to the gradation threshold setting unit 413 of the first embodiment, the gradation threshold setting unit 413 is configured using, for example, a ROM table. Then, the black image duration time Tk selected by the selection unit 463 is input, and a gradation threshold value K (0 ≦ K ≦ 1) is output. The gradation threshold value K to be output is uniquely determined according to the input black image duration Tk. However, since the input black image duration Tk changes with time in one field in accordance with the timing of the image signal, Unlike the first embodiment, the output gradation threshold K also changes with time in one field in accordance with the timing of the image signal.

  Similar to the first embodiment, the delay unit 415 is provided to match the output of the gradation threshold setting unit 413 and the phase of the image signal input to the nonlinear processing unit 416. In this embodiment, the delay unit 415 also converts the image signal. It consists of a field memory that is delayed by one field.

  The nonlinear processing unit 416 replaces an image signal having a signal level lower than the signal level corresponding to the gradation threshold value K with an image signal having a signal level corresponding to gradation “0”, that is, black. However, unlike the first embodiment, the input gradation threshold K changes with time within one field in accordance with the timing of the image signal. Therefore, the non-linear processing unit 416 outputs a signal corresponding to a gradation threshold (hereinafter referred to as “small area gradation threshold K (p, q)”) determined corresponding to the small area black image duration Tk (p, q). An image signal less than the level is replaced with a signal level corresponding to the gradation “0”, that is, a black image signal.

  Here, in the small area (p, q) having a long small area black image duration Tk (p, q), the priming is insufficient and the probability of occurrence of a discharge failure increases. However, in such a small region (p, q), the small region gradation threshold value K (p, q) is also large, so even an image signal displaying a relatively high gradation of “1” or less is forcibly black. Is replaced with the signal level to display. As a result, there is no possibility that a pattern unrelated to the image signal is displayed, and a decrease in image display quality can be suppressed. On the other hand, in the small area (p, q) having a short small area black image duration Tk (p, q), since the priming remains, the small area gradation threshold K (p, q) is also set small, and the image signal To display images faithful to.

  As in the first embodiment, the intermediate gradation processing unit 417 performs a dither process or an error diffusion process on the image signal that has been subjected to the nonlinear process, and displays a pseudo intermediate gradation. Similarly to the first embodiment, the image data conversion unit 418 receives the image signal that has been subjected to the halftone process, and performs “light emission” / non-light emission in each of the subfields for each bit “1” of the digital signal. , “0” is output.

  Since the circuit configuration and operation of scan electrode driving circuit 43, sustain electrode driving circuit 44, and data electrode driving circuit 42 of the plasma display device in the second exemplary embodiment are the same as those in the first exemplary embodiment, detailed description thereof is omitted.

  As described above, in the second embodiment, the image display area is divided into a plurality of small areas, and a predetermined gradation threshold value is set for each corresponding small area based on the time for continuously displaying the black image in each of the small areas. It was set. As a result, non-linear processing corresponding to each small area can be applied to the image signal, so that stable writing operation is performed without using forced initialization operation to suppress black luminance and display quality of low luminance images. Can be further suppressed.

  In the second embodiment, the small area gradation threshold K (p, q) is set based on the small area black image duration Tk (p, q) of the corresponding small area (p, q). However, in addition to the corresponding small area (p, q) and the small area black image duration of the small area adjacent thereto, for example, the small area black image duration Tk (p, q) of the small area (p, q), Small region black image duration of region (p-1, q), small region black image duration of small region (p, q-1) (p, q-1), small region of small region (p, q + 1) The small area gradation threshold K (p, q) may be set based on the black image duration (p, q + 1), the small area black image duration (p + 1, q) of the small area (p + 1, q), and the like. .

  Further, the specific numerical values and the like shown in the first and second embodiments are merely examples, and it is desirable to set them optimally according to the panel characteristics, the specifications of the plasma display device, and the like.

  The present invention is useful as a plasma display device because it can suppress a black luminance by performing a stable writing operation without using a forced initialization operation, and can suppress a decrease in display quality of an image with a low luminance. .

DESCRIPTION OF SYMBOLS 10 Panel 22 Scan electrode 23 Sustain electrode 24 Display electrode pair 32 Data electrode 35 Phosphor layer 40 Plasma display apparatus 41, 46 Image signal processing circuit 42 Data electrode drive circuit 43 Scan electrode drive circuit 44 Sustain electrode drive circuit 45 Timing generation circuit 50 , 80 Sustain pulse generation circuit 51, 81 Power recovery circuit 60 Ramp waveform voltage generation circuit 61, 63 Miller integration circuit 70 Scan pulse generation circuit 85 Constant voltage generation circuit 411 Black image detection unit 412 Integration unit 413 Gradation threshold setting unit 415 Delay 416 Non-linear processing unit 417 Intermediate tone processing unit 418 Image data conversion unit 461 (p, q) Small region black image detection unit 462 (p, q) Small region integration unit 463 Selection unit

Claims (4)

A plasma display apparatus for driving a plasma display panel comprising a plurality of discharge cells each having a scan electrode, a sustain electrode, and a data electrode, comprising a plurality of subfields having an address period, a sustain period, and an erase period. Driving method,
A voltage obtained by subtracting a voltage applied to the data electrode from a low-voltage side voltage of the sustain pulse applied to the scan electrode in the sustain period is set as a first voltage, and a high voltage of the sustain pulse applied to the scan electrode in the sustain period The voltage obtained by subtracting the voltage applied to the data electrode from the side voltage is set as the second voltage, and the low voltage side voltage of the write pulse applied to the data electrode from the low voltage side voltage of the scan pulse applied to the scan electrode in the write period Is a voltage obtained by subtracting the third voltage from the first voltage is equal to or higher than a discharge start voltage using the data electrode as an anode and the scan electrode as a cathode, A voltage obtained by subtracting the third voltage from the second voltage is a discharge start voltage having the data electrode as an anode and the scan electrode as a cathode, and the data electrode as a cathode. The electrode is less than the sum of the discharge start voltage to the anode,
In addition, when the gradation to be displayed without causing the discharge cells to emit light in all subfields is gradation “0”, an image having a signal level less than a predetermined gradation threshold with respect to the input image signal. A method for driving a plasma display device, comprising performing a dithering process or an error diffusion process after performing a nonlinear process for replacing a signal with an image signal corresponding to a gradation "0". When the gradation displayed by causing the discharge cell to emit light in one subfield having the smallest luminance weight is gradation "1", the predetermined gradation threshold is gradation "0" or more and gradation "1" or less. The predetermined gradation threshold value when the time for continuously displaying a black image is long is set to be larger than the predetermined gradation threshold value when the time for continuously displaying a black image is short. The method of driving a plasma display device according to claim 1. The image display area is divided into a plurality of small areas, and the predetermined gradation threshold is set for each corresponding small area based on a time for continuously displaying a black image in each of the small areas. The driving method of the plasma display apparatus according to claim 2. A plasma display panel having a plurality of discharge cells each having a scan electrode, a sustain electrode, and a data electrode, and a plurality of subfields having an address period, a sustain period, and an erase period are used to form one field and drive voltage waveform A driving circuit that generates and applies to each electrode of the plasma display panel, and a plasma display device comprising:
The drive circuit is
A voltage obtained by subtracting a voltage applied to the data electrode from a low-voltage side voltage of the sustain pulse applied to the scan electrode in the sustain period is set as a first voltage, and a high voltage of the sustain pulse applied to the scan electrode in the sustain period The voltage obtained by subtracting the voltage applied to the data electrode from the side voltage is set as the second voltage, and the low voltage side voltage of the write pulse applied to the data electrode from the low voltage side voltage of the scan pulse applied to the scan electrode in the write period Is a voltage obtained by subtracting the third voltage from the first voltage is equal to or higher than a discharge start voltage using the data electrode as an anode and the scan electrode as a cathode, A voltage obtained by subtracting the third voltage from the second voltage is a discharge start voltage having the data electrode as an anode and the scan electrode as a cathode, and the data electrode as a cathode. The electrode generates the drive voltage waveform is less than the sum of the discharge start voltage to the anode,
In addition, when the gradation to be displayed without causing the discharge cells to emit light in all subfields is gradation “0”, an image having a signal level less than a predetermined gradation threshold with respect to the input image signal. A plasma display apparatus, wherein a non-linear process for replacing a signal with an image signal corresponding to a gradation “0” is performed, and then a dither process or an error diffusion process is performed.