JP2012054339A - Semiconductor device for motor control - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce impact of a contact pin on a semiconductor device for motor control.SOLUTION: The semiconductor device for motor control comprises an oscillator circuit 12 included in an offset cancel circuit 104 which removes offset voltage of an output from a hall element 102, a comparator circuit 106 which receives an output signal from the offset cancel circuit 104, and creates and outputs a comparison signal by comparing the output signal with a reference signal, an output circuit 110 which creates and outputs a drive signal for driving a motor, and a test circuit 112 not related to the motor control. An input/output pad P1 of a pulse width modulation signal is formed so as to overlap on any one of the circuit patterns of the oscillator circuit 12, the comparator circuit 106, or the test circuit 112.

Description

  The present invention relates to a motor control semiconductor device that performs drive control of a motor based on an output of a Hall element.

  In recent years, in camera shake correction processing of imaging devices such as digital still cameras and digital video cameras and vibration processing of mobile phones, position detection is performed using Hall elements to detect the position of optical elements such as lenses and vibration elements, 2. Description of the Related Art A motor control semiconductor device that drives a motor based on the output of a Hall element to realize a camera shake correction process and a vibration function is used.

  As shown in the circuit layout diagram of FIG. 5, the motor control semiconductor device 100 includes a Hall element 102, an offset cancel circuit 104, a comparator circuit 106, an output control circuit 108, and an output circuit 110. Further, as shown in FIG. 5, although not directly related to motor control, a test circuit 112 for confirming the operation and characteristics of the motor control semiconductor device 100 may be included.

  Here, as shown in FIG. 6, the offset cancel circuit 104 includes an oscillator circuit 12 including an amplifying element connected to the Hall element 102 and an averaging circuit 14, and an offset component included in the output voltage of the Hall element 102. Provided to cancel. Here, the Hall element 102 is represented by an equivalent circuit in which resistors R1 to R4 are connected.

  The oscillator circuit 12 includes a circuit that generates an oscillation signal used inside the motor control semiconductor device 100. The oscillator circuit 12 includes operational amplifiers 12a and 12b. The operational amplifier 12a amplifies and outputs the voltage input to the non-inverting input terminal (+). The operational amplifier 12b amplifies and outputs the voltage input to the non-inverting input terminal (+).

  The averaging circuit 14 includes switching elements S9 to S19, capacitors C1 to C4, an operational amplifier 14a, and a reference voltage generation circuit 14b. The switching elements S9 to S19 connect any one of the output terminals of the operational amplifiers 12a and 12b, the terminals of the capacitors C1 to C4, and the input terminal of the operational amplifier 14a.

  By turning on the switching element S1 and turning off the switching element S6, the power supply voltage Vcc is applied to the connection point A of the resistors R1 and R2, and connecting the resistors R3 and R4 by turning on the switching element S2 and turning off the switching element S8. Point C is grounded. Further, by turning on the switching element S7 and turning off the switching element S4, the connection point D of the resistors R1 and R4 is connected to the non-inverting input terminal (+) of the operational amplifier 12b, the switching element S5 is turned on, and the switching element S3 is turned off. As a result, the connection point B of the resistors R2 and R3 is connected to the non-inverting input terminal (+) of the operational amplifier 12a. Further, by turning on the switching elements S13 and S14 among the switching elements S9 to S19 and turning off the others, the output of the operational amplifier 12a is connected to the positive terminal of the capacitor C1, and the output of the operational amplifier 12b is connected to the negative terminal of the capacitor C1. The capacitor C1 is charged by the output voltages of the operational amplifiers 12a and 12b.

  Next, by turning on the switching element S6 and turning off the switching element S1, the connection point A of the resistors R1 and R2 is connected to the non-inverting input terminal (+) of the operational amplifier 12a, and the switching element S8 is turned on and the switching element S2 is turned on. By turning off, the connection point C of the resistors R3 and R4 is connected to the non-inverting input terminal (+) of the operational amplifier 12b. Further, the connection point D of the resistors R1 and R4 is grounded by turning on the switching device S4 and turning off the switching device S7, and the connection point B of the resistors R2 and R3 by turning on the switching device S3 and turning off the switching device S5. Is applied with a power supply voltage Vcc. Further, by turning on switching elements S15 and S16 among switching elements S9 to S19 and turning off others, the output of operational amplifier 12a is connected to the negative terminal of capacitor C2, and the output of operational amplifier 12b is connected to the positive terminal of capacitor C2. The capacitor C2 is charged by the output voltages of the operational amplifiers 12a and 12b.

  In this way, the two modes of applying a voltage are switched so as to change the direction of the current flowing through the Hall element 102, and the capacitors C1 and C2 are connected to the four terminals of the Hall element 102 with Hall voltages V1 and V2 in two directions (90 °). Charge each one. The charging voltage V1 is a value obtained by adding the offset voltage Voff to the Hall voltage Vhall in the first mode. That is, the charging voltage V1 = Vhall + Voff. When the current flowing through the Hall element 102 is changed by 90 °, the offset voltage Voff of the Hall element 102 is generated in the reverse direction, so that the charging voltage V2 is a value obtained by subtracting the offset voltage Voff from the Hall voltage Vhall in the second mode. . That is, the charging voltage V2 = Vhall−Voff.

  In the output state, the switching elements S13 to S16 are turned off, and the operational amplifiers 12a and 12b and the capacitors C1 and C2 are cut off. Further, by turning on the switching elements S11, S12, and S19 and turning off the switching element S18, the positive terminals of the capacitors C1 and C2 are commonly connected to one end of the input terminal of the operational amplifier 14a via the capacitor C4. Further, by turning on the switching elements S9 and S10, the negative terminals of the capacitors C1 and C2 are commonly connected to the other end of the input terminal of the operational amplifier 14a. The other end of the operational amplifier 14a is set to Vref generated by the reference voltage generation circuit 14b. The switching element S17 for erasing the charge of the capacitor C3 is also turned off.

  By setting such an output state, the capacitors C1 and C2 are connected in parallel, and the charges stored in the capacitors C1 and C2 are redistributed to the capacitors C1 to C4, and the charging voltages V1 and V2 are averaged. . As a result, the offset value Voff of the output voltage of the Hall element 102 is canceled and output as the output voltage Vout.

  The comparator circuit 106 compares the output signal from the offset cancel circuit 104 with a reference voltage and outputs the comparison result to the output control circuit 108. The output control circuit 108 receives the comparison result from the comparator circuit 106, and generates and outputs a control signal for driving the motor according to the comparison result. For example, the output control circuit 108 outputs a control signal for rotating the motor by a predetermined rotation angle when the comparison result from the comparator circuit 106 is continuously greater than the reference value for a certain number of times. The output circuit 110 transmits a control signal from the output control circuit 108 and generates a motor drive signal corresponding to the control signal. The output circuit 110 receives the control signal from the output control circuit 108, and generates and outputs a drive signal for actually driving the motor. The motor is driven by receiving a drive signal from the output circuit 110.

  Incidentally, as shown in FIG. 6, the offset cancel circuit 104 includes a portion of the oscillator circuit 12 having a small number of capacitor elements and a portion of the averaging circuit 14 including a large number of capacitor elements.

  On the other hand, the motor control semiconductor device 100 may be formed monolithically on a semiconductor substrate and configured as a wafer level package (WLP: Wafer Level Package). In a wafer level package (WLP), an electronic circuit, an insulating layer, and a wiring layer are formed on a semiconductor substrate, and contact pins such as solder balls are provided on the semiconductor substrate in order to perform input / output with respect to the circuit formed on the semiconductor substrate. To place. This makes it possible to mount the motor control semiconductor device 100 on a printed circuit board or the like without connection of bond wires or interposers.

  When such a wafer level package (WLP) is applied, as shown in the pin arrangement diagram of FIG. 7, the Hall element 102 formed on the semiconductor substrate 20, the offset cancel circuit 104, the comparator circuit 106, and the output control circuit 108. The input / output pins P1 to P6 are arranged on the output circuit 110 and the test circuit 112. Pins P1 to P6 are used for a pulse width modulation signal (PWM), an output signal (VOUT1), an output signal (VOUT2), a ground (GND), a mode setting signal of the motor control semiconductor device 100, and a power supply, respectively. For voltage (Vcc).

  Here, as shown in FIG. 7, when the pin P1 for the PWM signal is arranged so as to overlap the portion of the averaging circuit 14 of the offset cancel circuit 104, a large number of capacitor elements included in the averaging circuit 14 become alternating current of the PWM signal. The averaging circuit 14 may not operate correctly due to the influence of components.

  One aspect of the present invention is a motor control semiconductor device that includes a Hall element and performs drive control of a motor in accordance with an output from the Hall element, in an offset cancel circuit that removes an offset voltage of an output from the Hall element. A comparator circuit that receives an output signal from the included oscillator circuit and the offset cancel circuit, compares the output signal with a reference signal, generates and outputs a comparison signal, and generates a drive signal for driving the motor Output circuit, and a test circuit not related to motor control, and one of the circuit pattern of the oscillator circuit, the circuit pattern of the comparator circuit, and the circuit pattern of the test circuit. This is a semiconductor device for motor control in which input / output pads for pulse width modulation signals are formed so as to overlap.

  According to the present invention, it is possible to reduce the influence of the contact pins on the motor control semiconductor device.

FIG. 3 is a layout diagram illustrating a pin arrangement of a motor control semiconductor device according to an embodiment of the present invention. It is sectional drawing which shows the structure of the semiconductor device for motor control of embodiment of this invention. FIG. 3 is a layout diagram illustrating a pin arrangement of a motor control semiconductor device according to an embodiment of the present invention. FIG. 3 is a layout diagram illustrating a pin arrangement of a motor control semiconductor device according to an embodiment of the present invention. FIG. 5 is a layout diagram showing a circuit arrangement of a motor control semiconductor device. It is a figure which shows the structure of an offset cancellation circuit. It is a layout figure which shows the pin arrangement | positioning of the conventional semiconductor device for motor control.

  FIG. 1 is a diagram showing a circuit and pin arrangement of a motor control semiconductor device 200 according to an embodiment of the present invention. Similar to the conventional motor control semiconductor device 100, the motor control semiconductor device 200 includes a Hall element 102, an offset cancel circuit 104, a comparator circuit 106, an output control circuit 108, and an output circuit 110. Further, although not directly related to motor control, a test circuit 112 for confirming the operation and characteristics of the motor control semiconductor device 200 is included.

  Since the functions of the Hall element 102, the offset cancel circuit 104, the comparator circuit 106, the output control circuit 108, the output circuit 110, and the test circuit 112 are the same as those of the conventional motor control semiconductor device 100, description thereof is omitted.

  The motor control semiconductor device 200 in the present embodiment is configured as a wafer level package (WLP). As shown in the sectional view of FIG. 2, the wafer level package (WLP) has a configuration in which contact pins such as solder balls are formed on a semiconductor substrate 20 on which a semiconductor integrated circuit 22 is formed. The semiconductor substrate 20 is covered with an insulating resin 24, and wirings 26 connected to the semiconductor integrated circuit 22 through contact holes opened in the insulating resin 24 are formed. The wiring 26 is extended on the insulating resin 24 to the positions of the contact pins P1 to P6. Further, the wiring 26 is covered with the sealing resin 28, and the contact pins P1 to P6 made of solder balls or the like are electrically connected to the wiring 26 through the contact holes opened at the positions of the contact pins P1 to P6. Formed.

  In the motor control semiconductor device 200 according to the present embodiment, among the pins P1 to P6, the pulse width modulation signal (PWM) pin P1 including the AC component is at least in the circuit pattern of the offset cancel circuit 104. It should not be placed in areas other than on the pattern. That is, the PWM pin P1 is arranged at a position overlapping any of the Hall element 102, the oscillator circuit 12 of the offset cancel circuit 104, the comparator circuit 106, the output control circuit 108, the output circuit 110, and the test circuit 112. Is preferred. Here, in consideration of the influence on the Hall element 102, it is preferable to avoid placing the PWM pin P1 on the circuit pattern of the Hall element 102, and an output signal is provided in the vicinity of the output control circuit 108 and the output circuit 110. It is preferable to arrange pins P2 and P3 for (VOUT1, VOUT2). Based on these considerations, the PWM pin P1 is on the circuit pattern of the oscillator circuit 12 included in the offset cancel circuit 104 as shown in FIG. 1, on the circuit pattern of the comparator circuit 106 as shown in FIG. As shown in FIG. 4, it is more preferable to arrange the test circuit 112 on the circuit pattern. In particular, when arranged on the circuit pattern of the test circuit 112, the test circuit 112 itself is not used during operation even if there is an influence of the AC component of the PWM signal. The possibility that 14 will not operate correctly can be reduced more reliably. 1, 3 and 4, the arrangements other than the PWM pin P1 and the output signals (VOUT1, VOUT2) pins P2 and P3 may be appropriately switched.

  As described above, by arranging the PWM pin P1, the influence of the AC component of the PWM signal on the capacitor elements included in the averaging circuit 14 of the offset cancel circuit 104 is reduced, and the averaging circuit 14 is accurately set. The possibility of not operating can be reduced. In particular, the offset cancel circuit 104, the comparator circuit 106, the output circuit 110, and the test circuit 112 are arranged so as to surround the Hall element 102, and the PWM pin P1 is formed on the circuit pattern of the test circuit 112, and the pin P2 -P5 is formed on a circuit pattern other than the test circuit 112, and the influence of the PWM signal on the averaging circuit 14 is effectively suppressed while suppressing the increase in size (increase in area) of the motor control semiconductor device 200. Can be reduced.

  In the above embodiment, the offset cancel circuit 104 includes the oscillator circuit 12. However, since the oscillator circuit 12 can be used to perform drive control of the motor, You may provide in a circuit area. In the above embodiment, an example of the PWM pin P1 itself is shown. However, the wiring 26 (see FIG. 2) connected to the PWM pin P1 is connected to the oscillator circuit 12 included in the offset cancel circuit 104. Even when the circuit pattern is arranged on the circuit pattern of the comparator circuit 106 or the circuit pattern of the test circuit 112, the above-described effects can be obtained for the same reason.

  12 oscillator circuit, 12a, 12b operational amplifier, 14 averaging circuit, 14a operational amplifier, 14b reference voltage generation circuit, 20 semiconductor substrate, 22 semiconductor integrated circuit, 24 insulating resin, 26 wiring, 28 sealing resin, 100, 200 for motor control Semiconductor device, 102 Hall element, 104 Offset cancel circuit, 106 Comparator circuit, 108 Output control circuit, 110 Output circuit, 112 Test circuit

Claims (3)

A semiconductor device for motor control that includes a Hall element and performs drive control of a motor according to an output from the Hall element,
An oscillator circuit included in an offset cancel circuit that removes an offset voltage of the output from the Hall element, and an output signal from the offset cancel circuit, and compares the output signal with a reference signal to generate a comparison signal A comparator circuit for outputting, an output circuit for generating and outputting a drive signal for driving the motor, and a test circuit not related to the control of the motor,
An input / output pad for a pulse width modulation signal is formed so as to overlap any one of the circuit pattern of the oscillator circuit, the circuit pattern of the comparator circuit, and the circuit pattern of the test circuit. A semiconductor device for motor control. The motor control semiconductor device according to claim 1,
The offset cancel circuit, the comparator circuit, the output circuit, and the test circuit are arranged on the substrate so as to surround the Hall element formed on the substrate,
The input / output pad of the pulse width modulation signal is formed on a circuit pattern of the test circuit,
A motor control semiconductor device, wherein a grounding pad, a power supply voltage pad, a mode setting signal pad, and an output signal pad are formed on a circuit pattern other than the test circuit. . A motor control semiconductor device according to claim 1 or 2,
A wafer level package in which an input / output pad for the pulse width modulation signal is formed on a semiconductor wafer on which the Hall element, the offset cancel circuit, the comparator circuit, and the test circuit are formed via a sealing resin is applied. The semiconductor device for motor control characterized by the above-mentioned.

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