JP2011222101A - Semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory device that can suppress rising of a writing or reading voltage by making threshold voltage distribution of a memory cell narrower than conventional distribution without changing ECC correction capability.SOLUTION: The semiconductor memory device comprises word lines, bit lines, memory cells in which each gate is connected to any one of the word lines, a word line driver that drives voltages of the word lines, and a sense amplifier that detects data in the memory cells through the bit lines. The memory cells are connected in series between the bit line and a source to constitute a cell string. At the time of a verifying operation in a certain writing loop in a writing stage which repeats multiple times the writing loop consisting of a writing operation to write data into a selected memory cell in the cell string and a verifying operation to verify that data has been written into the selected memory cell, the word line driver increases a voltage at a time of verification of any one of non-selected word lines which are connected to non-selected memory cells other than the selected memory cell in the cell string among the word lines.

Description

  Embodiments described herein relate generally to a semiconductor memory device.

  Nonvolatile semiconductor memory devices such as NAND flash memories have been increasingly miniaturized in order to increase memory capacity. As miniaturization progresses, the interval between adjacent memory cells becomes narrower, so that interference between memory cells (hereinafter referred to as proximity effect) cannot be ignored. As a result, the width of the threshold voltage distribution of the memory cell into which data is written becomes wide.

  On the other hand, it is preferable to reduce the voltage applied at the time of writing and reading as the memory becomes finer. However, if the width of the threshold voltage distribution of the memory cell becomes wider, the interval between the data (voltage difference) must be increased, so that the voltage applied at the time of writing and reading becomes rather high. Therefore, the difference between the threshold voltage of the memory cell after data writing and the threshold voltage of the memory cell after data erasing becomes large. As a result, interference (proximity effect) between adjacent memory cells is increased, and the width of the threshold voltage distribution is further increased.

  Even if the width of the threshold voltage distribution is widened, it is possible to suppress an increase in write or read voltage by using ECC (Error Correcting Code). However, ECC with a high correction capability requires many redundant columns, and the number of gates of the ECC circuit increases. This increases the memory chip size and increases the cost.

JP-A-5-144277 JP 2009-59460 A JP 2009-37720 A

  Provided is a semiconductor memory device capable of suppressing an increase in write or read voltage by making a threshold voltage distribution of memory cells narrower than before without changing ECC correction capability.

A semiconductor memory device according to an embodiment of the present invention includes a plurality of word lines, a plurality of bit lines, a plurality of memory cells whose gates are connected to any one of the word lines, and the plurality of word lines. A word line driver that drives a voltage; and a sense amplifier that detects data of the memory cell via the plurality of bit lines;
A plurality of the memory cells are connected in series between the bit line and the source to form a cell string,
In a certain write loop in a write stage, a write loop consisting of a write operation for writing data to a selected memory cell in the cell string and a verify operation for verifying that data has been written to the selected memory cell is repeated a plurality of times. At the time of verify operation, the word line driver increases the voltage at the time of verifying any non-selected word line connected to non-selected memory cells other than the selected memory cell in the cell string. It is characterized by making it.

1 is a block diagram showing a configuration of a NAND flash memory according to a first embodiment of the present invention. The graph which expressed typical data write-in operation as a comparative example by transition of threshold voltage distribution of a memory cell. FIG. 3 is a conceptual diagram showing a verify voltage applied to a word line of a certain NAND string NS of the NAND flash memory according to the first embodiment and a gate of a selection transistor. 6 is a graph showing a transition of a voltage of a word line in a certain writing stage according to the first embodiment. 6 is a graph representing a data write operation (program operation) according to the first embodiment as a transition of a threshold voltage distribution of a memory cell. The conceptual diagram which shows the verify voltage applied to the word line of a certain NAND string NS of the NAND type flash memory according to 2nd Embodiment, and the gate of a selection transistor. The graph which shows transition of the voltage of the word line in a certain write stage according to a 2nd embodiment. The conceptual diagram which shows the verify voltage applied to the word line of a certain NAND string NS of the NAND type flash memory according to 3rd Embodiment, and the gate of a selection transistor. The graph which shows transition of the voltage of the word line in a certain write stage according to a 3rd embodiment. The conceptual diagram which shows the verify voltage applied to the word line of a certain NAND string NS of the NAND type flash memory according to 4th Embodiment, and the gate of a selection transistor. The graph which shows transition of the voltage of the word line in a certain write stage according to 4th Embodiment. 10 is a graph representing a data write operation (program operation) according to the fifth embodiment as a transition of a threshold voltage distribution of a memory cell. The graph which shows transition of the voltage of the selection word line in a certain write stage according to 5th Embodiment. The graph which shows threshold voltage distribution when 3 bit data is written in the memory cell MC. The conceptual diagram which shows the verify voltage applied to the word line of NAND string NS by the modification of 1st Embodiment, and the gate of a selection transistor.

  Embodiments according to the present invention will be described below with reference to the drawings. This embodiment does not limit the present invention.

(First embodiment)
FIG. 1 is a block diagram showing a configuration of a NAND flash memory according to the first embodiment of the present invention. In the memory cell array 11, a plurality of memory cells are two-dimensionally arranged in a matrix. The gate of the memory cell is connected to the word line, and the source or drain of the memory cell is connected to the bit line. The plurality of word lines are wired so as to cross each other in the row direction and the bit lines cross each other in the column direction. A sense amplifier 12 is disposed at one end of the memory cell array 11 in the bit line direction. A sense amplifier 12 is also arranged at the other end of the memory cell array 11 opposite to one end in the bit line direction. The sense amplifier 12 is connected to the bit line, and detects data stored in the memory cell by detecting a cell current flowing through the bit line in the memory cell connected to the selected word line. At both ends of the memory cell array 11 in the word line direction, a row decoder 13 and a word line driver 21 are arranged. The word line driver 21 is connected to the word line and is configured to apply a voltage to the word line when data is written to the memory cell.

  In a NAND flash memory, a plurality of memory cells are connected in series to form a NAND string. One end of the NAND string is connected to the bit line BL via a selection transistor, and the other end is connected to the source S via a selection transistor. Therefore, the memory cell is connected to the bit line BL via another memory cell interposed between the memory cell and the bit line BL. An interval between adjacent memory cells in the NAND string is, for example, 30 nm or less.

  Data exchange between the sense amplifier 12 and the external input / output terminal I / O is performed via the data bus 14 and the I / O buffer 15.

  Various external control signals such as a chip enable signal / CE, an address latch enable signal ALE, a command latch enable signal CLE, a write enable signal / WE, and a read enable signal / RE are input to the controller 16. Based on these control signals, the controller 16 identifies the address Add and the command Com supplied from the input / output terminal I / O. Then, the controller 16 transfers the address Add to the row decoder 13 and the column decoder 18 via the address register 17. Further, the controller 16 decodes the command Com. The sense amplifier 12 is configured to apply a voltage to the bit line according to the column address decoded by the column decoder 18. The word line driver 21 is configured to apply a voltage to the word line according to the row address decoded by the row decoder 13.

  The controller 16 performs sequence control of data reading, data writing, and erasing in accordance with an external control signal and a command. The internal voltage generation circuit 19 is provided to generate an internal voltage (for example, a voltage boosted from the power supply voltage) necessary for each operation. The internal voltage generation circuit 19 is also controlled by the controller 16 and performs a boosting operation to generate a necessary voltage.

  2A to 2D are graphs representing a typical data write operation (program operation) as a comparative example by transition of threshold voltage distribution of memory cells. The horizontal axis of the graph is the threshold voltage of the memory cell. The vertical axis of the graph is the number of memory cells. FIG. 2A shows an erased state distribution De, and all the memory cells are in an erased state. 2A to 2D show a write stage for writing data to a selected memory cell in each column connected to a certain selected word line.

  A memory cell MC of the NAND flash memory includes a floating gate FG and a control gate CG as shown in FIG. The control gate CG is connected to the word line WL, and the word line driver 21 applies a voltage to the control gate CG via the word line WL. As a result, the threshold voltage of the memory cell MC changes by injecting charges (for example, electrons) into the floating gate FG or by extracting charges from the floating gate FG. For example, if all the memory cells MC are composed of N-type FETs (Field-Effect Transistors), the threshold voltage is increased by injecting electrons into the floating gate FG. Conversely, the threshold voltage is lowered by extracting electrons from the floating gate FG. Here, a state where the threshold voltage of the memory cell MC is high is referred to as data “0”, and a state where the threshold voltage of the memory cell MC is low is referred to as data “1”. That is, the erase state shown in FIG. 2A shows data “1”, and FIGS. 2A to 2D show memory cells MC storing data “1” (hereinafter referred to as “1” cells). The operation of writing data “0” to any one of the above is also shown.

  The NAND flash memory writes data to the memory cell MC by repeating a write loop including a write operation for writing data to the selected memory cell and a verify operation for verifying that the data has been written to the selected memory cell a plurality of times. . For example, FIGS. 2A to 2D may each be referred to as a threshold voltage distribution indicating a result of executing a write loop. Hereinafter, a series of write sequences including a plurality of write loops is referred to as a write stage.

  The selected memory cell that has reached a predetermined threshold voltage in one write verify operation is disconnected from the bit line by the select transistors Tsel and Tsels (see FIG. 3) in the next write operation, and writing is not executed. The selected memory cell that has not reached the predetermined threshold voltage in the verify operation is also written in the next write operation.

  FIG. 2B shows the threshold voltage distribution of the memory cell after executing the first write loop. Dp1 indicates the threshold voltage distribution of all the memory cells to which data has been written. Among the memory cells having the distribution Dp1, the distribution Dpa1 indicates a memory cell having a relatively high threshold voltage, that is, a memory cell having a relatively high writing speed. Among the memory cells having the distribution Dp1, the distribution Dpb1 indicates a memory cell having a relatively low threshold voltage, that is, a memory cell having a relatively low writing speed.

  A verify operation is performed after each write operation. VL indicates a verify level. When the threshold voltage of the selected memory cell reaches the verify level VL, it is considered that data is written in the selected memory cell. That is, it is determined that the selected memory cell has passed (passed) verification. Therefore, subsequent writing in the writing stage is not executed for the selected memory cell.

  On the other hand, when the threshold voltage of the selected memory cell is lower than the verify level VL, it is considered that data has not yet been written in the selected memory cell. That is, it is determined that the selected memory cell has failed verify. Therefore, the selected memory cell is further written in the next write loop.

  FIG. 2C shows the threshold voltage distribution of the memory cell after the second write loop is executed. Dp2 represents the threshold voltage distribution of all the memory cells that have been written for the second time. Among the memory cells having the distribution Dp2, the distribution Dpa2 indicates a memory cell having a relatively high threshold voltage, that is, a memory cell having a relatively high writing speed. Among the memory cells having the distribution Dp2, the distribution Dpb2 indicates a memory cell having a relatively low threshold voltage, that is, a memory cell having a relatively low writing speed. Generally, the memory cells belonging to the distribution Dpa1 shift to the distribution Dpa2 by the second writing, and the memory cells belonging to the distribution Dpb1 shift to the distribution Dpb2 by the second writing.

  At the time of the second writing, the threshold voltages of most memory cells belonging to the distribution Dpa2 having a high writing speed reach the verify level VL. The threshold voltages of most memory cells belonging to the distribution Dpb2 whose write speed is slow have not yet reached the verify level VL. A memory cell that has reached the verify level VL is considered to have been written, and is not subject to the next write loop. Therefore, hereinafter, a selected memory cell in a column for which writing has been completed is referred to as a writing completed memory cell, and a selected memory cell in a column for which writing has not yet been completed is referred to as a writing incomplete memory cell.

  Since the NAND string including the write completion memory cell is disconnected from the bit line BL and the source S, the body region (channel portion) of the write completion memory cell is in an electrically floating state.

  FIG. 2D shows the threshold voltage distribution of the memory cell after the third write loop is executed. Distribution Dp3 shows the threshold voltage distribution of all the memory cells that have been written for the third time. Among the memory cells having the distribution Dp3, the distribution Dpa3 indicates a memory cell having a relatively high threshold voltage, that is, a memory cell having a relatively high writing speed. Among the memory cells having the distribution Dp3, the distribution Dpb3 indicates a memory cell having a relatively low threshold voltage, that is, a memory cell having a relatively low writing speed. Generally, the memory cells belonging to the distribution Dpa2 in FIG. 2C shift to the distribution Dpa3 by the third writing, and the memory cells belonging to the distribution Dpb2 shift to the distribution Dpb3 by the third writing.

  The NAND string including the write completion memory cell shares the word line WL with the NAND string including the write incomplete memory cell. For this reason, even after the completion of programming, the gate voltage is applied to the gate of the programming completed memory cell. At this time, the potential of the body region of the write-completed memory cell is boosted according to the gate voltage by capacitive coupling with the control gate CG, and writing hardly occurs. However, since the potential of the body region does not transition to a voltage equal to the gate voltage, a certain electric field is applied to the floating gate FG. Due to this electric field, a small amount of charge is quantum-injected into the write completion memory cell. That is, the write completion memory cells belonging to the distribution Dpa2 in FIG. 2C are prohibited from being written thereafter, but the threshold voltage of the write completion memory cell is as shown in the distribution Dpa3 in FIG. It rises slightly due to the writing loop after the writing is completed.

  Therefore, the threshold voltage distribution Dpa3 having a relatively high threshold voltage in the threshold voltage distribution Dp3 in FIG. 2D is composed of memory cells having a high write speed and having been written in a small write loop. The distribution Dpb3 having a relatively low threshold voltage is composed of memory cells having a low write speed and having been written in many write loops.

   As described above, the threshold voltage of the write completion memory cell gradually increases due to the write loop after the write is completed, so that the threshold voltage distribution Dp3 is widened at the end of the write stage in which the writing of all the memory cells is completed.

  Therefore, in the NAND flash memory according to the present embodiment, the word line driver 21 uses the voltage VREAD at the time of verifying one of the word lines connected to the non-selected memory cell in the NAND string at a certain point in the write stage. To raise.

  FIG. 3 shows the verification applied to the word lines WL0 to WLn, WLDS, WLDD of the NAND string NS of the NAND flash memory according to the first embodiment and the gates SGS, SGD of the selection transistors Tsels, Tseld. It is a conceptual diagram which shows a voltage. Note that n is an integer. As shown in FIG. 3, the NAND string NS as a cell string includes a plurality of memory cells MC connected in series between a bit line BL and a source S. One end of the NAND string NS is connected to the bit line BL via the selection transistor Tseld, and the other end is connected to the source S via the selection transistor Tsels.

  Each memory cell MC includes a source layer, a drain layer, a floating gate FG, and a control gate CG. Two adjacent memory cells MC in the NAND string NS share a source layer or a drain layer. Thus, the plurality of memory cells MC are connected in series in the NAND string NS.

  In FIG. 3, a word line WLk (0 ≦ k ≦ n) functions as a selected word line. When 1 ≦ k ≦ n−1, the word lines WL0 to WLk−1 and WLk + 1 to WLn are unselected word lines. When k = 0, WL1 to WLn function as non-selected word lines, and when k = n, WL0 to WLn-1 function as non-selected word lines. The word line driver 21 applies the same voltage as the other unselected word lines WL0 to WLk−1 and WLk + 1 to WLn to the word lines WLDS and WLDD closest to the selection transistors Tsels and Tseld. The memory cells connected to the word lines WL0 to WLn are indicated as MC0 to MCn, respectively. Memory cells connected to the word lines WLDS and WLDD are denoted as MCds and MCdd. Here, the word lines WLDS and WLDS are dummy word lines, and the cells MCds and MCdd are dummy cells that are not used for data storage. In this embodiment, a NAND string having dummy word lines WLDS and WLDD is taken as an example. However, this embodiment can also be applied to a NAND string having no dummy word line. In this case, the same effect as this embodiment can be obtained.

  After writing data in each write loop, the memory performs a verify operation. In the verify operation, the word line driver 21 applies the verify read voltage VREAD to the unselected word lines WL0 to WLk−1, WLk + 1 to WLn, WLDS, and WLDD. The word line driver 21 applies a gate voltage VCG lower than VREAD to the selected word line WLk. Further, the word line driver 21 sets the gate voltages of the selection transistors Tsels and Tseld to VSG. The gate voltage VSG is lower than the verify read voltage VREAD and is a voltage that brings the selection transistors Tsels and Tseld into a conductive state. As a result, the non-selected memory cells MC0 to MCk−1, MCk + 1 to MCn, MCds, and MCdd are turned on, and the select transistors Tsels and Tseld are turned on. As a result, the selected memory cell MCk is connected between the bit line BL and the source S. By applying a voltage to the selected memory cell MCk via the bit line BL, the sense amplifier S / A can detect data in the selected memory cell MCk.

  4A and 4B are graphs showing the transition of the voltage of the word line in a certain write stage according to the first embodiment. FIG. 4A shows the voltage of the selected word line WLk. FIG. 4B shows voltages of unselected word lines WL0 to WLk−1, WLk + 1 to WLn, WLDD, and WLDS.

  First, the operation of the selected word line WLk shown in FIG. The word line driver 21 steps up the program voltages VPGM (1) to VPGM (M) of the selected word line WLk in the write operation in each of the write loops Loop1 to LoopM. Thus, the program voltage increases as the number of write loops increases. That is, even in a memory cell that did not pass verification in the initial write loop of the write stage, data (charge) is sufficiently written in the subsequent write loop by passing up the program voltage, and passes verification. be able to.

  In the verify operation in each of the write loops Loop1 to LoopM, the voltage applied to the selected word line WLk is VCG and is constant. That is, in each of the write loops Loop1 to LoopM, the gate voltage VCG of the selected memory cell MCk in the verify operation is constant.

  On the other hand, the voltages of the unselected word lines WL0 to WLk−1, WLk + 1 to WLn, WLDD, and WLDS shown in FIG. 4B are VPASS and constant in the write operations of the write loops Loop1 to LoopM. However, in the verify operation of each of the write loops Loop1 to LoopM, the voltages of the unselected word lines WL0 to WLk−1, WLk + 1 to WLn, WLDD, and WLDS are VREAD (1) or VREAD (2). Here, VREAD (1) is a voltage lower than VREAD (2). In the initial write loop of the write stage, the word line driver 21 applies a relatively low verify read voltage VREAD (1) to the unselected word lines WL0 to WLk−1, WLk + 1 to WLn, WLDD, and WLDS. At some point in the write stage, the word line driver 21 applies a relatively high verify read voltage VREAD (2) to the unselected word lines WL0 to WLk−1, WLk + 1 to WLn, WLDD, and WLDS.

  The reason for changing the verify read voltage applied to the unselected word lines in this way will be described below with reference to FIGS. 5 (A) to 5 (C). FIG. 5A to FIG. 5C are graphs representing the data write operation (program operation) according to the present embodiment as transitions of the threshold voltage distribution of the memory cells. Since the threshold voltage distribution in the erased state is the same as that in FIG. 2A, the illustration thereof is omitted.

  When the verify read voltage is constant in each write loop as in the prior art, as described with reference to FIGS. 2C and 2D, the threshold voltage of the write completion memory cell is Gradually increases by the write loop, and the threshold voltage distribution Dp3 is widened at the end of the write stage.

  On the other hand, in the memory according to the present embodiment, the low verify read voltage VREAD (1) is used for the non-selected word line at the initial stage of the write stage. Although the non-selected memory cells MC0 to MCk−1, MCk + 1 to MCn, MCDD, and MCDS are turned on by applying the refine read voltage VREAD (1) to the gates, their on-resistance is VREAD (2). High compared. For this reason, the resistance between the bit line BL and the source S is apparently increased. That is, when viewed from the sense amplifier 12, the resistance of the selected memory cell MCk looks high. In other words, the verify level VL is apparently lowered. As a result, the selected memory cell is likely to pass the verify operation. The apparent verify level at this time is displayed as VL0 in FIG.

  The selected memory cell with fast writing belonging to the distribution Dpai (i = 1 to 3) in FIGS. 5A to 5C passes the verification with a small number of writings. At this time, as shown in FIG. 5B, some of the selected memory cells with slow writing belonging to the distribution Dpbi also pass verification with a small number of writings, but many of the selected memory cells belonging to the distribution Dpbi are still verified. Has not passed.

  The word line driver 21 raises the verify read voltage to a relatively high VREAD (2) at some point during the write stage. As a result, the on-resistances of the unselected memory cells MC0 to MCk−1, MCk + 1 to MCn, MCDD, and MCDS are lowered. For this reason, the resistance between the bit line BL and the source S is apparently lowered. That is, when viewed from the sense amplifier 12, the resistance of the selected memory cell MCk looks relatively low. In other words, the verify level is apparently increased. As a result, the selected memory cell is difficult to pass in the verify operation. The apparent verify level at this time is displayed as VL1 in FIG.

  As shown in FIG. 5B, many of the fast-writing selected memory cells belonging to the distribution Dpa2 have already passed the verification in the write loop using the verify read voltage VREAD (1). These selected memory cells that are written quickly pass the verification with a low verification level VL0. Accordingly, the distribution Dpa2 in FIG. 5B is shifted to a lower threshold voltage side as compared with the distribution Dpa2 in FIG. 2C of the comparative example. Thus, even if the apparent verify level is changed, the selected memory cell that has once passed verification is prohibited from being written in the subsequent write loop. On the other hand, as described above, even if writing is prohibited, the threshold voltage of the selected memory cell in which writing has been completed slightly increases by driving the word line WLk in the subsequent writing loop. In other words, in the present embodiment, the threshold voltage of the selected memory cell with fast writing that has passed verification is originally shifted to the low voltage side. Can be substantially canceled. Here, in order to cancel the increase in the threshold voltage after the completion of writing, the difference between the verify read voltages VL0 and VL1 is preferably substantially equal to the shift amount of the threshold voltage by the writing loop after the writing is completed.

  Further, when the verify read voltage is stepped up to VREAD (2) at a certain point in the write stage, as shown in FIG. 5C, the selected write memory cell belonging to the distribution Dpb3 has the verify read voltage VREAD. Verify is performed in the write loop using (2). These selected memory cells that are written slowly apparently pass verify when the high verify level VL1 is exceeded. As a result, an overlapping region between the threshold voltage distribution Dpb3 of the selected memory cell with slow writing and the threshold voltage distribution Dpa3 of the selected memory cell with fast writing becomes large, and the width of the entire threshold voltage distribution Dp3 becomes narrow.

  As described above, the NAND flash memory according to the present embodiment apparently lowers the verify level in the initial write loop of the write stage, and raises the verify level in the write loop in the middle of the write stage. The threshold voltage distribution of the memory cell can be narrowed. By narrowing the threshold voltage distribution of the memory cell after writing, this embodiment can suppress an increase in the writing voltage or the reading voltage without changing the ECC correction capability. Therefore, this embodiment can suppress an increase in chip size.

  With the recent miniaturization of memory cells and increase in memory capacity, the number of memory cells MC included in each NAND string NS is increasing. In such a situation, the on-resistance of the entire NAND string NS has more unselected memory cells MC0 to MCk−1, MCk + 1 to MCn, MCDD, MCV, than the verify voltage VCG applied to the single selected memory cell MCk. It can vary greatly depending on the verify voltage VREAD applied to the MCDS. Therefore, the threshold voltage distribution Dp3 can be effectively narrowed by changing the verify voltage VREAD in the middle of the write stage.

  The voltage difference ΔVREAD between VREAD (1) and VREAD (2) depends on the gate interval between adjacent memory cells MC. For example, in the generation in which the distance between adjacent gates is about 30 nm, the voltage difference ΔVREAD is preferably 0.4V to 0.6V. In the generation in which the distance between adjacent gates is about 25 nm, the voltage difference ΔVREAD is preferably 0.3V to 0.4V. In the generation in which the distance between adjacent gates is about 20 nm, the voltage difference ΔVREAD is preferably 0.2V to 0.3V.

  The write loop Loopj (1 ≦ j ≦ M) for changing the verify read voltage VREAD is preferably an intermediate write loop of all the write loops. That is, j is preferably an integer around M / 2. However, when the data writing stage and erasing are repeated in the memory cell, charges trapped in the tunnel insulating film between the floating gate FG and the body region are generated, so that the number of write loops in the write stage tends to decrease. There is. Considering this charge trap, it is preferable that the write loop Loopj for changing the verify read voltage VREAD is a write loop slightly before the middle of all the write loops. That is, j is preferably an integer smaller than M / 2.

  In the present embodiment, the word line driver 21 steps up the verify voltage VREAD only once during the write stage. However, the number of times that the refinement voltage VREAD is changed in each write stage is not limited. The word line driver 21 may increase the verify voltage VREAD two or more times during the write stage. For example, the word line driver 21 may increase the verify voltage VREAD in each of the write loops Loop1 to LoopM. In this case, it is necessary to finely set the verify voltage VREAD in multiple stages, but the width of the threshold voltage distribution Dp3 can be narrowed more effectively and the variation in threshold voltage can be further suppressed. The step-up width of the verify read voltage VREAD is preferably equal in each write loop. For example, if the verify read voltage that rises in a certain write stage is ΔVREAD, the step-up width of the verify read voltage VREAD in each of the write loops Loop1 to LoopM may be ΔVREAD / (M−1).

(Second Embodiment)
FIG. 6 shows word lines WL0 to WLn, WLDS, and WLDD of a NAND string NS of the NAND flash memory according to the second embodiment of the present invention, and gates SGS and SGD of selection transistors Tsels and Tseld. It is a conceptual diagram which shows the verify voltage applied.

  In the first embodiment, the word line driver 21 applies the same verify read voltage VREAD to unselected word lines WL0 to WLk-1, WLk + 1 to WLn, WLDS, and WLDD other than the selected word line WLk. On the other hand, in the second embodiment, the word line driver 21 applies the verify read voltage VREADK of the unselected word lines WLk−1 and WLk + 1 adjacent to both sides of the selected word line WLk in the NAND string NS to other non-selected word lines WLk + 1. This is different from the verify read voltage VREAD of the selected word lines WL0 to WLk-2 and WLk + 2 to WLn.

  The proximity effect increases as the spacing between adjacent memory cells decreases. In the verify read operation, the memory cells MCk−1 and MCk + 1 connected to the word lines WLk−1 and WLk + 1 adjacent to the selected word line WLk need to be in a conductive state.

  However, when the interval between adjacent word lines is reduced, the capacitance between the word lines or the capacitance between the word line and the floating gate FG corresponding to the word line adjacent to the word line is increased (hereinafter referred to as this). The phenomenon is also called proximity effect). Therefore, the floating gates FG of the memory cells MCk−1 and MCk + 1 are easily affected by the voltage of the selected word line WLk due to the proximity effect. In the verify read, a voltage VCG lower than VREAD is applied to the selected word line WLk. For this reason, the voltage of the floating gate FG of the non-selected memory cells MCk−1 and MCk + 1 is less likely to rise than the voltage of the floating gate FG of the other non-selected memory cells MC0 to MCk−2 and MCk + 2 to MCn. That is, the threshold voltages of the unselected memory cells MCk−1 and MCk + 1 are apparently higher than the threshold voltages of the other unselected memory cells MC0 to MCk−2 and MCk + 2 to MCn. As a result, the unselected memory cells MCk-1 and MCk + 1 are unlikely to become conductive.

  Therefore, the verify read voltage VREADK of the word lines WLk−1 and WLk + 1 adjacent to the selected word line WLk is set higher than the verify read voltages VREAD of the other non-selected word lines WL0 to WLk−2 and WLk + 2 to WLn. Yes. As a result, the influence of the voltage VCG of the selected word line WLk on the word lines WLk−1 and WLk + 1 is canceled as much as possible.

  Furthermore, in the second embodiment, the word line driver 21 increases only the verify read voltage VREADK of the unselected word lines WLk−1 and WLk + 1 adjacent to both sides of the selected word line WLk in the middle of the write stage. The word line driver 21 maintains the verify read voltage VREAD of the unselected word lines WL0 to WLk-2, WLk + 2 to WLn, WLDD, and WLDS other than the unselected word lines WLk−1 and WLk + 1. Other operations in the second embodiment may be the same as the corresponding operations in the first embodiment. The configuration of the second embodiment may be the same as the configuration of the first embodiment.

  FIG. 7A to FIG. 7C are graphs showing the transition of the voltage of the word line in a certain write stage according to the second embodiment.

  As shown in FIG. 7A, verify read voltages VREAD of unselected word lines WL0 to WLk-2, WLk + 2 to WLn, WLDD and WLDS not adjacent to the selected word line WLk are set to all write loops Loop1 to Loop1 in the write stage. Constant in LoopM.

  As shown in FIG. 7B, the verify read voltage of the unselected word lines WLk−1 and WLk + 1 adjacent to the selected word line WLk is changed from VREADK (1) to VREADK (2) in the write loop Loopj in the middle of the write stage. It has changed.

  As shown in FIG. 7C, the verify read voltage VCG of the selected word line WLk is constant in all write loops Loop1 to LoopM in the write stage.

  Usually, the unselected word lines WLk−1 and WLk + 1 adjacent to the selected word line WLk have the greatest influence on the selected memory cell MCk among the unselected word lines due to the proximity effect. That is, the threshold voltage of the selected memory cell MCk can be controlled to some extent by the voltages of the unselected word lines WLk−1 and WLk + 1. Therefore, the width of the threshold voltage distribution Dp3 shown in FIG. 5C can be effectively narrowed only by changing the verify read voltage of only the unselected word lines WLk−1 and WLk + 1. The second embodiment can further obtain other effects of the first embodiment. In the second embodiment, it is sufficient to raise only the two non-selected word lines WLk−1 and WLk + 1. Therefore, the power consumption can be reduced as compared with the first embodiment.

  In the second embodiment, only the verify read voltage VREADK of the unselected word line WLk + 1 or WLk−1 adjacent to one side of the selected word line WLk may be stepped up. Even in this case, the effect of the second embodiment is not lost.

  The voltage difference ΔVREADK between the verify read voltage VREADK (1) and the verify read voltage VREADK (2) may be approximately the same as the voltage difference ΔVREAD in the first embodiment.

  In addition, the write loop Loopj that steps up the verify read voltage of the unselected word lines WLk−1 and WLk + 1 takes into account the tendency that the number of write loops in the write stage decreases with time, as in the first embodiment. Thus, it is preferable that the write loop be in the middle of all the write loops. That is, j is preferably an integer smaller than M / 2.

  The number of times to step up the verify read voltage of the unselected word lines WLk−1 and WLk + 1 is not limited as in the first embodiment. The word line driver 21 may increase the verify voltage VREADK in each of the write loops Loop1 to LoopM. At this time, the step-up width of the verify read voltage VREADK in each of the write loops Loop1 to LoopM may be ΔVREADK / (M−1).

(Third embodiment)
FIG. 8 shows word lines WL0 to WLn, WLDS and WLDD of a NAND string NS and gates SGS and SGD of selection transistors Tsels and Tseld in a NAND flash memory according to the third embodiment of the present invention. It is a conceptual diagram which shows the verify voltage applied.

  In the second embodiment, the word line driver 21 increases only the verify read voltage VREADK of unselected word lines WLk−1 and WLk + 1 adjacent to both sides of the selected word line WLk in the middle of the write stage. The word line driver 21 maintains the verify read voltage VREAD of the unselected word lines WL0 to WLk-2, WLk + 2 to WLn, WLDD, and WLDS other than the unselected word lines WLk-1 and WLk + 1. On the other hand, in the third embodiment, the word line driver 21 maintains the verify read voltage VREADK of the unselected word lines WLk−1 and WLk + 1 adjacent to both sides of the selected word line WLk constant. Then, the word line driver 21 raises the verify read voltage VREAD of the unselected word lines WL0 to WLk-2, WLk + 2 to WLn, WLDD, and WLDS other than the unselected word lines WLk−1 and WLk + 1 in the middle of the write stage. Yes. Other operations in the third embodiment may be the same as the corresponding operations in the second embodiment. The configuration of the third embodiment may be the same as the configuration of the second embodiment.

  FIG. 9A to FIG. 9C are graphs showing the transition of the voltage of the word line in a certain write stage according to the third embodiment.

  As shown in FIG. 9A, verify read voltages of unselected word lines WL0 to WLk-2, WLk + 2 to WLn, WLDD, and WLDS that are not adjacent to the selected word line WLk are VREAD (in the write loop Loopj during the write stage). 1) to VREAD (2).

  As shown in FIG. 9B, the verify read voltage VREADK of the unselected word lines WLk−1 and WLk + 1 adjacent to the selected word line WLk is constant in all the write loops Loop1 to LoopM in the write stage.

  As shown in FIG. 9C, the verify read voltage VCG of the selected word line WLk is constant in all write loops Loop1 to LoopM in the write stage.

  Although the unselected word lines WL0 to WLk-2, WLk + 2 to WLn, WLDD and WLDS are not adjacent to the selected word line WLk, the number thereof is very large. For this reason, even if the verify read voltage of the unselected word lines WL0 to WLk-2, WLk + 2 to WLn, WLDD and WLDS is stepped up from VREAD (1) to VREAD (2), the third embodiment The same effect as that of the embodiment can be obtained. However, the power consumption of the third embodiment is higher than that of the second embodiment.

  The write loop Loopj for stepping up the verify read voltage VREAD (1) to VREAD (2) takes into account the tendency that the number of write loops in the write stage decreases with time as in the first embodiment. Preferably, the write loop is before the middle of the loop. That is, j is preferably an integer smaller than M / 2.

  The number of times to step up the verify read voltage is not limited as in the first embodiment. The word line driver 21 may increase the verify voltage VREAD in each of the write loops Loop1 to LoopM. At this time, the step-up width of the verify read voltage VREAD in each of the write loops Loop1 to LoopM may be ΔVREAD / (M−1).

(Fourth embodiment)
FIG. 10 shows the word lines WL0 to WLn, WLDS, and WLDD of a NAND string NS of the NAND flash memory according to the fourth embodiment of the present invention, and the gates SGS and SGD of the selection transistors Tsels and Tseld. It is a conceptual diagram which shows the verify voltage applied.

  The fourth embodiment is an embodiment of a combination of the second embodiment and the third embodiment. That is, in the fourth embodiment, the word line driver 21 uses the verify read voltage VREADK of the unselected word lines WLk−1 and WLk + 1 adjacent to both sides of the selected word line WLk and the unselected word lines WL0 to WLk−2 and WLk + 2. The verify read voltages VREAD of .about.WLn, WLDD and WLDS are all raised in the middle of the write stage.

  The configuration of the fourth embodiment may be the same as the configuration of the first embodiment.

  FIG. 11A to FIG. 11C are graphs showing the transition of the voltage of the word line in a certain write stage according to the fourth embodiment.

  As shown in FIG. 11A, verify read voltages of unselected word lines WL0 to WLk-2, WLk + 2 to WLn, WLDD, and WLDS that are not adjacent to the selected word line WLk are set to VREAD (in the write loop Loopj during the write stage). 1) to VREAD (2).

  As shown in FIG. 11B, the verify read voltage of the unselected word lines WLk−1 and WLk + 1 adjacent to the selected word line WLk is changed from VREADK (1) to VREADK (2) in the write loop Loopj in the middle of the write stage. It has changed.

  As shown in FIG. 11C, the verify read voltage VCG of the selected word line WLk is constant in all write loops Loop1 to LoopM in the write stage.

  As described above, by stepping up the verify read voltages of the unselected word lines WL0 to WLn, WLDD, and WLDS, the fourth embodiment can obtain the same effect as the first embodiment.

  The voltage difference ΔVREAD between the verify read voltage VREAD (1) and the verify read voltage VREAD (2) and the voltage difference ΔVREADK between the verify read voltage VREADK (1) and the verify read voltage VREADK (2) are the voltages in the first embodiment. The difference may be equal to or less than ΔVREAD. If the voltage difference ΔVREAD and the voltage difference ΔVREADK are set to the same level as the voltage difference ΔVREAD in the first embodiment, the effects of the second and third embodiments can be obtained simultaneously. On the other hand, when the voltage difference ΔVREAD and the voltage difference ΔVREADK are reduced, stress on the memory cell can be reduced, and the width of the threshold voltage distribution can be narrowed without impairing the reliability of the memory cell characteristics.

  In addition, the write loop Loopj for stepping up the verify read voltages VREAD and VREADK is performed before the middle of all the write loops in consideration of the tendency that the number of write loops in the write stage decreases with time as in the first embodiment. Preferably, the write loop is That is, j is preferably an integer smaller than M / 2.

  The number of times that the verify read voltages VREAD and VREADK are stepped up is not limited as in the first embodiment. The word line driver 21 may increase the verify voltages VREAD and VREADK in each of the write loops Loop1 to LoopM. At this time, the step-up widths of the verify read voltages VREAD and VREADK in each of the write loops Loop1 to LoopM may be ΔVREAD / (M−1) and ΔVREADK / (M−1), respectively.

(Fifth embodiment)
FIGS. 12A to 12C are graphs representing a data write operation (program operation) according to the fifth embodiment of the present invention as transitions of threshold voltage distributions of memory cells. The horizontal axis of the graph is the threshold voltage of the memory cell. The vertical axis of the graph is the number of memory cells. In the fifth embodiment, each memory cell MC stores 2-bit data. That is, the NAND flash memory according to the fifth embodiment is a multi-level memory.

  FIG. 12A shows an erased state distribution De, and all memory cells are in an erased state. In order to store 2-bit data in the memory cell MC, two write stages are required.

  In the first write stage, the memory writes data “0” to the memory cells MC of the distribution De (data “1”) in FIG. 12A, and the distribution D0 (data “0”) in FIG. Form (Write Lower Page). At this time, data “0” may be written into the memory cell MC using any one of the first to fourth embodiments. Thereby, the width of the distribution D0 can be narrowed. In the first write stage, the verify level is VA1.

  In the second write stage, the memory forms the distribution Da (data “10”) in FIG. 12C from the memory cells MC in the distribution De (data “1”) in FIG. The distribution Db (data “00”) and the distribution Dc (data “01”) of FIG. 12C are formed from the memory cells MC of the distribution D0 (data “0”) of B) (Upper Page writing). In FIG. 12C, the distribution De is data “11”. In the second write stage, the verify levels are VA2, VB2, and VC2.

  FIG. 13 is a graph showing the transition of the voltage of the selected word line in a certain write stage according to the fifth embodiment. Since the transition of the voltage of the unselected word line may be the same as the transition of the voltage of the unselected word line in any of the fourth embodiments, the illustration is omitted here. In order to write 2-bit data to each memory cell MC, the verify read voltage is changed in three stages in each of the write loops Loop1 to LoopM. The verify read voltage VREAD (A) is a voltage of the selected word line WLk when reading the distribution Da in FIG. The verify read voltage VREAD (B) is a voltage of the selected word line WLk when reading the distribution Db. The verify read voltage VREAD (C) is a voltage of the selected word line WLk when reading the distribution Dc. Therefore, the verify read voltage increases in the order of VREAD (A), VREAD (B), and VREAD (C).

  In each of the write loops Loop1 to LoopM, the verify read operation is executed in each of the distributions Da, Db, and Dc. Therefore, as shown in FIG. 13, in the verify read operation, the read operation is executed using each of the verify read voltages VREAD (A), VREAD (B), and VREAD (C).

  In the initial stage of the write stage, since the program voltage VPGM is low, data having a low threshold voltage is written into the memory cell. When the write loop is repeatedly executed and the program voltage VPGM increases, data having a high threshold voltage is written into the memory cell. That is, the write operation is executed roughly in the order of distributions Da, Db, and Dc.

  Since the write operation is executed in the order of the distributions Da, Db, and Dc, data corresponding to the distribution Da is mainly written in the memory cells in the initial stage of the write stage, and the distributions correspond to the distributions Db and Dc. It can be predicted that the data has not yet been written to the memory cell. Therefore, in the initial write loop of the write stage, only the verify read using the low verify read voltage VREAD (A) is executed, and the verify read using VREAD (B) and VREAD (C) may not be executed. . Therefore, the verify read using VREAD (B) and VREAD (C) may be skipped.

  When the repetition of the write loop proceeds to some extent, it can be predicted that the data corresponding to the distributions Da and Db are written to the memory cells, and the data corresponding to the distribution Dc is not yet written to the memory cells. Therefore, the verify read using VREAD (A) and the verify read using VREAD (B) may be executed, and the verify read using VREAD (C) may be skipped.

  Further, when the repetition of the write loop proceeds, the data of the distribution Dc is written into the memory cells, and the data of the distribution Da can be predicted to be written into the memory cells. Therefore, each verify read using VREAD (B) and VREAD (C) may be executed, and the verify read using VREAD (A) may be skipped. Thus, if verify skip is used, the period of each write loop is shortened, and as a result, the write stage can be executed in a short time.

  Reference is again made to FIG. Among the distributions Da to Dc, the threshold voltage of the memory cell belonging to the distribution Dc is the highest, and the voltage applied to the unselected word line at the time of reading is determined by the upper limit of the distribution Dc. When the width of the distribution Dc is narrow, the maximum value of the threshold voltage is lowered, so that the voltage applied to the unselected word line can be lowered. Therefore, it is preferable to apply any of the first to fourth embodiments at least in writing of data “01”. That is, the word line driver 21 increases the verify voltage stepwise during the stage of writing data “01” in which the threshold voltage of the memory cell is the highest among the 2-bit data. Thereby, the width of the distribution Dc can be narrowed, and the unselected word line voltage at the time of reading can be reduced. As a result, the writing speed can be increased.

  For example, when the memory writes data in the order of distribution Da (data “10”), Db (data “00”), and Dc (data “01”) based on the magnitude of the threshold voltage in the second write stage, It is preferable to apply any one of the first to fourth embodiments when writing the distribution Dc having the highest voltage.

  When writing is performed in the order of the distribution Da, the distribution Db, and the distribution Dc, the writing of the distribution Da is completed first among the distributions Da to Dc. After the writing is completed, the memory cells in the distribution Da are subjected to a proximity effect (also referred to as inter-cell interference) from the memory cell to which writing is subsequently performed. For this reason, the width of the distribution Da is likely to be wider than the other distributions Db and Dc. Therefore, any one of the first to fourth embodiments may be applied to the writing of data “10”. Thereby, both the widths of the distributions Dc and Da can be narrowed. By narrowing the widths of the distributions Dc and Da, the threshold voltage difference between the distribution De and the distribution Dc is further reduced. Thereby, the unselected word line voltage at the time of reading can be further reduced, and the writing speed can be increased.

  Furthermore, any of the first to fourth embodiments may be applied to writing all of the distributions Da to Dc. Thereby, the width | variety of distribution Da-Dc can be narrowed. By narrowing the width of the distributions Da to Dc, the threshold voltage difference between the distribution De and the distribution Dc is further reduced. Thereby, the unselected word line voltage at the time of reading can be further reduced, and the writing speed can be increased.

  Of course, if there is a distribution that is particularly likely to vary among the distributions Da to Dc, the memory can apply any of the first to fourth embodiments when writing data corresponding to the distribution. Good. Thereby, the threshold voltage difference between the distribution De and the distribution Dc can be effectively reduced. Thereby, the unselected word line voltage at the time of reading can be further reduced, and the writing speed can be increased.

  The word line driver 21 may increase the verify voltage in the middle of the stage of writing the last written data among the plurality of bits of data. In the above example, the memory cell MC belonging to the distribution Dc is written last. Therefore, the first to fourth embodiments described above are performed at the time of writing the distribution Dc written last, based on the writing order of the distributions Da (data “10”), Db (data “00”), and Dc (data “01”). It is preferable to apply any of the above. When the distribution width of the distribution Dc in which writing is finally performed is narrowed, the amount of change in the threshold voltage of the memory cell during writing can be reduced. When the amount of variation in the threshold voltage of the memory cell is small, the proximity effect (inter-cell interference) that the memory cell belonging to the distribution Dc to which writing is executed last gives to the memory cell that has been written before is small. . As a result, it is possible to suppress not only the distribution Dc in which writing is executed last but also the other distributions Da and Db from spreading by the last writing.

  For example, in the second write stage, when the memory forms the distribution Dc (data “01”) and then writes in the order of Da (data “10”) and Db (data “00”), the threshold voltage is the highest. It is preferable to apply any of the first to fourth embodiments when writing the distribution Dc. In addition, it is preferable to apply any one of the first to fourth embodiments when writing the distribution Db in which writing is finally performed.

  In the fifth embodiment, the memory writes 2-bit data in the memory cell MC. However, when writing data of 3 bits or more into each memory cell MC, any of the first to fourth embodiments may be applied.

  FIG. 14 is a graph of the threshold voltage distribution when 3-bit data is written in the memory cell MC. The horizontal axis of the graph is the threshold voltage of the memory cell. The vertical axis of the graph is the number of memory cells.

  Even in the case of a 3-bit memory, as in the case of a 2-bit memory, any one of the first to fourth embodiments can be applied. For example, the word line driver 21 increases the verify voltage stepwise during the stage of writing data corresponding to the distribution D7 in which the threshold voltage of the memory cell is the highest among the 3-bit data. Thereby, the width | variety of distribution D7 can be narrowed. By reducing the width of the distribution D7, the threshold voltage difference between the distribution De and the distribution D7 is reduced. Thereby, the unselected word line voltage at the time of reading can be reduced, and the writing speed can be increased.

  Note that the verify voltage may be increased stepwise during the stage of writing data corresponding to the two distributions D6 and D7 having the highest threshold voltage. Thereby, the threshold voltage difference between the distribution De and the distribution D7 is further reduced, and the word line voltage at the time of writing or reading can be further reduced.

  For example, the word line driver 21 may increase the verify voltage in the middle of the stage of writing the last written data among the 3-bit data. When data corresponding to the distribution Dm (1 ≦ m ≦ 7) is written last, the verify voltage is increased stepwise in the middle of the stage of writing data corresponding to the distribution Dm. As a result, the width of the distribution Dm can be narrowed, and the proximity effect (inter-cell interference) applied to the memory cell that has been written before can be reduced. As a result, not only the distribution Dm but also the distribution width other than the distribution Dm can be narrowed.

  In the 3-bit memory shown in FIG. 14, verify skip can be used in each write loop. Thereby, the period of each write loop is shortened, and as a result, the write stage can be executed in a short time.

(Modification)
FIG. 15 is a conceptual diagram showing verify voltages applied to the word lines WL0 to WLn, WLDS, and WLDD of the NAND string NS and the gates SGS and SGD of the selection transistors Tsels and Tseld according to the modification of the first embodiment. It is. In this modification, verify read voltages of the memory cells MCds and MCdd adjacent to the selection transistors Tsels and Tseld are fixed to Vrds and Vrdd, respectively. Vrds and Vrdd are higher than the gate voltage VSG of the selection transistor and lower than the verify read voltage VREAD (1) of other word lines.

  The word line driver 21 fixes the verify voltages of the word lines WLDS and WLDD connected to the unselected memory cells MCds and MCdd at both ends of the NAND string NS to Vrds and Vrdd, and other unselected memory cells MC0 to MCk. −1, the verify voltage VREAD (1) of the word lines WL0 to WLk−1 and WLk + 1 to WLn connected to MCk + 1 to MCn is increased. WLDS and WLDD in FIG. 15 and the like are dummy word lines. The dummy word line is a word line to which no writing is performed. For this reason, the threshold voltage of the dummy cells MCdd and MCds connected to the dummy word line may be low. Therefore, the verify voltages of the word lines WLDS and WLDD may be fixed to voltages Vrds and Vrdd lower than VREAD (1) and VREAD (2). Thereby, it is possible to avoid applying excessive stress to the gates of the dummy cells MCds and MCdd.

  Other operations of the memory according to this modification are the same as those of the memory according to the first embodiment. Therefore, this modification can obtain the effect of the first embodiment. Moreover, this modification can be easily applied to the second to fifth embodiments.

  When this modification is applied to the second to fifth embodiments, the word line driver 21 applies the highest voltage to the unselected word lines WLk−1 and WLk + 1 adjacent to the selected word line WLk in the NAND string NS. The lowest voltage is applied to the unselected word lines WLDS and WLDD farthest from the selected word line WLk. Thereby, it is possible to avoid applying excessive stress to the gates of the dummy cells MCds and MCdd.

  Further, the non-selected memory cells MCk + 1 and MCk−1 adjacent to the selected memory cell MCk are difficult to conduct due to the proximity effect by the selected word line WLk. However, by applying a high voltage to unselected word lines WLk−1 and WLk + 1 adjacent to the selected word line WLk, the unselected memory cells MCk + 1 and MCk−1 can be made sufficiently conductive. That is, by applying a high voltage to the unselected word lines WLk−1 and WLk + 1 adjacent to the selected word line WLk, the threshold voltages of the unselected memory cells MCk + 1 and MCk−1 adjacent to the selected memory cell MCk are apparently lowered. can do.

BL ... bit line, WL ... word line, MC ... memory cell, 12 ... sense amplifier, 21 ... word line driver, VREAD ... verify read voltage of unselected word line, VCG ... verify read voltage of selected word line, VPASS ... non Selected word line write voltage, VPGM ... selected word line write voltage, Tsels, Tsel ... selected transistor, Loop1 to LoopM ... write loop, VL0, VL1 ... threshold voltage, Dp1, Dp2, Dp3 ... threshold voltage distribution

Claims (6)

Multiple word lines,
Multiple bit lines,
A plurality of memory cells having gates connected to any of the word lines;
A word line driver for driving voltages of the plurality of word lines;
A sense amplifier that detects data of the memory cell via the plurality of bit lines;
A plurality of the memory cells are connected in series between the bit line and the source to form a cell string,
In a certain write loop in a write stage, a write loop consisting of a write operation for writing data to a selected memory cell in the cell string and a verify operation for verifying that data has been written to the selected memory cell is repeated a plurality of times. At the time of verify operation, the word line driver increases the voltage at the time of verifying any non-selected word line connected to non-selected memory cells other than the selected memory cell in the cell string. A semiconductor memory device.   The word line driver is configured to verify a non-selected word line connected to a non-selected memory cell adjacent to both sides or one side of the selected memory cell at the time of a verify operation in a certain write loop in the write stage. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is raised.   The word line driver is configured to detect unselected word lines connected to unselected memory cells other than unselected memory cells adjacent to both sides of the selected memory cell at a verify operation time in a certain write loop in the write stage. 3. The semiconductor memory device according to claim 1, wherein a voltage at the time of verification is increased.   The word line driver increases a voltage at the time of verifying a non-selected word line connected to a non-selected memory cell other than a non-selected memory cell at both ends or one end of the cell string. The semiconductor memory device according to claim 1.   5. The word line driver increases the voltage at the time of verifying any one of the word lines connected to the non-selected memory cells for each write loop in a stepwise manner. The semiconductor memory device according to any one of the above. Each of the memory cells can store a plurality of bits of data,
2. The word line driver according to claim 1, wherein the voltage at the time of verification is increased stepwise during a period of writing data in which the threshold voltage of the memory cell is highest among the plurality of bits of data. 6. The semiconductor memory device according to any one of items 5.

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