JP2011249627A - Semiconductor wafer pattern exposure method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor wafer pattern exposure method capable of increasing the number of chips obtainable from a semiconductor wafer.SOLUTION: A semiconductor wafer pattern exposure method is such that, when a circuit pattern is exposed to a semiconductor wafer 18 while sequentially moving a rectangle-shaped exposure unit area 35 in a first direction parallel to the short sides of the rectangle, the semiconductor wafer 18 is tilted during exposure so that the surface roughness in the exposure unit area 35 due to an uneven thickness of the semiconductor wafer 18 will become smaller on a focal plane of exposure. In the above method, an edge exclusion area 31 of the semiconductor wafer 18 defined for excluding the peripheral section thereof from the areas for which exposure or the focal plane of exposure is determined, is set in such a way that a first exclusion width d1 in the first direction is smaller than a second exclusion width d2 in a second direction at right angles to the first direction. And, within the exposure unit area 35 not including the edge exclusion area 31, the focal plane of exposure is set by tilting the semiconductor wafer 18 so that the surface roughness becomes smaller on the focal plane of exposure.

Description

  The present invention relates to a pattern exposure method for a semiconductor wafer.

  When a large-scale integrated circuit (LSI) or the like is formed on a semiconductor wafer, a process (lithography process) is performed by reducing and projecting a circuit pattern drawn on the reticle onto the semiconductor wafer by an exposure apparatus called a stepper.

  Usually, a circuit pattern for one chip or a plurality of chips is performed by one exposure, and the operation of moving the exposure position on the semiconductor wafer to expose the next chip (or chip group) is repeated. Bake all over.

  With the miniaturization and high integration of the semiconductor device, the exposure apparatus includes a semiconductor wafer with respect to the exposure focal plane at the time of pattern exposure in order to suppress the occurrence of pattern blur due to surface irregularities caused by uneven thickness of the semiconductor wafer. A leveling mechanism for tilting the semiconductor wafer is employed so that the surface unevenness due to the thickness unevenness is minimized.

  Furthermore, when the pattern is exposed on the semiconductor wafer, a scan exposure method is adopted in which the pattern on the reticle is not exposed at a time, but a part of the pattern is scanned and the semiconductor wafer is moved while moving. .

  On the other hand, the outer peripheral portion of the semiconductor wafer has a different uneven state as compared with the central portion of the semiconductor wafer, and there is a large local inclination, so-called sagging that is difficult to avoid in the processing of the semiconductor wafer. The above-described method is not always effective for the deterioration of flatness due to sagging, and it is difficult to suppress the occurrence of pattern blur.

  Conventionally, in order to avoid the influence of the sagging, an edge exclusion region for removing the outer peripheral portion of the semiconductor wafer from the exposure or exposure focal plane determination region is provided in advance on the semiconductor wafer (see, for example, Patent Document 1). .

  The edge exclusion region is provided in a ring shape having a certain exclusion width from the outer peripheral edge, for example, 4 mm width, with respect to the circular semiconductor wafer.

  However, since the exclusion width of this edge exclusion area is uniquely determined, there may be a case where an area that is not affected by sagging is included in the edge exclusion area depending on the shape of the area to be exposed. As a result, there is a problem that an area that should originally be usable is wasted, and the number of chips that can be obtained from one semiconductor wafer is reduced.

JP 2009-88549 A

  The present invention provides a pattern exposure method for a semiconductor wafer that can increase the number of chips that can be obtained from the semiconductor wafer.

  According to the semiconductor wafer exposure method of one aspect of the present invention, a semiconductor wafer is exposed to a circuit pattern while sequentially moving a rectangular exposure unit region in a first direction parallel to the short side of the rectangle. A pattern exposure method for a semiconductor wafer in which the semiconductor wafer is tilted and exposed so that surface unevenness due to thickness unevenness of the semiconductor wafer in the exposure unit region is reduced in an exposure focal plane, the semiconductor wafer being exposed to the semiconductor wafer An edge exclusion region that excludes the outer peripheral portion from the region that determines the exposure or exposure focal plane is greater than the second exclusion width in the second direction in which the first exclusion width in the first direction is perpendicular to the first direction. In the exposure unit area that does not include the edge exclusion area, the surface unevenness is small in the exposure focal plane. Kunar so to tilt the semiconductor wafer is characterized by setting the exposure focal plane.

  ADVANTAGE OF THE INVENTION According to this invention, the pattern exposure method of the semiconductor wafer which can increase the chip | tip number which can be acquired from a semiconductor wafer is obtained.

5 is a flowchart showing an exposure method according to an embodiment of the present invention. 1 is a block diagram showing a configuration of an exposure apparatus according to an embodiment of the present invention. The figure for demonstrating the edge exclusion area | region of the semiconductor wafer which concerns on the Example of this invention as contrasted with a comparative example. The figure which shows the flatness of the semiconductor wafer which concerns on the Example of this invention. The figure which shows the flatness of the semiconductor wafer which concerns on the Example of this invention. The figure for demonstrating the exposure area | region of the semiconductor wafer outer peripheral part which concerns on the Example of this invention in contrast with a comparative example. The flowchart which shows another exposure method which concerns on the Example of this invention.

  Embodiments of the present invention will be described below with reference to the drawings.

  A pattern exposure method according to the present embodiment will be described with reference to FIGS. FIG. 1 is a flowchart showing an exposure method, FIG. 2 is a block diagram showing a configuration of an exposure apparatus, and FIG. 3 is a diagram for explaining an edge exclusion region of a semiconductor wafer in comparison with a comparative example.

  First, the exposure apparatus according to the present embodiment will be described. As shown in FIG. 2, the exposure apparatus 10 is a scan type stepper apparatus. The exposure apparatus 10 includes a pattern exposure light source 11, a pattern exposure mask 12, a reduction projection optical system 13, a mask scan mechanism 14 that scans and moves the mask 12, and a control unit that controls the entire exposure apparatus 10 based on a program ( CPU) 15, stage 16 for mounting wafer, stage scanning mechanism 17 for moving stage 16 and the like, and exposing the circuit pattern while sequentially moving the exposure unit area with respect to semiconductor wafer 18 on stage 16 It is.

  Further, the exposure apparatus 10 includes leveling control means for tilting the semiconductor wafer 18 so that the surface unevenness caused by the thickness unevenness of the semiconductor wafer 18 in the exposure unit region is minimized in the exposure focal plane during pattern exposure. .

  This leveling control means performs distance measurement between the pattern exposure mask 12 side and a plurality of locations in each chip in the exposure unit area of the semiconductor wafer 18 when the semiconductor wafer 18 is exposed to the circuit pattern. In addition, the reflected light of the laser projected from the laser light source 19 to the semiconductor wafer 18 is received by a plurality of sensors 20 and converted into electrical signals, the output signals of the sensors 20 are processed, distance measurement is performed, and the reference plane calculation means 21 A reference plane is calculated.

  Then, based on the reference surface calculated by the reference surface calculation means 21, the wafer inclination control mechanism 22 is controlled to control the inclination of the stage 16 (inclination of the semiconductor wafer 18) and the height position of the stage 16 as necessary. Is configured to do.

  By such leveling control means, the exposure focal plane is set by tilting the semiconductor wafer 18 so that the surface unevenness is minimized in the exposure focal plane within the exposure unit region. In this case, the CPU 15 for controlling the exposure apparatus also controls the leveling control means.

  A sagging occurs in the outer periphery of the semiconductor wafer 18. For this reason, the semiconductor wafer 18 is provided with an edge exclusion region that excludes the outer peripheral portion from the exposure or exposure focal plane determination region.

  The edge exclusion area data 23 is stored in, for example, an external storage, and is read by the CPU 15 for controlling the exposure apparatus at the start.

  The CPU 15 discriminates the exposure unit area not including the edge exclusion area based on the edge exclusion area data 23, and tilts the semiconductor wafer 18 so that the surface unevenness is minimized in the exposure focal plane within the determined exposure unit area. An exposure focal plane is set, and the circuit pattern of the mask 12 is exposed.

  The sagging occurs in the outer periphery of the semiconductor wafer for the following reason. The process of making the surface of the semiconductor wafer into a mirror surface is performed by swinging and rotating the semiconductor wafer on a polishing cloth (urethane or non-woven fabric) using an abrasive typified by colloidal silica.

  At this time, since a load is applied to the back surface of the semiconductor wafer, the semiconductor wafer is not a little indented into the polishing cloth, and the polishing cloth contacts the outer peripheral portion of the semiconductor wafer obliquely.

  As a result, the outer peripheral corner portion of the semiconductor wafer is polished, and the outer peripheral portion of the semiconductor wafer becomes a rounded inclined surface. Due to the presence of the sagging, the flatness of the periphery of the semiconductor wafer is deteriorated.

  Next, the edge exclusion region of the semiconductor wafer 18 will be described in comparison with the comparative example. FIG. 3 shows a quarter-circle region of the semiconductor wafer 18. Here, the comparative example is an edge exclusion region provided in a circular shape with a certain exclusion width from the outer peripheral edge of the semiconductor wafer 18. First, the edge exclusion region of the comparative example will be described.

  As shown in FIG. 3, the edge exclusion region 36 of the comparative example includes an exclusion width in the first direction (Y direction in the figure) and an exclusion in the second direction (X direction in the figure) perpendicular to the first direction. Both widths are d2 and are equally provided.

  The edge exclusion region 36 is outside the circle 37 having a radius (R−d2) between the radius R of the semiconductor wafer 18 and the exclusion width d2. This exclusion width is normally determined empirically with reference to the pattern exposure result of the preceding lot.

  On the other hand, in the edge exclusion region 31 of the present embodiment, the first exclusion width d1 in the Y direction is set smaller than the second exclusion width d2 in the X direction (d1 <d2). The edge exclusion region 31 has a long diameter as the difference between the radius R of the semiconductor wafer 18 and the first exclusion width d1 (R-d12), and a short difference between the radius R of the semiconductor wafer 18 and the second exclusion width d2 (R-d2). It is the outside of the ellipse 32 as a diameter.

  Based on the shape of the exposure unit area and the flatness evaluation result of the semiconductor wafer 18, the exclusion width predicts an area where pattern blur does not occur due to the influence of sagging from the outer peripheral part, and excludes the area predicted from the outer peripheral part. The predetermined area is set as the edge exclusion area 31.

  Specifically, a region where the flatness of the semiconductor wafer 18 in the exposure unit region is smaller than the focal depth of the reduction projection optical system 13 is predicted as a region where pattern blur does not occur. The depth of focus D of the reduction projection optical system 13 is expressed by the following equation.

R = K1 × λ / (NA) (1), D = K2 × λ / (NA) 2 (2)
Here, R is the resolution, NA is the aperture ratio of the reduction projection optical system 13, λ is the wavelength of the pattern exposure light source 11, and K1 and K2 are constants.

  A region 33 on the semiconductor wafer 18 indicates an exposure region 33 that can be exposed on the semiconductor wafer 18 by the reticle of the mask 12 used in the exposure apparatus 10. In the exposure region 33, for example, a total of six chip regions 34 are arranged, three in the Y direction and two in the X direction.

  The hatched area 35 in the two chip areas 34 arranged in the X direction is an exposure unit area 35 exposed at a time by the scanning exposure of the exposure apparatus 10. The exposure unit area 35 has a rectangular shape, and the size is, for example, 8 mm × 26 mm. Accordingly, the size of the exposure region 33 is, for example, 33 mm × 26 mm.

  The exposure apparatus 10 exposes the circuit pattern of the reticle while sequentially moving the rectangular exposure unit area 35 in the Y direction parallel to the short side of the exposure unit area 35.

  As a result, in the edge exclusion region 36 of the comparative example, the pattern can be exposed to 131 chip regions 34 indicated by white portions existing inside the circle 37 on the semiconductor wafer 18.

  On the other hand, in the edge exclusion region 31 of the present embodiment, in addition to 131 chip regions 34 shown on the inside of the circle 37 on the semiconductor wafer 18, nine hatched chip regions 34, A pattern can be exposed to 140 chip regions 34.

  As a result, the number of chips (gross) that can be obtained from the semiconductor wafer 18 increases by approximately 7% (131/140).

  As described above, in the edge exclusion region 31 of the present embodiment, when the exposure unit region 35 is rectangular and scanned along the Y direction parallel to the short side of the rectangle, the “sag” of the outer periphery in the short side direction. Even in such a case, the first exclusion width d1 in the Y direction is reduced and the second exclusion width d2 in the X direction is increased by utilizing the fact that it easily follows the shape.

  Next, the reason why such an edge exclusion region 31 can be set will be described. 4 and 5 are diagrams showing the distribution of flatness of the semiconductor wafer 18.

  The definition of flatness is SFQR (Site Front least sQuare Rang). SFQR obtains the least square plane based on the surface irregularities in the measurement region, and indicates the maximum value of the amplitude of the surface irregularities in the direction perpendicular to the least square plane.

  The SFQR was measured by setting the measurement area to 8 mm × 26 mm, which is the same as the exposure unit area 35, and the edge exclusion area with edge exclusion widths of 3 mm (FIG. 4) and 2 mm (FIG. 5). In FIG. 4 and FIG. 5, the measurement region where hatching and cross hatching are performed is a region where SFQR is 0.02 μm or more, and is a region where pattern blur is predicted to occur, for example.

  As shown in FIG. 4, when the edge exclusion width is 3 mm, it can be seen that the measurement region having SFQR of 0.02 μm or more is distributed in the outer peripheral portion and the flatness of the outer peripheral portion is low. The abundance ratio of the measurement region having an SFQR of 0.02 μm or more is approximately 5.2% (17/324).

  As shown in FIG. 5, when the edge exclusion width is 2 mm, the measurement region with SFQR of 0.02 μm or more increases at the outer peripheral portion, and the flatness of the outer peripheral portion further decreases. The abundance ratio of the measurement region having an SFQR of 0.02 μm or more is approximately 14% (47/336).

  Here, it can be seen that in the region where the flatness of the outer peripheral portion deteriorates, the X direction is remarkable, whereas the Y direction is hardly seen.

  This is because the flatness measurement region is a rectangle, so the measurement width in the Y direction parallel to the short side of the rectangle is smaller than the measurement width in the X direction parallel to the long side of the rectangle. As a result, assuming that the maximum inclination of the sag at the outer peripheral portion of the semiconductor wafer 18 is the radial direction, the measurement area in the 3 o'clock and 9 o'clock directions is strongly affected by the sag, for example, in the direction of the short hand of the watch. Deterioration of the degree becomes remarkable. On the other hand, it is considered that the measurement area in the 6 o'clock and 12 o'clock directions is less affected by sagging and the flatness did not deteriorate.

  Since the exposure unit area 35 is the same rectangle as the flatness measurement area, even in the exposure unit area 35, the exposure unit area 35 in the 3 o'clock and 9 o'clock directions is strongly affected by sagging, and pattern blurring is likely to occur. The exposure unit area 35 in the 12 o'clock direction is considered to be less affected by sagging and less likely to cause pattern blur.

  Therefore, even if the edge exclusion areas in the 6 o'clock and 12 o'clock directions are smaller than the edge exclusion areas in the 3 o'clock and 9 o'clock directions, it is considered that no exposure failure due to pattern blur does not occur.

  FIG. 6 is a view for explaining the exposure region of the semiconductor wafer 18 of this embodiment in comparison with the comparative example. In the figure, an exposure region 44 having unit exposure regions 41, 42, 43 in which six chip regions 34, two in the X direction and three in the Y direction, are arranged is the outer peripheral edge of the semiconductor wafer 18 in the 12 o'clock direction. In the case of inscribed.

  In the comparative example, the exclusion width of the edge exclusion region 36 in the Y direction is d2. Since the exposure unit area 41 in the exposure area 44 is inside the edge exclusion area 36, it is scanned and exposed as usual. Since the exposure unit area 42 covers a part of the edge exclusion area 36, scanning exposure is not performed. Since a part of the exposure unit region 43 is outside the semiconductor wafer 18, it is outside the exposure range.

  On the other hand, in this embodiment, the exclusion width of the edge exclusion region 31 in the Y direction is d1 which is smaller than d2. The exposure unit areas 41 and 43 in the exposure area 44 are the same as in the comparative example. However, since the exposure unit area 42 is inside the edge exclusion area 31, the scan exposure is performed as usual. As a result, the exposure unit area 42 that was wasted in the comparative example can be used effectively.

  Next, in order to confirm this, the result of exposure of the circuit pattern on the semiconductor wafer will be described. First, 100 semiconductor wafers having a diameter of 300 mm and polished on both sides were prepared. Of these, the edge exclusion region 36 of the comparative example was set to 50 semiconductor wafers with an exclusion width d2 of 2 mm.

  A resist film was formed on the semiconductor wafer, and a stripe pattern having a width of 0.025 μm and a pitch of 0.040 μm was exposed.

  At this time, exposure is performed by scanning a range of 33 mm (Y direction) × 26 mm (X direction) as one shot while performing leveling control of the semiconductor wafer using the leveling control means with an exposure unit area of 8 × 26 mm, A 12 × 10.5 mm element was prepared. In this case, exposure of 6 chips, 2 chips in the X direction and 3 chips in the Y direction, in one cell was performed.

  After the exposure, the resist film was developed and the stripe pattern transferred to the resist was measured with a dimension SEM. In twelve semiconductor wafers out of the first fifty, pattern blur occurred in the semiconductor chip on the outer periphery.

  Next, after peeling off the resist film to which the stripe pattern was transferred, a resist film was formed again on the semiconductor wafer. This time, the exclusion width d2 was set to 4 mm, the edge exclusion region 36 of the comparative example was set, and exposure was performed in the same manner. As a result, pattern blur did not occur, but the chip yield decreased by 3% instead.

  On the other hand, in this example, the flatness (SFQR) of the remaining 50 semiconductor wafers was measured. Based on the measurement result, an area where SFQR is larger than the depth of focus D and pattern blur occurs is predicted, and the edge exclusion area 31 is set so as to exclude the predicted area. In the edge exclusion region 31, the first exclusion width d1 in the Y direction is approximately 2 mm, and the second exclusion width in the X direction is 4 mm.

  Scan exposure was performed only on the area not including the edge exclusion area 31. As a result, no defocusing occurred in all semiconductor wafers, and no reduction in chip yield was observed.

  From the above, returning to FIG. 1, the pattern exposure method of this embodiment will be described. As shown in FIG. 1, first, the semiconductor wafer 18 is set in a flatness (SFQR) measuring device, and the flatness (SFQR) of the semiconductor wafer 18 in the measurement region corresponding to the exposure unit region 35 is measured (step S01). ).

  Step S01 is repeated until all the measurement areas on the semiconductor wafer 18 are measured (step S02). The measurement region does not have to be the entire surface of the semiconductor wafer 18, and is sufficient at the outer peripheral portion of the semiconductor wafer 18 and the vicinity thereof.

  Next, based on the measurement result, the exclusion width that can be placed in the Y direction is d1, and the exclusion width that can be placed in the X direction is d2, so that the measurement region whose SFQR is larger than the focal depth D of the reduction projection optical system 13 is the edge exclusion region. An elliptical edge exclusion region is set, and edge exclusion region data 23 is created (step S03).

  Next, the semiconductor wafer 18 is placed on the stage 16 of the exposure apparatus 10, the edge exclusion region data 23 is read by the CPU 15, and the operation of the exposure apparatus 10 is started. Thereby, the exposure apparatus 10 checks whether the exposure unit area to be exposed is located inside the edge exclusion area (step S04), and if it is located inside the edge exclusion area (YES in step S04), Next, in step S05, the reference plane calculation means 21 calculates the exposure reference plane using the information of all the sensors 20 (step S05).

  Next, the level of the semiconductor wafer 18 is leveled by the stage tilt control mechanism 22 (step S06), and the circuit pattern is exposed to the exposure unit area of the semiconductor wafer 18 by the reduction projection optical system 13 (step S07).

  Next, step S04 to step S07 are repeated until the entire exposure unit area is exposed (step S08).

  On the other hand, when an edge exclusion area is included in the exposure unit area (NO in step S04), the exposure unit area is not exposed and the process skips to step S08.

  As described above, in the pattern exposure method for a semiconductor wafer according to the present embodiment, pattern blurring occurs on the semiconductor wafer 18 due to the influence of sagging from the outer periphery based on the flatness of the semiconductor wafer 18 in the exposure unit region 35. The first exclusion width d1 in the Y direction is smaller than the second exclusion width d2 in the X direction in order to predict a region that does not occur and exclude the region excluding the region predicted from the outer periphery from the exposure or exposure focal plane determination region. An edge exclusion region 31 is provided.

  As a result, an area that is not affected by the sagging of the outer peripheral portion of the semiconductor wafer 18 can be effectively used without waste. Therefore, a pattern exposure method for a semiconductor wafer that can increase the number of chips that can be obtained from one semiconductor wafer can be obtained.

  Here, the case of performing the scan exposure after measuring the flatness of the semiconductor wafer 18 in advance and setting the edge exclusion region based on the result has been described. However, the present invention is not limited to this embodiment, but on the spot. A method of performing scan exposure while determining whether or not the region is an edge exclusion region is also possible. In that case, the exposure apparatus 10 has a function of converting the reference plane with all sensor information and calculating the flatness (SFQR).

  FIG. 7 is a flowchart showing a method of performing scan exposure while determining whether or not the region is an edge exclusion region on the spot. In FIG. 7, the exposure reference plane is calculated using the information of all the sensors 20, and the flatness (SFQR) is calculated (step S12).

  Next, it is determined whether SFQR is equal to or smaller than the focal depth D of the reduction projection optical system 13 (step S13). If the focal depth is equal to or smaller than the focal depth D (YES in step S13), it is determined to be inside the edge exclusion region. Go to step S06. On the other hand, when it is larger than the focal depth D (NO in step S13), it is determined that the region is an edge exclusion region, and the process skips to step S08.

DESCRIPTION OF SYMBOLS 10 Exposure apparatus 11 Pattern exposure light source 12 Mask 13 Reduction projection optical system 14 Mask scanning mechanism 15 Control means (CPU)
16 Stage 17 Stage scan mechanism 18 Semiconductor wafer 19 Laser light source 20 Sensor 21 Reference plane calculation means 22 Stage tilt control mechanism 23 Edge exclusion area data 31, 36 Edge exclusion area 32 Ellipse 33, 44 Exposure area 34 Chip areas 35, 41, 42 , 43 Exposure unit area 37 Circle d1 First exclusion width d2 Second exclusion width

Claims (5)

When the circuit pattern is exposed to the semiconductor wafer while sequentially moving the rectangular exposure unit area in the first direction parallel to the short side of the rectangle, the thickness of the semiconductor wafer in the exposure unit area A pattern exposure method for a semiconductor wafer in which the semiconductor wafer is tilted and exposed such that surface irregularities are reduced in the exposure focal plane,
An edge exclusion region that excludes an outer peripheral portion of the semiconductor wafer from an area that determines exposure or an exposure focal plane is formed on the semiconductor wafer, and a second exclusion width in the first direction is a second that is perpendicular to the first direction. Set to be smaller than the second exclusion width in the direction of
A pattern exposure method for a semiconductor wafer, wherein an exposure focal plane is set by inclining the semiconductor wafer so that the surface irregularities are reduced in the exposure focal plane within the exposure unit area not including the edge exclusion area.   The edge exclusion region includes an ellipse having a major axis that is the difference between the radius of the semiconductor wafer and the first exclusion width, and a minor axis that is the difference between the radius of the semiconductor wafer and the second exclusion width, and an outer peripheral edge of the semiconductor wafer. 2. The pattern exposure method for a semiconductor wafer according to claim 1, wherein the pattern exposure method is between.   In the edge exclusion region, the depth of the sagging in the direction perpendicular to the least square plane based on the sagging of the outer periphery of the semiconductor wafer in the exposure unit region of the outer periphery of the semiconductor wafer is larger than the depth of focus of the exposure optical system. 2. The pattern exposure method for a semiconductor wafer according to claim 1, further comprising a region where defocus occurs.   Obtaining data indicating the sagging of the outer periphery of the semiconductor wafer in the exposure unit region in advance, based on the data, predicting a region where the defocus does not occur, and excluding the predicted region from the outer periphery 4. The semiconductor wafer pattern exposure method according to claim 3, wherein the exposure is performed after the edge exclusion region is set.   Obtaining data indicating the sagging of the outer peripheral portion of the semiconductor wafer in the exposure unit region, predicting a region where the defocus does not occur based on the data, and subtracting the predicted region from the outer peripheral portion, 4. The pattern exposure method for a semiconductor wafer according to claim 3, wherein the exposure is performed while setting as an edge exclusion region.

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