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JP2000260840A - Method and device for measuring semiconductor substrate - Google Patents

Method and device for measuring semiconductor substrate

Info

Publication number
JP2000260840A
JP2000260840A JP11067099A JP6709999A JP2000260840A JP 2000260840 A JP2000260840 A JP 2000260840A JP 11067099 A JP11067099 A JP 11067099A JP 6709999 A JP6709999 A JP 6709999A JP 2000260840 A JP2000260840 A JP 2000260840A
Authority
JP
Japan
Prior art keywords
semiconductor substrate
measurement unit
exposure
measuring
unit region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11067099A
Other languages
Japanese (ja)
Inventor
Sukemune Udo
働 祐 宗 有
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP11067099A priority Critical patent/JP2000260840A/en
Publication of JP2000260840A publication Critical patent/JP2000260840A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70Microphotolithographic exposure; Apparatus therefor
    • G03F7/70216Mask projection systems
    • G03F7/70358Scanning exposure, i.e. relative movement of patterned beam and workpiece during imaging

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

PROBLEM TO BE SOLVED: To avoid a leveling error in a scan type stepper by, at measuring flatness for examining an exposure focal point plane with a semiconductor substrate tilted, measuring the flatness of the semiconductor substrate for each measurement unit region whose area is that of an exposure unit region or less. SOLUTION: An exposure unit region has a horizontal length X mm and vertical length Y mm, while a measurement unit region is a region S21 having a horizontal length L1 mm which is a scanning direction for scan exposure and a vertical length L2 mm. LTV-measurement is performed for each measurement unit region S21 to determine a leveling reference plane for each measurement unit region S21, and the measurement unit region is sequentially shifted from S21a to S21b, and then to S21c for measurement likewise, determining a leveling reference plane. Related to shifting of measurement unit region, the measurement unit regions S21a and S21b, for example, as well as S21b and S21c, are performed to overlap by at least 1/2 of horizontal length. Thus, a high-precision leveling control is provided.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は半導体基板の測定方
法及び測定装置に係り、特に、半導体基板に回路パター
ンをスキャン露光する際における半導体基板の平坦度の
測定方法及び測定装置に関する。
The present invention relates to a method and an apparatus for measuring a semiconductor substrate, and more particularly to a method and an apparatus for measuring the flatness of a semiconductor substrate when scanning and exposing a circuit pattern on the semiconductor substrate.

【0002】[0002]

【従来の技術】半導体装置製造プロセスにおけるリソグ
ラフィ工程は、レチクルに描かれた回路パターンをステ
ッパと称される露光装置により半導体基板上に縮小投影
してその回路パターンを焼き付ける工程である。回路パ
ターンの焼き付けは、1チップ又は複数チップからなる
チップ群を1回の露光で行い、露光箇所を順次移動して
後続のチップ又はチップ群の露光を行う。この動作を繰
り返して半導体基板全面に回路パターンを焼き付ける。
2. Description of the Related Art In a semiconductor device manufacturing process, a lithography step is a step of projecting a circuit pattern drawn on a reticle onto a semiconductor substrate in a reduced size by an exposure apparatus called a stepper and printing the circuit pattern. The printing of the circuit pattern is performed by one exposure of a chip group or a chip group including a plurality of chips, and the exposure part is sequentially moved to perform exposure of a subsequent chip or a chip group. This operation is repeated to print a circuit pattern on the entire surface of the semiconductor substrate.

【0003】ところで、リソグラフィ工程における露光
を行う際に、半導体基板の厚さにばらつきがあると、レ
ンズと半導体基板表面との距離が変動し、その変動幅が
ある限度を超えると、いわゆる焦点ずれが生じ、回路パ
ターンがぼけてしまう。この焦点ずれが生じない範囲を
焦点深度Dといい、焦点深度D、解像度R、ステッパの
開口比NA、光源の波長λの間には、 R=K1/NA D=K2×λ/(NA)2 なる関係がある。但し、K1,K2は定数である。解像
度Rは、描画可能な最小線幅に依存し、半導体装置の高
集積化に伴い最小線幅も縮小化が図られている。従っ
て、解像度Rを細かくするには、光源の波長λも短波長
化が必要であり、結果的に焦点深度Dが小さくなる。即
ち、半導体基板に対してはより高精度な平坦度が要求さ
れることになる。
By the way, when the exposure in the lithography process is performed, if the thickness of the semiconductor substrate varies, the distance between the lens and the surface of the semiconductor substrate fluctuates. Occurs and the circuit pattern is blurred. The range in which this defocus does not occur is called the depth of focus D. Between the depth of focus D, the resolution R, the aperture ratio NA of the stepper, and the wavelength λ of the light source, R = K1 / NA D = K2 × λ / (NA) There are two relationships. Here, K1 and K2 are constants. The resolution R depends on the minimum line width that can be drawn, and the minimum line width has been reduced with higher integration of semiconductor devices. Therefore, in order to make the resolution R fine, it is necessary to shorten the wavelength λ of the light source, and as a result, the depth of focus D becomes small. That is, a more accurate flatness is required for the semiconductor substrate.

【0004】そこで、回路パターンが露光される範囲に
おいて、焦点面に対して半導体基板の厚さむらに起因す
る高低差が最も小さくなるように半導体基板を傾斜させ
る動作、即ちレベリングを導入することにより、半導体
基板に要求される平坦度を緩和する機構がステッパに組
み込まれている。
Therefore, in the range where the circuit pattern is exposed, an operation of inclining the semiconductor substrate with respect to the focal plane so as to minimize the height difference caused by the uneven thickness of the semiconductor substrate, that is, leveling is introduced. A mechanism for reducing the flatness required for a semiconductor substrate is incorporated in a stepper.

【0005】図4は、従来のステッパにおいて半導体基
板のレベリングを行っている様子を模式的に示した説明
図である。
FIG. 4 is an explanatory view schematically showing a state in which leveling of a semiconductor substrate is performed in a conventional stepper.

【0006】図4に示すように、従来は、予め半導体基
板41表面の裏面に対する平坦度を測定しておき、基板
41表面全体にわたる露光面S41に対して、基板41
各部における焦点ずれが可能な限り小さくなるような角
度に基板41を傾斜させるレベリングを行いながら、一
度に基板41表面全体の露光を行っていた。
As shown in FIG. 4, conventionally, the flatness of the front surface of the semiconductor substrate 41 is measured in advance, and the exposed surface S41 over the entire surface of the substrate 41 is compared with the substrate 41.
The entire surface of the substrate 41 has been exposed at one time while performing leveling for inclining the substrate 41 at an angle that minimizes the defocus at each part.

【0007】一方、半導体装置の高集積化の進展速度が
速いために、描画できる最小線幅の縮小化が図られて
も、チップ面積は増大してきている。従って、ステッパ
でより大きい面積の領域をより小さい解像度で描画する
必要を生じ、より大口径で収差の少ないレンズを使用す
る必要がある。しかし、このことはステッパ・レンズ系
の設計に大きな負担がかかるばかりでなく、ステッパの
コストが大幅に増加する。
On the other hand, since the rate of progress of high integration of semiconductor devices is high, even if the minimum line width that can be drawn is reduced, the chip area is increasing. Therefore, it becomes necessary to draw a region having a larger area with a stepper with a smaller resolution, and it is necessary to use a lens having a larger diameter and less aberration. However, this not only places a heavy burden on the design of the stepper lens system, but also greatly increases the cost of the stepper.

【0008】そこで、ある回路パターンを半導体基板上
に露光する際、レチクル上のパターンを一度に露光する
のではなく、パターンの一部分をスキャンしながら露光
するスキャン露光が考え出された。このスキャン露光に
より、ステッパにとっては小さいレンズを使用すること
ができるようになり、半導体基板にとっては露光単位面
積の縮小による実質的な平坦度が向上することになっ
た。
Therefore, when a certain circuit pattern is exposed on a semiconductor substrate, a scan exposure method has been devised in which a pattern on a reticle is exposed while scanning a part of the pattern instead of exposing the pattern at once. By this scanning exposure, a small lens can be used for the stepper, and the substantial flatness of the semiconductor substrate can be improved by reducing the exposure unit area.

【0009】しかし、スキャン露光においては、前述の
レベリングをしながら露光を行なうとすると、露光単位
面積が小さいことから、より表面形状に適合するように
半導体基板が傾斜させられるため、レベリング時におけ
る半導体基板の傾斜角度が大きくなることがある。即
ち、半導体基板の厚さむらが同程度でも、スキャンを行
わない従来のステッパに比較して、よりレベリング角度
が大きくなることがあり得る。
However, in the case of scanning exposure, if the exposure is performed while performing the above-described leveling, the semiconductor substrate is tilted so as to conform to the surface shape because the unit area of the exposure is small. The inclination angle of the substrate may increase. That is, even if the thickness unevenness of the semiconductor substrate is almost the same, the leveling angle may be larger than that of a conventional stepper that does not perform scanning.

【0010】図5は、スキャン露光ステッパにおいて半
導体基板のレベリングを行っている様子を模式的に示し
た説明図である。
FIG. 5 is an explanatory diagram schematically showing a state in which a semiconductor substrate is leveled in a scan exposure stepper.

【0011】従来のスキャン露光においては、予め半導
体基板全体としての平坦度を測定しておき、図5(A)
に示すように、その測定結果に基づき、従来と同様に、
露光面S51Aに対する焦点ずれを可能な限り小さくす
べく、半導体基板51を傾斜させてレベリングを行う。
ところが、スキャン露光のために露光対象領域が移動し
て、図5(B)に示すように、半導体基板51表面の勾
配が急な部分において、上記同様、予め半導体基板全体
としての平坦度を測定した結果に基づき、露光面S51
Bに対する焦点ずれを可能な限り小さくすべく、レベリ
ングを行おうとすると、半導体基板51の傾斜角度が非
常に大きくなってしまう。
In the conventional scan exposure, the flatness of the whole semiconductor substrate is measured in advance, and FIG.
As shown in the figure, based on the measurement results,
The leveling is performed by tilting the semiconductor substrate 51 so as to minimize the defocus with respect to the exposure surface S51A.
However, as shown in FIG. 5B, the exposure target area moves for scan exposure, and the flatness of the entire semiconductor substrate is measured in advance in a portion where the surface of the semiconductor substrate 51 has a steep gradient, as described above. Based on the result, the exposure surface S51
If an attempt is made to perform leveling in order to minimize the defocus with respect to B, the inclination angle of the semiconductor substrate 51 becomes extremely large.

【0012】しかし、ステッパのレベリングの角度は、
所定水準のスループットを確保すること等のために無制
限ではなく、例えば40μradといった限界がある。
従って、レベリングが表面形状の変化に対応できなくな
り、焦点面が対象とする単位露光面の最適面に適合させ
られないレベリングエラーが生じ、結果として焦点ずれ
によるパターンぼけを引き起こす可能性がある。即ち、
厚さむらだけでなく、表面形状の勾配をも考慮する必要
がある。
However, the leveling angle of the stepper is
It is not unlimited to ensure a predetermined level of throughput, and has a limit of, for example, 40 μrad.
Therefore, leveling cannot cope with a change in surface shape, and a leveling error occurs in which the focal plane cannot be adjusted to the optimum plane of the target unit exposure plane, which may result in pattern blur due to defocus. That is,
It is necessary to consider not only the thickness unevenness but also the gradient of the surface shape.

【0013】一方、半導体基板の平坦度の定義として
は、裏面を基準として半導体基板の厚さのむらの絶対値
を表すLTV(Local Thickness Variation)と、表面
を基準としたS−TIR(Surface Total Indicato
r),S−FPD(Surface Focal Plane Deviation)が
広く用いられている。前述のレベリング機構のあるステ
ッパに対応するのはS−TIRであるが、これは、所定
の正方形又は長方形について、表面に対してある面から
表面までの差(距離)が最小になるように基準面を設定
し、その基準面に対する表面の高低差の和(peak to va
lley)を表したものである。しかし、これはある固定さ
れた領域に対する値なので、スキャンを行わない従来の
ステッパには対応するが、スキャンには対応しない。即
ち、これらはある固定された領域の平坦度を表すもので
あり、スキャン露光のように領域が移動していった場合
のことは考慮されていない。しかも、スキャン型ステッ
パでは、先に述べたようにレベリング角、従って、半導
体基板表面の勾配が重要になる。勾配を直接測定する方
法では、半導体基板裏面を絶対的な基準平面に一致させ
る必要があるが、半導体基板裏面に微小な粒子が付着し
ているとその部分が盛り上がり正確な測定をすることが
できない。この場合、ステッパの半導体基板保持治具等
を利用することにより解決は可能であるが、半導体基板
製造工程に新たにこれを導入することは、検査コストの
増大を招き、結果として半導体基板価格上昇につなが
る。
On the other hand, the flatness of the semiconductor substrate is defined as LTV (Local Thickness Variation) representing the absolute value of the thickness unevenness of the semiconductor substrate with respect to the back surface, and S-TIR (Surface Total Indicator) with reference to the front surface.
r), S-FPD (Surface Focal Plane Deviation) is widely used. Corresponding to a stepper with the leveling mechanism described above is S-TIR, which is a reference for a given square or rectangle such that the difference (distance) from one surface to the other with respect to the surface is minimized. A plane is set, and the sum of the height difference of the surface with respect to the reference plane (peak to va
lley). However, since this is a value for a fixed area, it corresponds to a conventional stepper that does not perform scanning, but does not correspond to scanning. That is, they represent the flatness of a fixed area, and do not take into account the case where the area moves like scanning exposure. In addition, in the scan type stepper, as described above, the leveling angle and, therefore, the gradient of the surface of the semiconductor substrate are important. In the method of directly measuring the gradient, the back surface of the semiconductor substrate needs to coincide with an absolute reference plane. However, if minute particles adhere to the back surface of the semiconductor substrate, the portion rises and accurate measurement cannot be performed. . In this case, the problem can be solved by using a semiconductor substrate holding jig of a stepper, but introduction of a new one into the semiconductor substrate manufacturing process causes an increase in inspection cost, and as a result, a semiconductor substrate price rises Leads to.

【0014】さらに、半導体基板は表面を鏡面加工する
が、これはコロイダルシリカに代表される研磨剤を用
い、ウレタン、不織布等の研磨布上で研磨する。このと
き、荷重をかけるので、半導体基板は少なからず研磨布
にめり込んだ状態になり、半導体基板の外周部分がより
選択的に研磨され、いわゆる「ダレ」が発生する。ダレ
の存在により半導体基板周縁部は、前述の勾配がきつく
なることになり、レベリングエラー発生の可能性が高く
なる。
Further, the surface of the semiconductor substrate is mirror-finished, and is polished on a polishing cloth such as urethane or non-woven fabric using an abrasive represented by colloidal silica. At this time, since a load is applied, the semiconductor substrate is more or less immersed in the polishing cloth, and the outer peripheral portion of the semiconductor substrate is more selectively polished, so-called "sagging" occurs. Due to the sagging, the peripheral portion of the semiconductor substrate has the above-mentioned gradient steep, and the possibility of occurrence of a leveling error increases.

【0015】本発明は上記問題点に鑑みてなされたもの
で、その目的は、スキャン型ステッパにおけるレベリン
グエラーを回避することが可能な半導体基板の平坦度の
測定方法及び測定装置を提供することである。
The present invention has been made in view of the above problems, and an object of the present invention is to provide a method and an apparatus for measuring the flatness of a semiconductor substrate which can avoid a leveling error in a scan type stepper. is there.

【0016】[0016]

【課題を解決するための手段】本発明に係る半導体基板
の測定方法及び測定装置によれば、半導体基板に回路パ
ターンを露光する露光単位領域を順次移動させながら回
路パターンの露光を行うに際し、露光焦点面に対する半
導体基板表面の高低差が小さくなるように半導体基板を
傾斜させて露光焦点面を定めるために半導体基板の平坦
度を測定する半導体基板の測定方法において、露光単位
領域の面積以下の面積とした測定単位領域ごとに半導体
基板の平坦度を測定することを特徴とし、この構成によ
り、半導体基板表面の凹凸の周期が小さくなるに従い、
レベリングの傾斜角が小さくなるので、従来より使用さ
れている厚さ測定器を改変することなく、半導体基板表
面の平坦度の測定を行うことができ、半導体基板全体と
しての裏面基準のパラメータであるLTV測定に比較し
て、レベリングエラー発生率を低減することができる。
According to a method and an apparatus for measuring a semiconductor substrate according to the present invention, when exposing a circuit pattern while sequentially moving an exposure unit area for exposing the circuit pattern on the semiconductor substrate, In a semiconductor substrate measuring method for measuring the flatness of a semiconductor substrate to incline the semiconductor substrate so as to reduce the height difference of the semiconductor substrate surface with respect to the focal plane and to determine an exposure focal plane, an area equal to or less than an area of an exposure unit region It is characterized by measuring the flatness of the semiconductor substrate for each measurement unit region, and according to this configuration, as the period of the irregularities on the surface of the semiconductor substrate becomes smaller,
Since the inclination angle of the leveling is reduced, it is possible to measure the flatness of the surface of the semiconductor substrate without modifying the conventionally used thickness measuring device, which is a parameter based on the back surface of the entire semiconductor substrate. The leveling error occurrence rate can be reduced as compared with the LTV measurement.

【0017】レベリングの基準面を的確に定めるために
は、測定単位領域は、露光単位領域が移動させられる第
1の方向に垂直な第2の方向における長さが、第1の方
向における長さ以上の長さであることとするとよい。
In order to accurately define the leveling reference plane, the measurement unit area has a length in a second direction perpendicular to the first direction in which the exposure unit area is moved, and a length in the first direction. The length should be longer than the above.

【0018】また、スキャン露光に対応して、測定単位
領域を、露光単位領域が移動させられる第1の方向に順
次移動させながら、半導体基板の平坦度の測定を行うと
よい。
Further, it is preferable to measure the flatness of the semiconductor substrate while sequentially moving the measurement unit area in the first direction in which the exposure unit area is moved in response to the scan exposure.

【0019】高精度のレベリング制御を行うためには、
第1の測定単位領域と、第1の測定単位領域の次に測定
が行われる第2の測定単位領域とは、各面積の半分以上
が相互に重複していることとするとよい。
In order to perform high-precision leveling control,
The first measurement unit region and the second measurement unit region in which measurement is performed next to the first measurement unit region may have at least half of each area overlapping each other.

【0020】[0020]

【発明の実施の形態】以下、本発明に係る半導体基板の
測定方法及び測定装置の実施の形態について、図面を参
照しながら説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of a method and an apparatus for measuring a semiconductor substrate according to the present invention will be described below with reference to the drawings.

【0021】本発明に係る半導体基板の測定方法及び測
定装置においては、レベリングのための半導体基板表面
の平坦度の測定を、露光単位領域の面積以下の面積とし
た測定単位領域ごとに行う。
In the method and apparatus for measuring a semiconductor substrate according to the present invention, the measurement of the flatness of the surface of the semiconductor substrate for leveling is performed for each measurement unit area having an area equal to or less than the area of the exposure unit area.

【0022】最初に、本発明に係る半導体基板の測定方
法及び測定装置におけるレベリングと半導体基板表面の
凹凸の周期との関係について説明する。ここでは、説明
の簡単のため、1次元の場合について説明する。
First, the relationship between the leveling and the period of the irregularities on the semiconductor substrate surface in the method and apparatus for measuring a semiconductor substrate according to the present invention will be described. Here, a one-dimensional case will be described for simplicity.

【0023】図1は、本発明に係る半導体基板の測定方
法及び測定装置におけるレベリングと半導体基板表面の
凹凸の周期との関係を模式的に表した説明図である。
FIG. 1 is an explanatory diagram schematically showing the relationship between the leveling and the period of irregularities on the surface of a semiconductor substrate in the method and apparatus for measuring a semiconductor substrate according to the present invention.

【0024】半導体基板表面の凹凸の周期をX、振幅を
A、露光単位領域長をLとし、また、測定単位領域長は
露光単位領域長Lと等しいものとする。基板表面の勾配
が最も急になるのは凹部と凸部との中間の部分であり、
その勾配は2Aπ/Xとなる。また、LTV=2Aとな
るから、勾配はLTVπ/Xとも表記することができ
る。図1(A)に示すように、半導体基板11表面の凹
凸の周期Xが、露光単位領域長Lに対し十分長い場合
は、表面凹凸に対するレベリングの基準面S11は凹部
と凸部との中間の部分の勾配に等しい。図1(B)に示
すように、半導体基板12表面の凹凸の周期Xが短くな
るに従い、レベリングの基準面S12の勾配は凹部と凸
部との中間の部分の勾配(LTVπ/X)より小さくな
り、図1(C)に示すように、半導体基板13表面の凹
凸の周期Xが露光単位領域長L未満になると、レベリン
グの基準面S13は水平になる。
It is assumed that the period of the unevenness on the surface of the semiconductor substrate is X, the amplitude is A, the length of the exposure unit area is L, and the length of the measurement unit area is equal to the length L of the exposure unit area. The steepest slope of the substrate surface is in the middle between the concave and convex parts,
The gradient is 2Aπ / X. Further, since LTV = 2A, the gradient can also be expressed as LTVπ / X. As shown in FIG. 1A, when the period X of the irregularities on the surface of the semiconductor substrate 11 is sufficiently long with respect to the exposure unit region length L, the reference surface S11 for leveling the surface irregularities is located between the concave portion and the convex portion. Equal to the gradient of the part. As shown in FIG. 1B, as the period X of the irregularities on the surface of the semiconductor substrate 12 becomes shorter, the gradient of the leveling reference surface S12 becomes smaller than the gradient (LTVπ / X) between the concave portion and the convex portion. As shown in FIG. 1C, when the period X of the irregularities on the surface of the semiconductor substrate 13 becomes smaller than the exposure unit region length L, the leveling reference plane S13 becomes horizontal.

【0025】以上のように、本発明に係る半導体基板の
測定方法及び測定装置においては、レベリングのための
半導体基板表面の平坦度の測定を、露光単位領域の面積
以下の面積とした測定単位領域ごとに行い、レベリング
の基準面を定めることとしたので、従来より使用されて
いる厚さ測定器を改変することなく、半導体基板表面の
平坦度の測定を行うことができ、半導体基板全体として
の裏面基準のパラメータであるLTV測定に比較して、
レベリングエラー発生率を低減することができる。
As described above, in the method and apparatus for measuring a semiconductor substrate according to the present invention, the measurement of the flatness of the surface of the semiconductor substrate for leveling is performed in a measurement unit area having an area equal to or less than the area of the exposure unit area. The leveling reference plane is determined every time, so that the flatness of the semiconductor substrate surface can be measured without modifying the conventionally used thickness measuring device, and the entire semiconductor substrate can be measured. Compared to the LTV measurement, which is a parameter based on the back side,
The leveling error occurrence rate can be reduced.

【0026】実際には、レベリングのための半導体基板
表面の平坦度の測定は、2次元の測定単位領域で行う。
In practice, the measurement of the flatness of the surface of the semiconductor substrate for leveling is performed in a two-dimensional measurement unit area.

【0027】図2は、本発明に係る半導体基板の測定方
法及び測定装置におけるレベリングのための半導体基板
表面の平坦度の測定を模式的に表した説明図である。
FIG. 2 is an explanatory view schematically showing the measurement of the flatness of the surface of the semiconductor substrate for leveling in the method and apparatus for measuring a semiconductor substrate according to the present invention.

【0028】図2(a)に示すように、ここでは、露光
単位領域は横Xmm、縦Ymmの領域、測定単位領域
は、スキャン露光におけるスキャン方向である横方向に
おける長さがL1mm(L1=X)、スキャン方向に垂
直な方向である縦方向における長さがL2mm(L2≦
Y)の領域S21とする。即ち、測定単位領域は露光単
位領域面積以下の面積である。但し、レベリングの基準
面を的確に定めるためには、縦方向の長さは横方向の長
さより長くするとよい。
As shown in FIG. 2A, here, the exposure unit area has a width of X mm and a length of Y mm, and the measurement unit area has a length of L1 mm (L1 = L1 mm) in the scanning direction in the scanning exposure. X), the length in the vertical direction perpendicular to the scanning direction is L2 mm (L2 ≦
A region S21 in FIG. That is, the measurement unit region has an area equal to or less than the exposure unit region area. However, in order to accurately determine the reference plane for leveling, the length in the vertical direction should be longer than the length in the horizontal direction.

【0029】この測定単位領域S21ごとにLTV測定
を行ってレベリングの基準面を測定単位領域S21ごと
に定め、図2(b)に示すように、測定単位領域をS2
1a、S21b、S21cと順次移動させて、同様に測
定を行いレベリングの基準面を定める。測定単位領域の
移動は、例えば、測定単位領域S21aとS21b、測
定単位領域S21bとS21cが、それぞれ少なくとも
横方向の長さL1/2の領域だけ重複するように行う。
これにより、高精度のレベリング制御を行うことができ
る。
An LTV measurement is performed for each measurement unit area S21 to determine a leveling reference plane for each measurement unit area S21. As shown in FIG.
1a, S21b, and S21c are sequentially moved, measurement is performed in the same manner, and a leveling reference plane is determined. The movement of the measurement unit area is performed, for example, so that the measurement unit areas S21a and S21b and the measurement unit areas S21b and S21c overlap at least an area having a length L1 / 2 in the horizontal direction.
Thus, highly accurate leveling control can be performed.

【0030】図2における横方向にのみ基板表面の凹凸
があるとすると、レベリングの傾斜角θは、θ=LTV
/L1となる。
Assuming that there are irregularities on the substrate surface only in the horizontal direction in FIG. 2, the inclination angle θ of leveling is given by θ = LTV
/ L1.

【0031】[0031]

【実施例】以下に、本発明の実施例を詳細に述べる。チ
ョコラルスキ法によりシリコンの単結晶を引き上げ、こ
の単結晶をスライス、ラップ、エッチング、鏡面研磨の
工程により、直径200mm、厚さ目標725μmの片
面鏡面半導体基板100枚を加工した。次に、これらの
半導体基板の静電容量式厚さ測定器で半導体基板の厚さ
分布を測定することにより平坦度を評価した。評価条件
は横8mm、縦8mmの領域を測定単位領域とするLT
Vの測定と、横8mm、縦24mmの領域を測定単位領
域とするS−TIRの測定とを行った。さらに、スキャ
ン露光のレベリングに対応して、横8mm、縦8mmの
領域を測定単位領域とし、後の露光時におけるスキャン
方向に測定単位領域を1mmずつ移動させながらLTV
の測定を行った。
Embodiments of the present invention will be described below in detail. A silicon single crystal was pulled up by the Czochralski method, and this single crystal was processed into 100 single-sided mirror-surface semiconductor substrates having a diameter of 200 mm and a target thickness of 725 μm by slicing, lapping, etching, and mirror polishing. Next, the flatness was evaluated by measuring the thickness distribution of the semiconductor substrate using a capacitance type thickness measuring instrument for these semiconductor substrates. The evaluation condition is LT in which an area of 8 mm in width and 8 mm in height is set as a measurement unit area.
The measurement of V and the measurement of S-TIR using an area of 8 mm in width and 24 mm in length as a measurement unit area were performed. Further, in correspondence with the leveling of the scanning exposure, an area of 8 mm in width and 8 mm in height is used as a measurement unit area, and the LTV is moved while moving the measurement unit area by 1 mm in the scanning direction at the time of subsequent exposure.
Was measured.

【0032】いずれの半導体基板もS−TIR測定値は
0.2μm以下であり、焦点ずれは、発生しない。一
方、LTV測定値については、横8mm、縦8mmの測
定単位領域を従来のように順次測定したところ、LTV
≦0.32μmの条件を満たさない半導体基板は10枚
あった(これをAグループとする。)。次に、残りの9
0枚について、横8mm、縦8mmの測定単位領域を、
後の露光時におけるスキャン方向に1mmずつ移動させ
ながら測定を行ったところ、LTV≦0.32μmの条
件を満たさない半導体基板は40枚あった(これをBグ
ループとする。)。先の従来のような測定でLTV≦
0.32μmの条件を満たした半導体基板であっても、
測定単位領域を1mmずつ移動させていくと、平坦度の
悪い部分が1つの測定単位領域に含まれるようになるこ
とがあるため、このようなことが起こる。さらに残りの
半導体基板50枚をCグループとする。
The S-TIR measurement value of each semiconductor substrate is 0.2 μm or less, and no defocus occurs. On the other hand, with respect to the LTV measurement value, when the measurement unit area of 8 mm in width and 8 mm in height was sequentially measured as in the past, the LTV
There were 10 semiconductor substrates that did not satisfy the condition of ≦ 0.32 μm (this is referred to as Group A). Next, the remaining 9
For 0 sheets, the measurement unit area of 8 mm wide and 8 mm long is
When the measurement was performed while moving by 1 mm in the scanning direction at the time of the subsequent exposure, there were 40 semiconductor substrates that did not satisfy the condition of LTV ≦ 0.32 μm (this is referred to as Group B). LTV ≦
Even if the semiconductor substrate satisfies the condition of 0.32 μm,
When the measurement unit area is moved by 1 mm at a time, a portion having poor flatness may be included in one measurement unit area, so this occurs. Further, the remaining 50 semiconductor substrates are set as a C group.

【0033】次に、0.20μm幅の線が0.40μm
ピッチで描画される回路パターンをスキャン型ステッパ
を用いて半導体基板上に露光した。単位露光領域は横8
mm、縦24mmの領域であり、横32mm、縦24m
mの領域を1ショットとして露光を行った。その後、測
定された平坦度に対して、焦点ずれによるパターンぼけ
発生の有無を確認したところ、LTV測定値が悪かった
ところではパターンぼけが発生していた。即ち、Aグル
ープの半導体基板においては、レベリングエラーが発生
してパターンボケが生じていた。Bグループの半導体基
板においては、測定単位領域をスキャン方向に1mmず
つ移動させながらの測定でLTV≦0.32μmの条件
を満たさなかった領域でレベリングエラーに起因する焦
点ずれによるパターンぼけが発生していた。Cグループ
の半導体基板においては、レベリングエラーは発生せ
ず、半導体基板表面の凹凸に起因するパターンボケは発
生していなかった。
Next, a line having a width of 0.20 μm is
A circuit pattern drawn at a pitch was exposed on a semiconductor substrate using a scan type stepper. The unit exposure area is horizontal 8
mm, 24 mm long, 32 mm wide, 24 m long
Exposure was performed with the area of m being one shot. After that, the presence or absence of pattern blurring due to defocus was checked with respect to the measured flatness. The pattern blurring occurred where the LTV measurement value was poor. That is, in the semiconductor substrate of the group A, a leveling error has occurred and a pattern blur has occurred. In the semiconductor substrate of the B group, pattern blurring due to defocus due to a leveling error has occurred in a region where the condition of LTV ≦ 0.32 μm was not satisfied in the measurement while moving the measurement unit region by 1 mm in the scanning direction. Was. No leveling error occurred in the semiconductor substrate of Group C, and no pattern blur due to the unevenness of the surface of the semiconductor substrate occurred.

【0034】図3は、本発明に係る半導体基板の測定方
法及び測定装置におけるLTV測定値と回路パターンぼ
け発生率との関係を示したグラフである。
FIG. 3 is a graph showing the relationship between the LTV measurement value and the occurrence rate of circuit pattern blur in the method and apparatus for measuring a semiconductor substrate according to the present invention.

【0035】上記実施例においては、レベリングのため
のLTV測定の測定単位領域を横L1=8mm、縦L2
=mmとしており、また、スキャン露光ステッパのレベ
リングの最大傾斜角は40μradであるので、横方向
にのみ基板表面の凹凸があるとするとLTV=θ×L1
より、LTV測定値がθ×L1=0.32μm以下のと
きは回路パターンぼけは発生しないが、LTV測定値が
θ×L1=0.32μmを超えると、回路パターンぼけ
発生率が急激に増加することがわかる。
In the above embodiment, the measurement unit area for LTV measurement for leveling is L1 = 8 mm in width and L2 in length.
= Mm, and the maximum inclination angle of the leveling of the scan exposure stepper is 40 μrad. Therefore, if there is unevenness on the substrate surface only in the lateral direction, LTV = θ × L1
Therefore, when the LTV measurement value is θ × L1 = 0.32 μm or less, the circuit pattern blur does not occur. However, when the LTV measurement value exceeds θ × L1 = 0.32 μm, the circuit pattern blur occurrence rate sharply increases. You can see that.

【0036】[0036]

【発明の効果】本発明に係る半導体基板の測定方法及び
測定装置によれば、半導体基板に回路パターンを露光す
る露光単位領域を順次移動させながら回路パターンの露
光を行うに際し、露光焦点面に対する半導体基板表面の
高低差が小さくなるように半導体基板を傾斜させて露光
焦点面を定めるために半導体基板の平坦度を測定する半
導体基板の測定方法において、露光単位領域の面積以下
の面積とした測定単位領域ごとに半導体基板の平坦度を
測定することとしたので、リソグラフィ工程において、
露光時のショット領域内の平坦度内のみならず、基板表
面の裏面に対する勾配の影響により、レベリングエラー
が発生して焦点ずれによるパターンぼけが発生するのを
防止することができる。その結果、層間絶縁膜の平坦化
(CMP)においても研磨布に対する追従性に起因した
研磨むらが抑制され、膜厚分布が均一になる等、半導体
装置製造における特性不良発生を抑制し、高歩留まりで
信頼性の高いデバイスを得ることができる。
According to the method and the apparatus for measuring a semiconductor substrate according to the present invention, when exposing a circuit pattern while sequentially moving an exposure unit area for exposing the circuit pattern on the semiconductor substrate, the semiconductor is positioned with respect to the exposure focal plane. In a method of measuring the flatness of a semiconductor substrate, in which a semiconductor substrate is inclined so that a difference in height of the substrate surface is reduced so as to define an exposure focal plane, a measurement unit having an area equal to or less than an area of an exposure unit region. Since the flatness of the semiconductor substrate was measured for each region, in the lithography process,
It is possible to prevent the occurrence of a leveling error and the occurrence of pattern blur due to defocus due to the influence of the gradient on the back surface of the substrate surface as well as within the flatness in the shot region at the time of exposure. As a result, even in the planarization (CMP) of the interlayer insulating film, uneven polishing due to the ability to follow the polishing cloth is suppressed, and the occurrence of characteristic defects in semiconductor device manufacturing such as uniform film thickness distribution is suppressed, and high yield is achieved. Thus, a highly reliable device can be obtained.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明に係る半導体基板の測定方法及び測定装
置におけるレベリングと半導体基板表面の凹凸の周期と
の関係を模式的に表した説明図。
FIG. 1 is an explanatory view schematically showing a relationship between leveling and a period of irregularities on a semiconductor substrate surface in a method and an apparatus for measuring a semiconductor substrate according to the present invention.

【図2】本発明に係る半導体基板の測定方法及び測定装
置におけるレベリングのための半導体基板表面の平坦度
の測定を模式的に表した説明図。
FIG. 2 is an explanatory view schematically showing the measurement of the flatness of the surface of the semiconductor substrate for leveling in the method and apparatus for measuring a semiconductor substrate according to the present invention.

【図3】本発明に係る半導体基板の測定方法及び測定装
置におけるLTV測定値と回路パターンぼけ発生率との
関係を示したグラフ。
FIG. 3 is a graph showing a relationship between an LTV measurement value and a circuit pattern blurring occurrence rate in the method and apparatus for measuring a semiconductor substrate according to the present invention.

【図4】従来のステッパにおいて半導体基板のレベリン
グを行っている様子を模式的に示した説明図。
FIG. 4 is an explanatory view schematically showing a state in which leveling of a semiconductor substrate is performed in a conventional stepper.

【図5】スキャン露光ステッパにおいて半導体基板のレ
ベリングを行っている様子を模式的に示した説明図。
FIG. 5 is an explanatory view schematically showing a state where leveling of a semiconductor substrate is performed in a scan exposure stepper.

【符号の説明】[Explanation of symbols]

11,12,13,21,41,51 半導体基板 S11,S12,S13 レベリングの基準面 S21,S21a,S21b,S21c 測定単位領域 S41,S51A,S51B 露光面 11, 12, 13, 21, 41, 51 Semiconductor substrate S11, S12, S13 Reference surface for leveling S21, S21a, S21b, S21c Measurement unit area S41, S51A, S51B Exposure surface

Claims (8)

【特許請求の範囲】[Claims] 【請求項1】半導体基板に回路パターンを露光する露光
単位領域を順次移動させながら回路パターンの露光を行
うに際し、露光焦点面に対する前記半導体基板表面の高
低差が小さくなるように前記半導体基板を傾斜させて前
記露光焦点面を定めるために半導体基板の平坦度を測定
する半導体基板の測定方法において、 前記露光単位領域の面積以下の面積とした測定単位領域
ごとに前記半導体基板の平坦度を測定することを特徴と
する半導体基板の測定方法。
When a circuit pattern is exposed while sequentially moving an exposure unit area for exposing the circuit pattern to the semiconductor substrate, the semiconductor substrate is tilted so that a height difference of the semiconductor substrate surface with respect to an exposure focal plane is reduced. In the semiconductor substrate measuring method for measuring the flatness of the semiconductor substrate to determine the exposure focal plane, the flatness of the semiconductor substrate is measured for each measurement unit region having an area equal to or less than the area of the exposure unit region. A method for measuring a semiconductor substrate, comprising:
【請求項2】前記測定単位領域は、前記露光単位領域が
移動させられる第1の方向に垂直な第2の方向における
長さが、前記第1の方向における長さ以上の長さである
ことを特徴とする請求項1に記載の半導体基板の測定方
法。
2. The measurement unit area has a length in a second direction perpendicular to a first direction in which the exposure unit area is moved, which is equal to or longer than the length in the first direction. The method for measuring a semiconductor substrate according to claim 1, wherein:
【請求項3】前記測定単位領域を、前記露光単位領域が
移動させられる第1の方向に順次移動させながら、前記
半導体基板の平坦度の測定を行うことを特徴とする請求
項1又は2に記載の半導体基板の測定方法。
3. The flatness of the semiconductor substrate is measured while sequentially moving the measurement unit region in a first direction in which the exposure unit region is moved. The method for measuring a semiconductor substrate according to the above.
【請求項4】第1の前記測定単位領域と、前記第1の前
記測定単位領域の次に測定が行われる第2の前記測定単
位領域とは、各面積の半分以上が相互に重複しているこ
とを特徴とする請求項3に記載の半導体基板の測定方
法。
4. The first measurement unit region and the second measurement unit region in which measurement is performed next to the first measurement unit region have at least half of their respective areas overlapping each other. 4. The method for measuring a semiconductor substrate according to claim 3, wherein:
【請求項5】半導体基板に回路パターンを露光する露光
単位領域を順次移動させながら回路パターンの露光を行
うに際し、露光焦点面に対する前記半導体基板表面の高
低差が小さくなるように前記半導体基板を傾斜させて前
記露光焦点面を定めるために半導体基板の平坦度を測定
する半導体基板の測定装置において、 前記露光単位領域の面積以下の面積とした測定単位領域
ごとに前記半導体基板の平坦度を測定することを特徴と
する半導体基板の測定装置。
5. When exposing a circuit pattern while sequentially moving an exposure unit area for exposing the circuit pattern on the semiconductor substrate, the semiconductor substrate is tilted so that a height difference of the semiconductor substrate surface with respect to an exposure focal plane is reduced. In the semiconductor substrate measuring apparatus for measuring the flatness of the semiconductor substrate to determine the exposure focal plane, the flatness of the semiconductor substrate is measured for each measurement unit area having an area equal to or less than the area of the exposure unit area. An apparatus for measuring a semiconductor substrate, comprising:
【請求項6】前記測定単位領域は、前記露光単位領域が
移動させられる第1の方向に垂直な第2の方向における
長さが、前記第1の方向における長さ以上の長さである
ことを特徴とする請求項5に記載の半導体基板の測定装
置。
6. The measurement unit area has a length in a second direction perpendicular to the first direction in which the exposure unit area is moved, which is equal to or longer than the length in the first direction. The apparatus for measuring a semiconductor substrate according to claim 5, wherein:
【請求項7】前記測定単位領域を、前記露光単位領域が
移動させられる第1の方向に順次移動させながら、前記
半導体基板の平坦度の測定を行うことを特徴とする請求
項5又は6に記載の半導体基板の測定装置。
7. The semiconductor device according to claim 5, wherein the flatness of the semiconductor substrate is measured while sequentially moving the measurement unit area in a first direction in which the exposure unit area is moved. The apparatus for measuring a semiconductor substrate according to claim 1.
【請求項8】第1の前記測定単位領域と、前記第1の前
記測定単位領域の次に測定が行われる第2の前記測定単
位領域とは、各面積の半分以上が相互に重複しているこ
とを特徴とする請求項7に記載の半導体基板の測定装
置。
8. The first measurement unit region and the second measurement unit region in which measurement is performed next to the first measurement unit region have at least half of their areas overlapping each other. The apparatus for measuring a semiconductor substrate according to claim 7, wherein:
JP11067099A 1999-03-12 1999-03-12 Method and device for measuring semiconductor substrate Pending JP2000260840A (en)

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Cited By (6)

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WO2003025999A1 (en) * 2001-09-14 2003-03-27 Shin-Etsu Handotai Co., Ltd. Wafer shape evaluating method, wafer, and wafer selecting method
US6925860B1 (en) 2003-02-21 2005-08-09 Nanometrics Incorporated Leveling a measured height profile
KR100889843B1 (en) * 2006-06-14 2009-03-20 캐논 가부시끼가이샤 Scanning exposure apparatus and device manufacturing method
CN102193321A (en) * 2010-03-05 2011-09-21 上海微电子装备有限公司 Controlling method and controlling loop of workpiece-stage vertical position
CN108873599A (en) * 2017-05-08 2018-11-23 信越化学工业株式会社 Large-size synthetic quartz glass substrate, evaluation method and manufacturing method
CN114384770A (en) * 2020-10-22 2022-04-22 中国科学院微电子研究所 Wafer alignment method, wafer alignment device and semiconductor device

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003025999A1 (en) * 2001-09-14 2003-03-27 Shin-Etsu Handotai Co., Ltd. Wafer shape evaluating method, wafer, and wafer selecting method
US6975960B2 (en) 2001-09-14 2005-12-13 Shin-Etsu Handotai Co., Ltd. Method for evaluating wafer configuration, wafer, and wafer sorting method
US6925860B1 (en) 2003-02-21 2005-08-09 Nanometrics Incorporated Leveling a measured height profile
KR100889843B1 (en) * 2006-06-14 2009-03-20 캐논 가부시끼가이샤 Scanning exposure apparatus and device manufacturing method
US7710543B2 (en) 2006-06-14 2010-05-04 Canon Kabushiki Kaisha Scanning exposure apparatus and device manufacturing method
CN102193321A (en) * 2010-03-05 2011-09-21 上海微电子装备有限公司 Controlling method and controlling loop of workpiece-stage vertical position
CN108873599A (en) * 2017-05-08 2018-11-23 信越化学工业株式会社 Large-size synthetic quartz glass substrate, evaluation method and manufacturing method
US11591260B2 (en) 2017-05-08 2023-02-28 Shin-Etsu Chemical Co., Ltd. Large-size synthetic quartz glass substrate, evaluation method, and manufacturing method
CN108873599B (en) * 2017-05-08 2024-03-12 信越化学工业株式会社 Large-size synthetic quartz glass substrate, evaluation method, and manufacturing method
CN114384770A (en) * 2020-10-22 2022-04-22 中国科学院微电子研究所 Wafer alignment method, wafer alignment device and semiconductor device
CN114384770B (en) * 2020-10-22 2024-04-02 中国科学院微电子研究所 Wafer alignment method and device and semiconductor device

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